Battery cell with monitoring device, and corresponding operating method

Abstract

A battery cell with a monitoring device including a data processing unit for processing state data of the battery cell as a function of a trigger pulse and a triggering unit, which is connected to the data processing unit, to generate the trigger pulse and to provide the trigger pulse to the data processing unit. The triggering unit is designed to evaluate a measurement signal, which correlates with an electrical energy of the battery cell in order to generate the trigger pulse as a function of the measurement signal. The invention further relates to a battery having such a battery cell as well as to a motor vehicle having such a battery. Furthermore, the invention relates to a method for monitoring at least one such battery cell.

Claims

1. A battery cell with a monitoring device, comprising: a data processing unit for processing state data of the battery cell as a function of a trigger pulse, a triggering unit, which is connected to the data processing unit, for generating the trigger pulse, and provision of the trigger pulse to the data processing unit, wherein the triggering unit is designed to evaluate a measurement signal, which comes from the battery cell and correlates with an electrical energy of the battery cell, and to generate the trigger pulse as a function of the measurement signal, wherein the triggering unit is designed to generate the trigger pulse at a first point in time, at which the battery cell has a first electrical energy content and to generate the trigger pulse at a second point in time, at which the battery cell has a second electrical energy content, wherein the first electrical energy content and the second electrical energy content differ by a pre-definable energy value, and wherein the measurement signal is proportional to an electric current through the battery cell or proportional to an electrical power of the battery cell, wherein the triggering unit has means to generate an integration signal as a function of the measurement signal and when the integration signal falls below or exceeds a pre-definable threshold value, is designed to generate the trigger pulse and to reset the integration signal to a start value.

2. The battery cell according to claim 1, wherein the triggering unit has a first capacitor, which is electrically connected to a first analog input of the data processing unit as well as to a first comparator unit for generating the integration signal, wherein the integration signal can be provided to the first capacitor by a first electric voltage and the comparator unit is designed to generate the trigger pulse upon the exceeding of a pre-definable first threshold value by the first electric voltage at the first capacitor.

3. The battery cell according to claim 2, wherein the first capacitor is electrically connected to a first bidirectional connection terminal (of the data processing unit by way of a first resistor, wherein the first bidirectional connection terminal is designed to take on one of the three following states: low level with an electrically conductive connection to a reference potential of the data processing unit, high level with an electrically conductive connection to a supply potential of the data processing unit, wherein a supply voltage of the data processing unit is present between the supply potential and the reference potential, or nonexistence of a conductive connection.

4. The battery cell according to claim 2, wherein the triggering unit has a second capacitor, which is electrically connected to a second bidirectional connection terminal of the data processing unit by a second resistor and is electrically connected to a second analog input of the data processing unit as well as to a second comparator unit, wherein a reference signal can be provided by a second electric voltage at the second capacitor, and the comparator unit is designed to generate the trigger pulse upon the exceeding of a pre-definable second threshold value by the second electric voltage, wherein the triggering unit has a common current source with a pre-definable constant current, which is designed to impose a compensating current in the first capacitor and in the second capacitor to compensate for self-discharging currents of the first capacitor and of the second capacitor.

5. The battery cell according to claim 4, wherein the triggering unit is designed to reset the second electric voltage to a reference state and to feed an equalization charge quantity to be introduced into the second capacitor also into the first capacitor when the pre-definable second threshold value is exceeded by the second electric voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features and feature combinations listed previously in the description as well as the features and feature combinations listed in the figure description and/or in the figures alone in the following can be used not only in the respectively indicated combination, but also in other combinations, or in isolation, without going beyond the scope of the invention. Thus, there also embodiments that are to be considered comprised and disclosed by the invention, which are not explicitly shown and explained in the figures, but are emphasized and can be created through separate feature combinations from the explained embodiments.

(2) Additional advantages, features, and details of the invention result from the claims, the following description of the preferred embodiments, as well as the drawings: The following is shown:

(3) FIG. 1 shows a schematic representation of an embodiment of a monitoring device of a battery cell in a simplified schematic representation;

(4) FIG. 2 shows a schematic representation of a time progression of characteristic signals of the monitoring device according to FIG. 1, assuming an ideal self-charging compensation;

(5) FIG. 3 shows a schematic representation of a time progression of characteristic signals of the monitoring device according to FIG. 1, assuming a non-ideal self-charging compensation; and

(6) FIG. 4 shows a schematic representation of a time progression of characteristic signals of the monitoring device according to FIG. 1, assuming an uneven self-charging compensation with current drifting apart of a measurement signal and a reference signal;

DETAILED DESCRIPTION OF THE DRAWINGS

(7) FIG. 1 schematically shows a monitoring device 10, as can be used in a battery cell. The monitoring device 10 comprises a data processing unit 12, which is connected to a triggering unit 14. Status data 13 is provided to the data processing unit 12 by sensors in or outside of the battery cell. The triggering unit 14 provides a trigger pulse 15 to an input P1 of the data processing unit 12. This may be an input P1, which enables a so-called wake-up of the data processing unit 12. A measurement signal, which is preferably proportional to an electric current through the battery cell, is supplied as a current signal 17 in a branching point of the triggering unit 14. Additional data can be queried by the data processing unit 12 of an external data source, for example a real-time clock 19 (RTC) or a locating signal 21, for example in the form of a GPS signal (global positioning system).

(8) The triggering unit 14 has a symmetrical arrangement of components. A first capacitor C1, at which a first voltage U1 is present, serves as a measuring capacitor, a second capacitor C2, at which a second voltage U2 is present, serves as a reference capacitor. Both capacitors C1, C2 are based on a common reference potential 11. A first parallel resistor Rp1, which represents a self-discharging of the first capacitor C1, is indicated parallel to the first capacitor C1. In the same manner, a second parallel resistor Rp2, which stands for a self-discharging of the second capacitor C2, is indicated parallel to the second capacitor C2. In order to compensate for the self-discharging by means of the first parallel resistor Rp1 and the second parallel resistor Rp2, a constant current source 18 is provided, which supplies a constant current I1. The constant current I1 is distributed over a first diode D1 and a second diode D2, in which the anodes of the two diodes, D1 and D2, are connected to the constant current source 18. A connection terminal, which is not connected to the reference potential 11, of the first capacitor C1, which is characterized in the following as the upper connection terminal of the first capacitor C1, is connected to a first bidirectional connection terminal I/O1 of the data processing unit 12 by means of a first resistor R1. In the same manner, a connection terminal, which is not connected to the reference potential 11, of the second capacitor C2, which is characterized in the following as the upper connection terminal of the second capacitor C2, is connected to a second bidirectional connection terminal I/O2 of the data processing unit 12 by means of a second resistor R2. The upper connection terminal of the first capacitor C1 is furthermore electrically connected to a first analog input ADC1 of the data processing unit 12 as well as to an input of a first comparator unit 22. Likewise, the upper connection terminal of the second capacitor C2 is connected to a second analog input ADC2 of the data processing unit 12 as well as to an input of the second comparator unit 26.

(9) The cathode of the first diode D1 Is connected to the upper connection terminal of the first capacitor C1 by means of a third resistor R3. In the same manner, the cathode of the second diode D2 is connected to the upper connection terminal of the second capacitor C2 by means of a fourth resistor R4. The first comparator unit 22 provides a signal 23, which indicates a falling below a pre-definable lower threshold value as well as a signal 25, which indicates an exceeding of a pre-definable upper threshold value. In the same manner, the second comparator unit 26 provides a signal 27, which indicates a falling below a pre-definable lower threshold value as well as a signal 29, which indicates an exceeding of a pre-definable upper threshold value. Preferably, the upper and the lower threshold values here can be specified identically for both comparator units, 22 and 26. Furthermore, an upper threshold value and a lower threshold value can be symmetrically classified to a starting state or a reference state of the first capacitor C1 and of the second capacitor C2, which preferably corresponds to half of a supply voltage V/2 (=*supply voltage V). Signals 23, 25, 27, 29 are provided to a logic linkage unit 24, which executes an OR operation and generates the trigger pulse 15 as a result.

(10) FIG. 2 shows a compilation of five graphs, which are represented over a common time axis. Represented are the first voltage U1 at the first capacitor C1 (measuring capacitor), also characterized as the measurement voltage, as well as the second voltage U2 at the second capacitor C2 (reference capacitor), also characterized as the reference voltage. The first voltage U1 and the second voltage U2 may assume a value ranging between 0 and the value of the supply voltage V, which represents an operating voltage of the circuit. Furthermore, a binary operating state signal OP is represented, which characterizes an operating state of the data processing unit 12. With a low level 0, the data processing unit 12 is in a sleep mode, which is characterized by an especially low energy consumption of the data processing unit 12; with a high level 1, the data processing unit 12 is in an operating mode. A transition from sleep mode into operating mode takes place by means of the trigger pulse 15 provided to the input P1. A resetting from operating mode to sleep mode can take place by means of the data processing unit 12 itself, particularly by executing a corresponding program code.

(11) Furthermore, the state of the first bidirectional connection terminal I/O1, which is connected to the first capacitor C1, and of the second bidirectional connection terminal I/O2, which is connected to the second capacitor C2, is represented in a graph, respectively. The three states may be present in this case, namely a high-resistance state Z, in which the first capacitor C1 or the second capacitor C2 remains uninfluenced, a high level 1, in which an electrically conductive connection is established to a supply potential, whereby a charging of capacitor C1 or C2, respectively, takes place. A low level 0 may be present as a further state, in which an electrically conductive connection is established to the reference potential 11, which leads to a discharging of the capacitor C1 or C2, respectively. In particular, there may be a provision that the high level 1 is represented physically by a voltage, which is equal to the supply voltage V.

(12) With a starting state between a time t0 and t1, the second voltage U2 amounts to a constant V/2. In a similar manner, the first voltage U2 likewise amounts to V/2. The operating state signal OP in this case has the low level 0. Both bidirectional connection terminals, I/O1 and I/O2, are in a high-resistance state Z. A supply of current to capacitor C1 then takes place between point in time t1 and point in time t2 through a positive current signal 17. At point in time t2, the first voltage U1 reaches an upper threshold value, which was set to the value of the supply voltage V here for simplification purposes. Thus, a certain energy quantity or charge quantity flows between point in time t1 and point in time t2, which is characterized here as EE. At point in time t2, thus the trigger pulse 15 is provided to the first input P1 of the data processing unit 12, whereby the operating state signal OP switches from the low level 0 to the high level 1. The data processing unit 12 then starts the processing of the status data and resets the first capacitor C1 back to its starting state, namely back to half of the supply voltage V/2 in which the bidirectional connection terminal I/O1 is set at the low level 0. Upon reaching half of the supply voltage V/2 by means of the first voltage U1, the first bidirectional connection terminal I/O1 is reset back to the high-resistance state Z, and the data processing unit 12 can return to sleep mode.

(13) For example, a current flow of the current signal 17 then starts in the opposite direction at a point in time t3. The previously stored energy unit EE or charge quantity is specifically hereby drained between point in time t3 and point in time t4. The first voltage U1 at the first capacitor C1 reaches a lower threshold, which was set to 0 for simplification purposes here, at a point in time t4. As previously in the interval between t2 and t3, a trigger pulse 15 at the first input P1 here starts the data processing unit 12 in order to process the status data. The single difference with respect to the process in interval t2, t3 is the first bidirectional connection terminal I/O1 is then switched to the high level 1, in which a connection exists with the supply voltage V. Once the first voltage U1 at the first capacitor C1 has reached the value of half of the supply voltage V/2, then the original state as found in interval t0, t1 is then present.

(14) FIG. 3 shows the same compilation of graphs, in which now a superimposed drifting apart of the two capacitors, C1 and C2, is also represented. Starting from a starting state, which is between a point in time t10 and a point in time t11, a supply of an energy unit EE again starts at point in time t11. It is now assumed here that a uniform voltage drift takes place in this interval with the two capacitors, C1 and C2, that is the measuring capacitor and the reference capacitor. The first voltage at the first capacitor C1 reaches an upper threshold value at a point in time t12. The logic linkage unit 24 then generates the trigger pulse 15, which is provided to the first input P1 of the data processing unit 12. The data processing unit 12 then determines, by means of the second analog input ADC2, that the second capacitor C2, i.e. the reference capacitor, is no longer at half of the supply voltage V/2. As a result of this, there is no status data processing or storage. In the time interval between t12 and t13, a discharging of the second capacitor C2 then takes place to the target value, namely half of the supply voltage V/2. The first charge quantity drained from the second capacitor C2 for this is characterized as Q0. The equivalent charge quantity Q0 is subsequently also drained from the first capacitor C1 at an interval between t13 and t14. The corresponding states of the bidirectional connection terminals I/O1 and I/O2 are correspondingly low level 0 in the respective interval or otherwise a high-resistance state Z.

(15) In the same manner, a starting state with respectively half of the supply voltage V/2 is present in a further progression between point in time t20 and t21 as a first voltage at the first capacitor and second voltage at the second capacitor. Current drain in the opposite direction then takes place. A requirement here is also that a superimposition of a drift current results in interval t21 and t22, which leads to a progressive discharging of the first capacitor C1 and of the second capacitor C2, which is not covered by the constant current source 18. At point in time t22, the first voltage U1 at the first capacitor C1 reaches the lower threshold value, whereby the trigger pulse 15 is generated, which is provided to the input P1. There is no storage of status data here either, because the second voltage U2 at the second capacitor C2 deviates from the target value of half the supply voltage V/2. Initially, in the time interval t22 to t23, the second voltage U2 at the second capacitor is reset to the target value of half the supply voltage V/2. A second charge quantity Q1 determined here is accordingly also reset back to that of the first capacitor C1. The state of the first bidirectional connection terminal I/O1 in this case is provided by the high level 1 between point in time t23 and t24; the state of the second bidirectional connection terminal I/O2 is provided by the high level 1 between point in time t22 and t23. Otherwise, the high-resistance state Z is present in this section with both bidirectional connection terminals I/O1 and I/O2.

(16) A further superimposed process comprising current drain and drift takes place between a point in time t30 and t31, in which, contrary to the previous cases, a first exceeding of the threshold value takes place here through the second voltage U2 of the second capacitor C2, i.e. of the reference capacitor. In this case as well, no data storage takes place through the data processing unit 12, because the voltage at the second capacitor C2 here does not correspond to the target value of half the supply voltage V/2. In interval t22 to t23, the voltage U2 at the second capacitor C2 is reset to the target value of half the supply voltage V/2. Furthermore, a third charge quantity Q2 in this case is also drained from the first capacitor C1 in interval t23 to t33.

(17) In particular, the phases in which the data processing unit 12 is active, for example between points in time t12 and t14 or points in time t31 and t33, may be very short, for example 200 ns. Reference is made at this juncture to the fact that the times are not being applied to scale. In particular, a time interval t11 to t12 can extend, for example, over a long timeframe, particularly of hours, days, or even weeks. This is particularly the case, for example, when a battery cell is being used with such type of monitoring device in a motor vehicle, which is shut off over a longer period of time.

(18) FIG. 4 shows a case of long-term drift, in which the two capacitors, C1 and C2, have self-discharging that is of differing level. In particular, one of the two capacitors C1, C2 receives a higher compensating current than is necessary and the other receives a lower compensating current than is necessary. As a result of this, the two voltages, U1 and U2, drift apart from one another deviating from the target value of half the supply voltage V/2. In doing so, the first voltage U1 achieves an upper threshold value at the point in time t42, as a result of which a trigger pulse 15 is generated. The data processing unit 12 recognizes, by means of the deviating second voltage U2 at the second capacitor C2, that no storage is taking place. Such non-uniform self-discharging can result, for example, due to temperature influences or the like. The non-adapted compensating current distribution at the two capacitors, C1 and C2, is then corrected to the extent that a fourth charge quantity Q3 drained from the second capacitor is then supplied to the first capacitor C1 with opposite polarity.

(19) The exemplary embodiment only serves to explain the invention and is not limited to this. In particular, the previously explained circuitry arrangement can be modified as desired, without extending beyond the scope of the invention.

(20) Thus, it has been shown how the monitoring of status information of energy storage units, particularly battery cells, without a time basis, particularly based on energy units, can take place in a very energy-saving manner.