PULSE GENERATING CIRCUIT, AND ELECTROSURGICAL GENERATOR INCORPORATING THE SAME

Abstract

A bipolar pulse generating circuit for an electrosurgical generator generates a waveform for electroporation of biological tissue comprising a voltage source connectable to a load via a switching element, and a coaxial transmission line having an inner conductor separated from an outer conductor. The inner conductor first end is connected between the switching element and the voltage source and second end is in an open circuit condition, whereby the line is charged when the switching element is OFF and discharged when the element is ON. The bipolar pulse generating circuit has an output connectable to the load, wherein the first output supports a positive pulse when the line discharges, and a second output supports a negative pulse when the line discharges. The impedance of the coaxial transmission line matches a sum of impedance of the switching element, the load at the first output, and the load at the second output.

Claims

1. A bipolar pulse generating circuit for an electrosurgical generator, the bipolar pulse generating circuit comprising: a voltage source connectable to a load via a switching element; a coaxial transmission line having an inner conductor separated from an outer conductor by a dielectric material, wherein the inner conductor has a first end connected between an input of the switching element and the voltage source and a second end in an open circuit condition, whereby the coaxial transmission line is charged by the voltage source when the switching element is in an OFF state and to be discharged when the switching element is in an ON state; a first output connectable to the load, wherein the first output is located between an output of the switching element and ground to support a positive pulse when the coaxial transmission line discharges; and a second output connectable to the load, wherein the second output is located between the outer conductor of the coaxial transmission line and ground to support a negative pulse when the coaxial transmission line discharges, wherein the impedance of the coaxial transmission line is configured to match a sum of (i) the impedance the switching element, (ii) the impedance of the load at the first output, and (iii) the impedance of the load at the second output, wherein a delay line is connected to either the first output or the second output, whereby supply of the positive pulse and negative pulse at the first output and second output occurs sequentially.

2. (canceled)

3. A bipolar pulse generating circuit according to claim 1, wherein the delay line has an adjustable length.

4. A bipolar pulse generating circuit according to claim 1, wherein the delay line is another length of coaxial transmission line.

5. A bipolar pulse generating circuit according to claim 1, wherein the switching element comprises: a plurality of series connected avalanche transistors; and a trigger pulse generator configured to generate a trigger pulse to activate the plurality of series connected avalanche transistors.

6. A bipolar pulse generating circuit according to claim 5, wherein the trigger pulse generator comprises a TTL device.

7. A bipolar pulse generating circuit according to claim 5, wherein the trigger pulse has a voltage less than the emitter-base breakdown voltage of each of the plurality of avalanche transistors.

8. A bipolar pulse generating circuit according to claim 5, wherein the trigger pulse generator is connected to the plurality of series connected avalanche transistors via a transformer.

9. A bipolar pulse generating circuit according to claim 5, wherein the trigger pulse is applied between the collector and emitter of a first transistor of the plurality of series connected avalanche transistors.

10. A bipolar pulse generating circuit according to claim 9, wherein the first transistor is furthest from the coaxial transmission line.

11. A bipolar pulse generating circuit according to claim 5, wherein a diode is connected in parallel with each of the plurality of series connected avalanche transistors to clamp the voltage across each transistor to less than its collector-base breakdown voltage.

12. A bipolar pulse generating circuit according to claim 5, wherein each transistor in the plurality of series connected avalanche transistors is identical.

13. A bipolar pulse generating circuit according to claim 1, wherein the coaxial transmission line has a length selected to provide a line delay equal to or less than 5 ns.

14. A bipolar pulse generating circuit according to claim 1, wherein the coaxial transmission line is charged by the voltage source through a resistor.

15. A bipolar pulse generating circuit according to claim 1, wherein the load is an electrosurgical instrument.

16. An electrosurgical generator having a bipolar pulse generating circuit according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the invention are discussed below with reference to the accompanying drawings, in which:

[0023] FIG. 1 is a schematic diameter that illustrates the principle of a discharge line generator with an ideal switch;

[0024] FIG. 2A is a graph showing a voltage waveform at (i) the transmission line, and (ii) the load in FIG. 1;

[0025] FIG. 3A is a schematic diagram representing the open circuit transmission line of FIG. 1 in a DC model;

[0026] FIG. 3B is a schematic diagram representing the open circuit transmission line of FIG. 1 in a transmission line model;

[0027] FIG. 4 is a schematic diagram of showing the open circuit transmission line of FIG. 1 with an avalanche transistor to generate a positive ultrashort electric field pulse;

[0028] FIG. 5 is a diagram of a simulated LTSpice circuit of a monopolar ultrashort electric field pulse generator;

[0029] FIG. 6 is a graph showing pulses of various durations generated from the LTSpice circuit of FIG. 5;

[0030] FIG. 7 is a monopolar positive pulse observed with a matched 35Ω load, from circuit in FIG. 5;

[0031] FIG. 8 is a schematic diagram of showing the open circuit transmission line of FIG. 1 with an avalanche transistor to generate a negative ultrashort electric field pulse;

[0032] FIG. 9 is a diagram of a simulated LTSpice circuit of a monopolar ultrashort electric field pulse generator configured to generate a negative pulse;

[0033] FIG. 10 is a monopolar negative pulse observed with a matched 35Ω load, from circuit in FIG. 9;

[0034] FIG. 11A is a diagram of a simulated LTSpice circuit of a bipolar ultrashort electric field pulse generator without delay lines;

[0035] FIG. 11B is a diagram of a simulated LTSpice circuit of a bipolar ultrashort electric field pulse generator with delay lines before the load;

[0036] FIG. 12A is a graph depicting voltage observed at various points in the circuit of FIG. 11A; and

[0037] FIG. 12B is a graph depicting voltage observed at various points in the circuit of FIG. 11A.

DETAILED DESCRIPTION, FURTHER OPTIONS AND PREFERENCES

[0038] Generation of ultra-short pulses is possible by using an open circuit coaxial transmission line as a high-Q storage element consisting of distributed series of inductors and shunt capacitors with minimal resistance and shunt conductance. Discharging an open ended delay line via a fast switching element provides a means of producing a ‘flat-top’ rectangular pulse with steep fall times of less than 2 ns in a simple and affordable manner. The co-axial transmission line with a characteristic impedance, Z.sub.c, a length of l, and a dielectric constant ε.sub.y, is charged to a voltage level, V.sub.cc, through a high impedance resistor, R.sub.c. The line will have and associated delay time T given by the following equation:

[00001]$T=\frac{l\sqrt{{\epsilon }_r}}{c}$

[0039] where c is the speed of light (2.99×10.sup.8 m/s).

[0040] It follows from this that the pulse duration associated with the transmission line is:

[00002]$2T=2\frac{l\sqrt{{\epsilon }_r}}{c}$

[0041] An ultrashort electric field pulse can be generated on a load, R.sub.L, by discharging the transmission line through R.sub.L by closing a switching element. The switching element determines the rise time of the ultrashort electric field pulse whilst the transmission line determines the pulse duration (or width) and the fall time.

[0042] As explained above, the duration of the pulse at the load will be twice the associated delay time of the transmission line.

[0043] FIG. 1 illustrates the principle of an open circuit transmission line technique with an ideal switch as the switching element.

[0044] FIG. 2 shows the voltage waveforms obtained from the system of FIG. 1 at (i) the transmission line Z.sub.c and (ii) load R.sub.L.

[0045] The relationship between the characteristic impedance of the transmission line Z.sub.c and the load R.sub.L is integral to the performance of an open circuit coaxial transmission line technique in two ways, which can be understood by modelling the configuration using direct circuit (DC) theory and transmission line theory.

[0046] In DC theory, the relationship between Z.sub.0 and R.sub.L imitates a potential divider, as shown in FIG. 3A. Their relationship determines the pulse amplitude at the load V.sub.L:

[00003]$V_L=\left(\frac{R_L}{R_L+Z_0}\right)V_{\mathrm{cc}}$

[0047] If the impedance Z.sub.u is the same as R.sub.L, the maximum amplitude of the pulse at the load, V.sub.Lmax, will be half the voltage the to which the transmission line is charged:

[00004]$\mathrm{if}{R}_L=Z_0,V_{\mathrm{Lmax}}=\frac{V_{\mathrm{cc}}}{2}$

[0048] Using a transmission line model, the system can be represented as shown in FIG. 3B. In this model, the relationship between Z.sub.0 and R.sub.L determines the reflection coefficient, and therefore the pulse shape at the load. If R.sub.L is the same as Z.sub.0, the reflection coefficient will be zero and no secondary pulse or reflection of the primary pulse will be seen at the load:

[00005]$\Gamma =\left(\frac{R_L-Z_0}{R_L+Z_0}\right)\therefore \mathrm{if}{R}_L=Z_0,\Gamma =0$

[0049] Thus, the relationship of Z.sub.0 and R.sub.L determine two key aspects of the pulse at a load: (i) the pulse amplitude, and (ii) pulse shape (caused by any reflection). It follows from the analysis above, that the best pulse shape and parameters, the characteristic impedance of the transmission line Z.sub.0 and the load R.sub.L should match.

[0050] Other features of the pulse are controlled by other parameters of the circuit. For example, the pulse risetime is determined by the behavioural of the switching element, whilst the pulse width is determined by the length of the transmission line, as discussed above.

[0051] This switching element in embodiments of the invention is preferably provided by a stacked array of avalanche transistors. An avalanche transistor is known to provide reliable and repeatable high-speed switching of high voltages with rise times as low as 300 μs, which can be achieved in practice if microwave component layout techniques are considered when the circuit are implemented. Avalanche transistors utilize the negative-resistance characteristics region of bipolar junction transistors, which result from operation in the common-emitter breakdown region. The avalanche region lies between collector emitter (V.sub.CEO) and collector base (V.sub.CBO) voltage when the base current I.sub.B=0 A and emitter current I.sub.E=0 A.

[0052] FIG. 4 is a schematic diagram of a pulse generating circuit 100 that utilises an open circuit transmission line technique in combination with an avalanche transistor as a fast switching element. The circuit function is based on the discharge of the open-circuit transmission line across an avalanche transistor into a load R.sub.L.

[0053] A single avalanche transistor circuit can be configured to have a bi-stable operation, where the maximum pulse amplitude at the output is limited to half the value of the transistor's collector-emitter breakdown voltage, BV.sub.CES, if Z.sub.0=R.sub.L. A supply voltage V.sub.0 above the transistor's BV.sub.CES would permanently breakdown and damage the avalanche transistors as a switching element.

[0054] Initially, energy is stored in a co-axial transmission line via a small current flow in loop 1. A positive trigger on the base of the transistor will suddenly switch the transistor ‘on’. The energy stored in the transmission line will simultaneously be released as a high current along loop 2, producing a pulse on R.sub.L. The width of the trigger on the base is longer than 2T, i.e. the required pulse width at the load.

[0055] FIG. 5 shows a pulse generation circuit 200 that is an embodiment of the invention. The pulse generation circuit 200 is similar to the circuit shown in FIG. 4, except that in place of the single avalanche transistor, there is a plurality (five in this example) of series-connected avalanche transistors. The plurality of series-connected avalanche transistors effectively operate in combination as a single avalanche transistor. This means that the discharge of the open-circuit transmission line is across the stacked transistors to the load, thereby resulting in a cascade effect that causes a proportionally higher pulse amplitude at the load. In this example, each of the avalanche transistors is identical so that the supply voltage V.sub.cc is equally distributed across each of the avalanche transistor in the series chain.

[0056] In this arrangement, the maximum pulse amplitude that can be generated is dependent on the number of stacked avalanche transistor n. The number of avalanche transistors required to generate a specific pulse amplitude V.sub.L can be expressed as

[00006]$V_L={\mathrm{nBV}}_{\mathrm{CBO}}\left(\frac{R_L}{R_L+Z_0}\right)$

[0057] where BV.sub.CB0 is the collector-base breakdown voltage of each avalanche transistor. If R.sub.L=Z.sub.0, a maximum pulse amplitude V.sub.Lmax can thus be expressed as

[00007]$V_{\mathrm{Lmax}}=\frac{{\mathrm{nBV}}_{\mathrm{CBO}}}{2}$

[0058] In the pulse generating circuit 200 five FMMT417 avalanche transistor are stacked. Each transistor has an collector-emitter breakdown voltage BV.sub.CEO of 100 V and a collector-base breakdown voltage BV.sub.CEO of 320 V. The circuit shown in FIG. 5 was simulated using LTSpice models. The Spice model of the FMMT417 was directly taken from the manufacture's website. The source resistance R.sub.c is 1 MA, characteristic impedance of the transmission line Z.sub.0 is 50Ω, source voltage V.sub.cc is 1.5 kV.

[0059] The circuit may include a diode (not shown) connected in parallel with each transistor to clamp the voltage to ensure that the voltage across each transistor does not exceed its collector-base breakdown voltage. Doing so can increase the lifespan of the transistors and ensure that triggering occurs by the trigger signal.

[0060] The trigger signal may be provided by any suitable source. Preferably the trigger signal is generated by a TTL source or a microcontroller. In this example, the trigger signal comprises a pulse having a duration of 600 ns and a 5 V amplitude and pulse period (period of repetition) of 20 ms. It is advantageous to have a 5 V trigger signal because it is less than the emitter-base breakdown voltage of the transistors.

[0061] The pulse width of trigger signal is arranged to be longer than the pulse desired to be generated from the transmission line. The duration of 600 ns was chosen in this case to provide a safe margin to allow the whole transmission line to discharge.

[0062] The trigger signal repetition rate (pulse period) is limited by the time it takes for the open-circuit charged transmission line to charge up again to full capacity.

[0063] A transformer is disposed between the trigger signal generator and the base and emitter of the first transistor in the stack (i.e. the transistor furthest from the transmission line). This configuration means that the trigger pulse is floating, and therefore should be the same between the base and emitter of the first transistor no matter the voltage through the transistor and onto the load. As a result, the amplitude of the pulse at the load ought to increase linearly with the number of transistors in the stack. The transformer may be a 1-EMR-046 Gate Drive Transformer having a 1:1 winding ratio and high voltage isolation.

[0064] In use, the five stacked avalanche transistors are initially in their off-state, with each transistor having 300 V across them (i.e. V.sub.cc/n). When a positive trigger signal is applied to the base of the first transistor Q1, Q1 is turned ‘on’ and places its collector voltage near ground potential. This results in the second transistor Q2 having twice the collector-emitter voltage, thus creating the desired condition in terms of overvolting and therefore causes a non-destructive avalanching of Q2 and places its collector near ground potential. This creates a sequential ‘knock-on’ effect on the next transistor in the chain resulting in the overvolting of the first avalanche transistors, Q1, to the final avalanche transistors, Q5 near the charged open circuit transmission line. When Q5 is turned ‘on’, a fast rise time is produced at the load (<2 ns), therefore allowing the charged open circuit transmission line to discharge through the load producing a pulse with a width of 2T and a maximum amplitude of V.sub.cc/2, if R.sub.L=Z.sub.0.

[0065] The pulse generating circuit 200 may thus be used to generate monopolar ultrashort electric field pulses.

[0066] FIG. 6 is a graph showing voltage pulses obtained for a range of transmission line lengths. In FIG. 6, the transmission line lengths are characterised by the line delay T. The graph demonstrate that the transmission line length determines the pulse width of 2T, i.e. transmission lines having line delays of 5 ns, 25 ns, 50 ns and 100 ns produce pulse widths of 10 ns, 50 ns, 100 ns and 200 ns respectively. Additionally, the rise times of all four pulses are the same and less than 2 ns, which emphasises that the switching element, i.e. the five avalanche transistors, determines this factor.

[0067] The graph in FIG. 6 suggests that a 50Ω load does not match the transmission line characteristic impedance because secondary pulse of lower amplitude to the primary pulse is seen on each signal. This suggested an unmatched load due to reflection, i.e. Γ≠0. The inventors have realised that it is necessary to compensate for the impedance of the transistors in order to optimise the pulse generation circuit. In the example shown in FIG. 5, each individual transistor has an impedance of ˜3Ω. Therefore, a total of ˜15Ω is across the transistor stack. The reflection coefficient can thus be expressed as

[00008]$\Gamma =\left(\frac{R_{\Sigma }-Z_0}{R_{\Sigma }+Z_0}\right)=\left(\frac{\left(R_L+{\mathrm{nR}}_A\right)-Z_0}{\left(R_L+{\mathrm{nR}}_A\right)+Z_0}\right)$

[0068] wherein the R.sub.z is the total impedance of the circuit, and R.sub.A is the impedance of a signal avalanche transistor.

[0069] This explains the reflection observed in the pulses shown in FIG. 6, as Γ=0.13, and the amplitude of the reflection pulse is ˜13% of the primary pulse (R.sub.L=50Ω, nR.sub.A=(3Ω×5)=15Ω and Z.sub.u=50Ω). The additional impedance of nR.sub.A also affects the DC component of the design, which can be rewritten as:

[00009]$V_L=\left(\frac{R_L}{Z_0+R_A+R_L}\right)V_{\mathrm{cc}}$

[0070] Taking this into account, the impedance of the load R.sub.L was adjusted to 35Ω. This resulted in a single monopolar pulse at the load with zero reflection and no secondary pulse, as shown in FIG. 7.

[0071] The circuit shown above in FIGS. 4 and 5 is configured to generate positive monopolar pulses. However, the circuit can also be adapted to generate a negative monopolar pulse by changing the position in which the load is connected. FIG. 8 is a schematic diagram of a pulse generating circuit 150 that utilises an open circuit transmission line technique in combination with an avalanche transistor as a fast switching element similar to the circuit 100 in FIG. 4. The circuit 150 of FIG. 8 differs from the circuit of FIG. 4 in that the load R.sub.L is connected so that current flows in the opposite direction from FIG. 4 when the coaxial transmission line discharges. FIG. 9 shows a pulse generation circuit 250 that is an embodiment of the invention. The pulse generation circuit 250 is similar to the circuit shown in FIG. 5, except that the load R.sub.L is connected so that current flows in the opposite direction from FIG. 5 when the coaxial transmission line discharges. FIG. 10 shows a graph of a negative monopolar pulse observed with a matched 35Ω load, obtained using the circuit 250 shown in FIG. 9.

[0072] In a development of the concepts discussed above, the pulse generating circuit can be configured as a bipolar pulse generating circuit. The operation of such a circuit can be identical to the monopolar designs in FIGS. 4 and 9.

[0073] FIG. 11A is a schematic diagram of a pulse generation circuit 300 that is an embodiment of a bipolar pulse generating circuit 300. It is similar to the circuits shown in FIGS. 4 and 9, except that the pulse is generated on two separate loads, which are marked at R.sub.L+ and R.sub.L− in FIG. 11A.

[0074] These load location correspond to the locations for the positive and negative pulses discussed above.

[0075] The bipolar pulse generating circuit 300 produces a bipolar pulse, as the voltage difference across R.sub.L; produces a positive pulse, where the voltage difference across R.sub.L− produces a negative pulse. When the circuit 300 is used, these pulses observed at on R.sub.L+ and R.sub.L− simultaneously and are symmetrical, i.e. with the same pulse width, rise time, amplitude a repletion rate, but of different polarity.

[0076] As there are two loads in this circuit, the optimisation equations to reduce reflection must be revised. For a bipolar design the total load impedance, R.sub.ZL=R.sub.L+R.sub.L−, is the impedance between the transmission line's outer conductor and the emitter of avalanche transistor Q1 and is the sum impedance of R.sub.L+ and R.sub.L−. The reflection coefficient can therefore be expressed using transmission line theory as:

[00010]$\Gamma =\left(\frac{\left(R_{\Sigma L}+{\mathrm{nR}}_A\right)-Z_0}{\left(R_{\Sigma L}+{\mathrm{nR}}_A\right)+Z_0}\right)=\left(\frac{\left(R_{L-}+R_{L+}+{\mathrm{nR}}_A\right)-Z_0}{\left(R_{L-}+R_{L+}+{\mathrm{nR}}_A\right)+Z_0}\right)\therefore \mathrm{if}{R}_{\Sigma L}=R_{L-}+R_{L+}=Z_0-{\mathrm{nR}}_A,\Gamma =0$

[0077] Similarly, the peak-to-peak voltage V.sub.ZL over the loads can be expressed using DC theory as:

[00011]$V_{\Sigma L}=V_{L+}+V_{L-}=\left(\frac{R_{\Sigma L}}{Z_0+R_A+R_{\Sigma L}}\right)V_{\mathrm{cc}}{V}_{L-}=\left(\frac{R_{L-}}{Z_0+R_A+R_{\Sigma L}}\right)V_{\mathrm{cc}}{V}_{L+}=\left(\frac{R_{L+}}{Z_0+R_A+R_{\Sigma L}}\right)V_{\mathrm{cc}}$

[0078] wherein V.sub.L+ and V.sub.L− are the amplitudes of the positive and negative pulses respectively.

[0079] From the above, R.sub.L+ and R.sub.L− values of 17.5Ω would produce a bipolar pulse of a single pulse with zero reflection (Γ=0), and a simultaneous symmetrical pulse width of 2T and rise times<2 ns. Put another way, the bipolar pulse generating circuit 300 operates to create a single positive pulse of amplitude V.sub.EL between the transmission line's outer conductor and the emitter of avalanche transistor Q1, across R.sub.EL with a pulse width of 2T and zero reflection.

[0080] FIG. 12A is a graph that shows a pulse 310 observed at R.sub.L+, a pulse 312 observed at R.sub.L−, and a pulse 314 observed at R.sub.EL. These observations verify the theory presented above. In FIG. 12A, a 5 ns transmission line produces a 10 ns pulse at all three loads with identical rise times (<2 ns). As R.sub.L+=R−=17.5Ω, there is no reflection, i.e.

[00012]$\Gamma -\left(\frac{\left(R_{L-}+R_{L+}+{\mathrm{nR}}_A\right)-Z_0}{\left(R_{L-}+R_{L+}+{\mathrm{nR}}_A\right)+Z_0}\right)-\left(\frac{\left(17.5+17.5+15\right)-50)}{\left(17.5+17.5+15\right)-50)}\right)-0$

[0081] The magnitude of V.sub.L+, and V.sub.L− is 262.5 V, so the peak-to-peak voltage V.sub.EL is 520 V, which is the same as the equivalent monopolar design.

[0082] FIG. 11B is a schematic diagram of a bipolar pulse generation circuit 350 that is another embodiment of the invention. The circuit in FIG. 11B differs from FIG. 11A by providing a delay line before each of the loads (R.sub.L+ and R.sub.L−).

[0083] Placing a delay line before one or both loads allows manipulation of a delay between the two pulses. A delayed pulse will follow a non-delayed paired pulse by the delay time minus pulse width. In FIG. 11B, a 20 ns delay line is placed before R.sub.L−.

[0084] FIG. 12B is a graph similar to FIG. 12A that shows a pulse 310 observed at R.sub.L+, a pulse 312 observed at R.sub.L−, and a pulse 314 observed at R.sub.EL. FIG. 12B confirms the effect of the introducing the delay line, as all the three pulses in FIG. 12B and there parameters are identical to the FIG. 12A. The only difference is that the negative pulse across R.sub.L− follows the positive pulse by 10 ns (i.e. 20 ns−10 ns).

[0085] The bipolar pulse generation circuit configuration discussed herein is thus capable of producing: [0086] a symmetrical bipolar pulse, with positive and negative parts generated simultaneously or sequentially (i.e. with differing delays) [0087] zero reflection but adjustable V.sub.L+ and V.sub.L− amplitudes, because the amplitudes are controlled by the ratio of R.sub.L+ and R.sub.L− but the reflection will remain zero if R.sub.EL=R.sub.L−+R.sub.L+=Z.sub.0−nR.sub.A, condition is met.

[0088] In a further development, one or both of the delay lines may have an adjustable length that allows the introduced delay to be controlled. This may permit the separation of the positive and negative pulses to be adjusted on the fly, e.g. so that the instrument is capable of generating a variety of electroporation waveforms.

REFERENCES

[0089] [1] W. Meiling and F. Stary, Nanosecond pulse techniques. New York: Gordon and Breach, 1970, p. 304. [0090] [2] Q. Yang, X. Zhou, Q.-g. Wang and M. Zhao, “Comparative analysis on the fast rising edge pulse source with two kinds of avalanche transistor,” in Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, Chengdu, 2013. [0091] [3] G. Yong-sheng et al., “High-speed, high-voltage pulse generation using avalanche transistor,” Review of Scientific Instruments, vol. 87, no. 5, p. 054708, 2016.