HEMT TRANSISTOR

Abstract

A high-mobility field-effect transistor, includes a stack along a Z axis, deposited on a substrate and comprising a buffer layer, a barrier layer, a heterojunction between the buffer layer and the barrier layer, and a two-dimensional electron gas localized in an XY plane perpendicular to the axis Z and in the vicinity of the heterojunction, a source, a drain, and a gate deposited on an upper face of the barrier layer, between the source and the drain, a first dielectric layer having a relative permittivity ε.sub.r and a thickness e which are such that: 0.5 nm≤e/ε.sub.r≤2 nm, a metal pad arranged between the gate and the drain and deposited on the first dielectric layer, the metal pad being electrically connected to the gate.

Claims

1. A high-mobility field-effect transistor operating at a frequency of between 10 and 80 GHz, comprising: a stack along a Z axis, arranged on a substrate and comprising: a buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second bandgap, the second bandgap being greater than the first bandgap, a heterojunction between said buffer layer and said barrier layer, and a two-dimensional electron gas localized in an XY plane and in the vicinity of the heterojunction, a source (S), a drain (D), and a gate (G) arranged on an upper face of the barrier layer, between the source and the drain, a distance between the source and the drain being less than or equal to 4 μm, a gate length (Lg) being less than or equal to 0.5 μm, a first dielectric layer (PL1) arranged at least on an upper surface of the barrier layer, between the gate (G) and the drain (D) and between the gate (G) and the source (S), having a relative permittivity ε.sub.r and a thickness e which are such that: 0.5 nm≤e/ε.sub.r≤2 nm, a metal pad (PM) arranged between the gate (G) and the drain (D) and deposited on the first dielectric layer (PL1), a length (Lp) of the metal pad being less than or equal to 2 times the length (Lg) of the gate, the metal pad being electrically coupled to the gate by a first metal connection, a distance between the pad and the drain being greater than or equal to 300 nm and a distance between the pad and the gate being greater than or equal to 200 nm, a sum of a surface of a cross section of the gate, a cross section of the pad and a cross section of the first metal connection connecting the gate and the pad (PM) is greater than or equal to two times a surface of a cross section (S.sub.G) of the gate (G), said cross sections being along the XZ plane.

2. The transistor as claimed in claim 1, wherein the relative permittivity ε.sub.r of the first dielectric layer is between 3 and 10.

3. The transistor as claimed in claim 1, wherein the first metal connection is in electrical contact with the metal pad.

4. The transistor as claimed in claim 1, furthermore comprising a second dielectric layer (PL2) deposited at least on the metal pad (PM), the first metal connection being in contact with said second dielectric layer deposited on the metal pad so as to establish a capacitive coupling between the metal pad and the gate.

5. The transistor as claimed in claim 4, wherein the first metal connection is in electrical contact with the gate.

6. The transistor as claimed in claim 4, wherein the second dielectric layer (PL2) is also deposited on the gate, and wherein the first metal connection is in contact with a part of the second dielectric layer deposited on the gate.

7. The transistor as claimed in claim 4, wherein the gate is connected to a gate bus (G-Bus) and the metal pad is connected to said gate bus.

8. The transistor as claimed in claim 7, furthermore comprising a second metal connection connecting the gate and the metal pad on the opposite side from the gate bus (G-bus).

9-13. (canceled)

14. An assembly comprising a plurality of transistors as claimed in claim 1, wherein a transistor alternately shares a source and a drain with an adjacent transistor, and wherein the sources are connected to one another by a source bridge (PS).

Description

[0050] The invention will be understood more clearly, and other characteristics, aims and advantages thereof will emerge during the following detailed description with reference to the appended drawings, which are given by way of nonlimiting examples and in which:

[0051] FIG. 1, already mentioned, schematically represents a cross section of the structure of a conventional elementary HEMT transistor.

[0052] FIG. 2, already mentioned, represents a conventional HEMT transistor with a gate having a T-shape.

[0053] FIG. 3 illustrates a high-mobility field-effect transistor according to the invention.

[0054] FIG. 4 illustrates the effect of the metal pad on the electric field in the channel for a transistor operating at the bias point (in this example V.sub.ds equal to 15 V and Ids equal to 0.2 A/mm). The upper part illustrates the gate of the transistor and the pad deposited on the passivation layer. The lower part illustrates the value Fx(x)_Canal of the component along x of the electric field in the channel as a function of x and as a function of various thicknesses of the passivation layer.

[0055] FIG. 5 illustrates the effect of the metal pad on the electric field in the channel for a transistor operating at a voltage V.sub.dsMAX equal to 40 V and V.sub.gsMAX equal to −9 V. The upper part illustrates the gate of the transistor and the pad deposited on the passivation layer. The lower part illustrates the value Fx(x)_Canal of the component along x of the electric field in the channel as a function of x and as a function of various thicknesses of the passivation layer.

[0056] FIG. 6 illustrates the evolution of the component of the electric field Fz(z)_Bar along z in the barrier as a function of z.

[0057] FIG. 7 illustrates a preferred first option of gate-pad connection “through the top”, in which the first metal connection electrically connects the gate and the metal pad by establishing a direct connection.

[0058] FIG. 8 illustrates a first alternative of a second option in which said connection between the gate and the pad is capacitive, in which the connection is made through the passivation layers.

[0059] FIG. 9 illustrates a second alternative of the second option in which the connection between the gate and the pad is capacitive, in which the connection is made through the layer PL2 on the metal pad side, the contact therewith on the gate side being direct.

[0060] FIG. 10 illustrates a “planar” gate-pad connection mode, in which the metal pad is connected to the gate bus.

[0061] FIG. 11 illustrates a variant of the gate-pad connection mode of FIG. 10, in which a second metal connection connects the gate and the metal pad on the opposite side from the gate bus.

DETAILED DESCRIPTION OF THE INVENTION

[0062] The high-mobility field-effect transistor 100 according to the invention is illustrated in FIG. 3. It comprises a stack 10 along a Z axis, deposited on a substrate 11, which comprises: [0063] a buffer layer 12 comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first bandgap (typically GaN), [0064] a barrier layer 13 comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second bandgap, the second bandgap being greater than the first bandgap (typically InAlN, or AlGaN or InAlGaN), [0065] a heterojunction 15 between the buffer layer 12 and the barrier layer 13, and [0066] a two-dimensional electron gas 9 localized in an XY plane perpendicular to the axis Z and in the vicinity of the heterojunction 15.

[0067] Preferably, a thin layer 15 of AlN (typically having a thickness of from 1 to 2 nm) is added between the buffer layer 12 and the barrier 13 in order to increase the electron density and the electron mobility in the channel.

[0068] The transistor also comprises, in the conventional way, a source S, a drain D, and a gate G deposited on an upper face 14 of the barrier layer 13, between the source S and the drain D. The alignment S/G/D defines the axis X of interest of the component. The origin O of the coordinate system (x, z) is taken at the foot of the source S, at the interface between the barrier and the buffer layer. The gate has for example a rectangular or T- or Γ-shape. The transistor according to the invention is configured to operate at high frequency, typically between 10 and 80 GHz. For this purpose, it is necessary for the distance d.sub.SD between the source and the drain (along the X axis) to be less than or equal to 4 μm, with a gate length Lg (along the X axis) less than or equal to 0.5 μm. Specifically, the operating frequency dictates the various distances d.sub.SG, d.sub.GD and Lg.

[0069] The following relationship applies: d.sub.SD=d.sub.SG+d.sub.GD+Lg

[0070] For an RF power transistor, it is necessary to have:

an input resistance (between the source and the gate) which is as low as possible. This resistance is proportional to the gate-source distance d.sub.SG.
a gate with a length such that the transit time of the electrons under this gate is compatible with the intended operating frequency. Typically, with Lg=0.5 μm the transistor operates up to 10 GHz, with Lg=0.25 μm it operates up to 20 GHz, with Lg=0.15 μm it operates up to 35 GHz, with Lg=0.1 μm up to 50 GHz, and with Lg=0.065 μm up to 80 GHz.
an output resistance which is as low as possible, but with the additional constraint (in comparison with the input) that the distance d.sub.GD between the gate and the drain is sufficiently large to withstand the voltage applied between the drain and the gate (if it is too short, this may lead to destruction of the component by avalanche breakdown). This distance d.sub.GD is therefore a compromise between these two requirements.

[0071] It should be noted that for nitride-based transistors, a high electron density in the channel is necessary for these RF applications.

[0072] In the conventional way, the transistor comprises a first dielectric layer PL1 (passivation layer) deposited at least on the upper surface 14 of the barrier layer 13, between the gate G and the drain D and between the gate G and the source S. However, this passivation layer has a particular thickness in the transistor according to the invention.

[0073] The transistor according to the invention also comprises a metal pad PM arranged between the gate G and the drain D. The metal pad PM is arranged between the gate G and the drain D and is deposited on the first dielectric layer PL1. Furthermore, the metal pad is electrically connected to the gate. As described below, this pad has an effect on the electric field localized at the foot of the gate on the drain side.

[0074] The source, the drain and the gate are commonly referred to as electrodes, and according to this nomenclature the pad PM may be likened to a fourth electrode. The pad PM is made of metal, typically Au.

[0075] In relation to the presence of the pad, the passivation layer PL1 according to the invention has a relative permittivity ε.sub.r and a thickness e, which are such that:

0.5 nm≤e/ε.sub.r≤2 nm  (1)

[0076] The upper bound of the parameter e/ε.sub.r is determined by simulation (see below). The ratio e/ε.sub.r cannot have a value of less than 0.5 nm either, because the electric field in this passivation under the pad PM would exceed the breakdown field of the material, which would degrade this passivation PL1.

[0077] For optimum operation of the pad, it is also expedient (see below) for it not to have a size that is too great in relation to the gate, that is to say for the length Lp of the metal pad along the X axis to be less than or equal to 2 times the length Lg of the gate: Lp≤2.Lg.

[0078] The value of the ratio R=e/ε.sub.r of the layer PL1, according to the invention, is much less than is commonly the practice in transistors of the prior art, in which this passivation layer typically has a thickness of 50 nm-2 μm, with permittivities typically between 3 and 10, that is to say an R of between 5 nm and 667 nm.

[0079] Preferably, for the invention, the relative permittivity ε.sub.r is between 3 and 10. This is because with a higher permittivity, a breakdown field of the material would be achieved which is too low in relation to the field applied during operation of the component. Furthermore, these permittivity values correspond to the technologically most well-established materials. These preferred permittivity values then lead to a thickness e of the passivation layer of between 1.5 nm and 20 nm.

[0080] In FIG. 3, the zone 30 is the critical zone of the component. The electric field is intense there, and since there is a high dislocation density in this barrier 13 because of the reverse piezoelectricity phenomenon, this is a zone of weakness of the component. Creation of conduction paths then takes place between the gate and the channel by means of these defects, which is ultimately manifested by an increase in the gate leakage currents and a degradation of the performance of the transistor. Fx_canal denotes the component of the field along x in the channel. The channel is located in the buffer layer at a few nm from the interface with the barrier or the layer 15, when it is present.

[0081] As will be shown in FIGS. 4 and 5, the zone 31 illustrates the location of a new electric field at the foot of the pad PM. The addition of a 4th electrode (PM) very close to the barrier and separated therefrom by a passivation PL1 makes it possible to reduce the intensity of the electric field at the gate foot, in the channel and the barrier, by offsetting it to the foot of this 4th electrode, which, being insulated from the barrier and its passivation defects, makes it possible to eliminate this cause of weakness.

[0082] The effect of the pad PM as claimed on the electric field in the vicinity of the foot of the gate is illustrated in FIGS. 4 and 5. In these two figures, the upper part illustrates the gate of the transistor and the pad PM deposited on the layer PL. The lower part illustrates the value Fx(x)_Canal of the component along x of the electric field as a function of x (with an origin O selected at the source, as illustrated in FIG. 3) as a function of various thicknesses e of the layer PL1. These simulations were carried out by TCAD (Technology Computer-Aided Design), which is a branch of electronic CAD aiming to model the manufacture and operation of semiconductor devices.

[0083] In this example, the gate foot-source distance is 0.7 μm and the gate foot-drain distance is 1.4 μm, and the length Lg of the gate is 110 nm. The pad PM has a length Lp of 75 nm and is located at 800 nm from the gate foot lying on the side of the drain (see the scale x in FIGS. 4 and 5).

[0084] FIG. 4 corresponds to the behavior of the field when the component is at the bias point (quiescent point) with the parameters:

V.sub.ds=15 V; I.sub.ds=0.2 A/mm (for operation in class AB) and the carrier density n.sub.s in the channel is of the order of 1.6.10.sup.13/cm.sup.2.

[0085] The charge density n.sub.s (set by the materials used) dictates the maximum operating voltage V.sub.dsMAX which can be applied to the transistor, this operating voltage V.sub.ds having to be less than V.sub.dsMAX.

[0086] FIG. 5 corresponds to the behavior of the field when the component is at the operating point with a maximum V.sub.ds of V.sub.dsMAX=40 V and V.sub.gsMAX=−9 V.

[0087] In this example, a layer PL1 of Si.sub.3N.sub.4 is selected (usual case), with a relative permittivity ε.sub.r equal to 7.5 and a variable thickness e.

[0088] In these two figures, the two curves C1 and C1′ illustrate the field Fx(x)_Canal without a pad (the thickness e of the layer PL1 then has no effect). The subsequent curves incorporate the presence of a pad PM. The curves C5 and C5′ correspond to a thickness e of PL1 equal to 5 nm, the curves C15 and C15′ to a thickness of PL1 equal to 15 nm, and the curves C25 and C25′ to a thickness of PL1 equal to 25 nm. For the simulation, ε.sub.r=7.5 was taken, a value of the nitride which is a material used very widely for passivation. Thus, in the simulations

e=5 nm<->R=e/ε.sub.r=0.66

e=15 nm<->R=e/ε.sub.r=2

e=25 nm<->R=e/ε.sub.r=3.33

[0089] It may be seen in these two figures, which illustrate two situations of the component (at the operating point of the transistor and at the maximum voltages applied to the drain and the gate), that the effect of the presence of the pad PM connected to the gate is to reduce the intensity of the peak P1 of the electric field Fx(x)_Canal at the foot of the gate located on the drain side. Together with this reduction, the growth of a second electric field peak P2 is observed at the foot of the pad PM, also located on the side of the drain. It is also observed that the lower the ratio R is, the more the intensity of the electric field at the foot of the gate is reduced and the more that at the foot of PM is increased.

[0090] It may be seen that for (25 nm and ε.sub.r=7.5) i.e. R=3.33, the field at the foot of the gate is not substantially reduced, the effect becoming clearer beyond (15 nm and ε.sub.r=7.5) i.e. R=2 (reduction of the field by at least 30%).

[0091] It is the capacitive effect induced by the presence of the metal pad PM associated with the dielectric layer PL1 which modifies the distribution of the field. The capacitive effect is created between the pad PM and the 2D electron gas 9 by means of the first passivation layer PL1. This pad PM allows an electrical potential to be brought between the gate and the drain, which makes it possible to reduce the density of electrons localized at the interface between the materials 13 and 12 which are in line with this pad. Its action is commensurately greater when this pad is close to the electron gas 9 and the ratio R is small.

[0092] The length Lg of the gate (that is to say its stem for a T- or Γ-gate) determines the maximum operating frequency of the transistor. In order not to degrade the performance of the transistor (particularly the gain) excessively, the pad PM must not have too great a length Lp because this would lead to a degradation of the power gain of the transistor. With the aid of simulations, the Inventors have determined that it is expedient for Lp to be less than or equal to 2 times the gate length Lg (along the alignment axis X). The criterion is that beyond this length of the pad equal to 2 times Lg, more than 1 dB is lost from the gain.

[0093] It should be noted that the reduction of the electric field peak P1 is more marked for V.sub.dsMAX=40 V and V.sub.gsMAX=−9 V, the pairing (15 nm and ε.sub.r=7.5) i.e. R=2 making it possible to reduce the field from 4 MV/cm to 2.5 MV/cm.

[0094] FIG. 6 illustrates an additional beneficial effect of the pairing (pad PM, PL1 with low R). FIG. 6 illustrates the evolution of the component Fz(z)_Bar of the electric field along z in the barrier 13 as a function of z (the point 0 corresponding to the start of the additional layer 15). The curves on the left correspond to the transistor at the operating point (in the example selected, I.sub.ds=0.2 A/mm and V.sub.ds=15 V) and the curve on the right corresponds to the transistor at V.sub.dsMAx=40 V and V.sub.gsMAX=−9 V. The curves D5, D15 and D25 on the left correspond respectively to a passivation layer thickness of 5 (R=0.66), 15 (R=2) and 25 nm (R=3.33), likewise for the curves D5′, D15′ and D25′ on the right. An excessive value of the field Fz(z)_Bar gives rise to weaknesses of the component due to the deformation of the crystal lattice by means of the stresses induced by the reverse piezoelectric effect. These weaknesses are manifested by the creation of parasitic conduction paths between the gate and the 2DEG channel, leading to degradation of the microwave performance of the transistor.

[0095] A decrease in the field Fz(z)_Bar at the foot of the gate on the drain side in the depth of the barrier layer may be observed, which is increasingly marked when the thickness becomes thin.

[0096] Furthermore, the gain of the transistor which is obtained for the four values of R, 0.66, 2, 3.33 and 4, was simulated and the results are given in Table I below, which also summarizes the results for the electric field at the foot of the gate.

[0097] For the gain, the quiescent operating point and a frequency of 35 GHz were assumed.

TABLE-US-00001 TABLE I Relative difference in Relative difference in Difference in the gain relation to the reference* relation to the reference* ratio at Ids = 200 mA/mm in the electric field Fx(x) in the electric field Fz(z) R = e/εr Vds = 15 V & 35 GHz in the channel** in the barrier*** of the in relation to the Ids = 200 mA/mm Vgs = −9 V Ids = 200 mA/mm Vgs = −9 V layer PL1 reference* Vds = 15 V Vds = 40 V Vds = 15 V Vds = 40 V R = 0.66 −0.25 dB  i.e. −5% 0.44 0.52 0.62 0.64 R = 2 −0.9 dB i.e. −18% 0.73 0.68 0.81 0.73 R = 3.33 −1.5 dB i.e. −29% 0.88 0.77 0.92 0.81 R = 4 −1.9 dB i.e. −35% 0.94 0.8 0.97 0.86 *reference: no pad PM **taken at the foot of the gate on the drain side in the channel (critical zone of the component) ***taken at the foot of the gate on the drain side in the barrier (critical zone of the component).

[0098] In terms of the gain, the presence of the pad tends to reduce the gain, more markedly when the thickness e increases. A loss ranging up to 1 dB is considered to be acceptable, and beyond this the performance is considered to be degraded. For a ratio R of 2, the situation is below 1 dB (0.9), and for R=3.33 this threshold has been exceeded (1.5). These results confirm the selection of a passivation layer (e, ε.sub.r) such that e/ε.sub.r 2 in order to produce the transistor according to the invention.

[0099] For the field Fx(x)_Canal, a ratio R=2 makes it possible to have at least 30% reduction of the maximum field (without a pad). For the field Fz(z)_Bar, the ratio R=2 makes it possible to have at least 25% reduction of the maximum field.

[0100] For ratios 3-4 (and beyond), the effect of reducing the peak P1 is weak and the gain loss is greater.

[0101] This effect of spreading the electric field is not dependent to first order on the position of the pad in the gate-drain space. Preferably, the pad PM is not too near the gate or the drain. If the pad PM is too close to the drain contact, this is manifested by an increase in C.sub.gd and therefore a reduction in the gain, and if it is placed too close to the gate, this becomes difficult to implement. Furthermore, if the bridge connecting the gate and the pad PM is not long enough, this will be manifested by a gate resistance which is too high. Thus, preferably, the pad-drain distance is greater than or equal to 300 nm and the pad-gate distance is greater than or equal to 200 nm.

[0102] One solution that makes it possible to simplify manufacture is that the metal pad has a pattern identical to the pattern of the gate. It is therefore produced by duplicating the gate.

[0103] The metal pad PM is electrically connected to the gate G via a metal connection. Various examples of this connection mode are described below.

[0104] The first connection mode “through the top” is illustrated in FIGS. 7 to 9. The metal pad is electrically connected to the gate by a first metal connection.

[0105] According to a preferred first option, which is illustrated FIG. 7, the first metal connection 60 electrically connects the gate G and the metal pad PM by producing a direct connection (of the resistive type, with a resistance that is as low as possible). When the gate is covered by the layer PL1, it is expedient to open a passage onto the gate cap in order to establish the connection. With this configuration, it is not necessary to optimize the capacitance, and it makes it possible to reduce the electric fields most strongly (see the simulations above carried out in this case). It does, however, make production more complex because it requires an opening to be formed in the passivation present on the gate in order to obtain a direct contact.

[0106] According to a second option, which is illustrated in FIGS. 8 and 9, the transistor comprises a second dielectric layer PL2 deposited at least on the metal pad PM, the first metal connection 61 being in contact with said second dielectric layer PL2 deposited on the pad PM. The metal pad and the gate are then connected by a capacitive connection. This configuration makes production simpler because it does not require an opening to be formed in the passivation present on the gate. However, it is then necessary to optimize the capacitance, and it is less effective in reducing the electric fields.

[0107] Typically, during manufacture, the layer PL1 covers the gate and the layer PL2 covers the pad and the gate, as illustrated in FIGS. 8 and 9.

[0108] According to one alternative, which is illustrated in FIG. 8, the capacitive connection between G and PM is carried out through PL1 and PL2 on the side of the gate G and through PL2 on the side of the metal pad PM. The first metal connection 61 is in contact with the part of the second dielectric layer PL2 deposited on the gate.

[0109] According to another alternative, which is illustrated in FIG. 9, the capacitive connection between G and PM is carried out through PL2 on the side of the metal pad, the contact therewith on the gate side being direct, an opening having been formed onto the gate cap. The first metal connection 61 is then in electrical contact with the gate.

[0110] If the pad PM has too high an electrical resistance, the losses will increase and the gain of the transistor will decrease. It is desirable for the pad to have a relatively low resistance, typically comparable with the electrical resistance of the gate or less. The sum ΣS of the cross sections is defined as being equal to the sum of the cross section S.sub.G of the gate, the cross section SPM of the pad PM and the cross section of the connection 60 or 61. The cross sections of these various elements are defined in the plane OXZ, a plane which is perpendicular to the flow of the gate current. Preferably, ΣS should be greater than or equal to 2 times the cross section of the gate. If these various elements are composed of the same metal, this ensures that the resistance of the assembly (gate+bridge/connection 60 or 61+pad PM) is at least less or equal by a factor of 2 than that of the gate alone (reference case without a pad PM).

[0111] According to one embodiment, the gates are connected together by means of a gate bus G-bus and the drains are connected together by means of a drain bus D-bus located in a plane P1. The sources are connected together with a “source bridge” PS passing over a passivation layer and located in a plane P2 above P1.

[0112] According to a second connection mode, the metal pad PM is connected to the gate bus G-Bus by one of its ends, PM and G thus both being connected to the gate bus. FIG. 10 illustrates this connection mode for a group 100 of transistors in which a transistor alternately shares a source and a drain with the adjacent transistor. This connection is easy to produce technologically, and it may be resistive or capacitive.

[0113] According to a variant of this connection mode, which is illustrated in FIG. 11, a second metal connection 62 connects the gate and the metal pad on the opposite side from the gate bus G-bus, via the opposite end of the pad PM from the gate bus. This makes it possible to reduce the gate resistance by a factor of 2, which is advantageous for the gain of the transistor.

[0114] In the case of connection by means of the gate bus, the condition for the sum of the cross sections is expressed without the cross section of the bridge. This is equivalent to saying that the sum of the cross section SPM of the pad PM+ the cross section S.sub.G of the gate G is greater than or equal to two times the cross section S.sub.G of the gate G.