Low noise non-foster circuit

Abstract

A method of and an apparatus for reducing noise in a non-Foster circuit having at least a pair of cross coupled transistor devices, each transistor device of the pair of cross coupled transistor devices having a pair of current carrying electrodes. The method and apparatus involves coupling inductors with each pair of the current carrying electrodes of each of the cross-coupled transistor devices in the non-Foster circuit, the inductors also being coupled with voltage and/or current sources associated with or coupled to the non-Foster circuit. The nominal values of the inductors are selected to provide a load asymmetry, so that the load inductor in the input side of the non-Foster circuit has a larger inductance than the load inductor at the output side of non-Foster circuit.

Claims

1. A bias circuit for a non-Foster circuit, the non-Foster circuit being coupled in use with a DC power supply, the non-Foster circuit having a pair of transistors, one of the transistors of said pair being coupled to an input of said non-Foster circuit and the other one of the transistors of said pair being coupled to an output of said non-Foster circuit, the bias circuit including: (a) first inductors connected with (i) current carrying electrodes of the one of the transistors coupled to an input of said non-Foster circuit and (ii) said DC power supply; (b) second inductors connected with (i) current carrying electrodes of the other one of the transistors coupled to an output of said non-Foster circuit and (ii) said DC power supply; and wherein a sum of the inductances of the first inductors is greater than a sum of the inductances of the second inductors.

2. The bias circuit of claim 1 further including a pair of resistors each coupled to (i) a control electrode of one of said transistors and (ii) said DC power supply.

3. The bias circuit of claim 2 furthering including a pair of capacitors each coupled to (i) a control electrode of one of said transistors and (ii) a current carrying electrode of the other one of the transistors.

4. The bias circuit of claim 3 wherein one of the inductors of said first inductors is connected to a ground associated with said DC power supply and one of the inductors of said second inductors is also connected to the ground associated with said DC power supply.

5. The bias circuit of claim 4 wherein said one of the inductors of said first inductors has a nominal value expressed in Henrys and said one of the inductors of said second inductors also has a nominal value expressed in Henrys, the nominal values of the one of the inductors of said first inductors and the one of the inductors of said second inductors are the same.

6. The bias circuit of claim 2 wherein each of said resistors has a value of at least one megohm.

7. A bias circuit for a non-Foster circuit, the non-Foster circuit being coupled in use with a power supply, the non-Foster circuit having a pair of transistors, one of the transistors of said pair being coupled to an input of said non-Foster circuit and the other one of the transistors of said pair being coupled to an output of said non-Foster circuit, the bias circuit including said power supply and inductors including at least inductors L.sub.1 and L.sub.2 coupled in series with said power supply, inductors L.sub.1 and L.sub.2 being arranged as asymmetrical impedances so that their corresponding impedance values Z.sub.L1 and Z.sub.L2 are selected such that the ratios Z.sub.L1/Z.sub.ant and Z.sub.L2/Z.sub.lna are approximately equal to each other, where Z.sub.ant is an impedance looking into an antenna coupled, in use, to said input of the non-Foster circuit while Z.sub.lna is an impedance looking into an amplifier connected, in use, to said output of the non-Foster circuit.

8. The bias circuit of claim 7 wherein the inductors L.sub.1 and L.sub.2 are each coupled in series with said power supply and a first current carrying electrode of each of said transistors and further including at least additional inductors L.sub.3 and L.sub.4 which are each coupled in series with said power supply and a second current carrying electrode of each of said transistors.

9. The bias circuit of claim 8 wherein additional inductors L.sub.3 and L.sub.4 have nominally identical inductance values.

10. The bias circuit of claim 8 wherein a total (sum of) the inductance of the inductors L.sub.1 and L.sub.3 connected in series with current carrying electrodes of said one of said transistors of said pair and the power supply is greater than the total (sum of) inductance of the two inductors L.sub.2 and L.sub.4 connected in series with current carrying electrodes of said other of said transistors of said pair and the power supply.

11. The bias circuit of claim 7 wherein the ratio (Z.sub.L1/Z.sub.ant) (Z.sub.L2/Z.sub.lna) falls within a range of 0.90 to 1.10 and more preferably in the range of 0.95 to 1.05.

12. An apparatus for biasing a non-Foster circuit having at least a pair of cross coupled transistor devices, each transistor device having a pair of current carrying electrodes, the apparatus comprising an inductor directly coupled with each of the current carrying electrodes of each of the cross-coupled transistor devices in said non-Foster circuit, the inductors also being coupled with voltage and/or current sources associated with or coupled to said non-Foster circuit.

13. The apparatus of claim 12 wherein each transistor device has a control electrode which is capacitively coupled with one of the current carrying electrodes of another one of said transistor devices.

14. The apparatus of claim 12 wherein the non-Foster circuit has an input coupled with an electrically small antenna and an output coupled with an amplifier having a low input impedance, the low input impedance of the amplifier being substantially lower than an impedance of the electrically small antenna, the input of the non-Foster circuit having one of said at least a pair of cross coupled transistor devices associated therewith along and the output of the non-Foster circuit also having one of said at least a pair of cross coupled transistor devices associated therewith, the inductors coupled with the one of said at least a pair of cross coupled transistor devices associated said input of the non-Foster circuit having an combined larger inductance than the inductors coupled with the one of said at least a pair of cross coupled transistor devices associated said output side of the non-Foster circuit.

15. A method of reducing noise in a non-Foster circuit having at least a pair of cross coupled transistor devices, each transistor device having a pair of current carrying electrodes, the method comprising directly coupling an inductor with each of the current carrying electrodes of each of the cross-coupled transistor devices in said non-Foster circuit, the inductors also being coupled with voltage and/or current sources associated with or coupled to said non-Foster circuit.

16. The method of claim 15 wherein each transistor device also has a control electrode which is capacitively coupled with one of the current carrying electrodes of another one of said transistor devices.

17. The method of claim 15 wherein the non-Foster circuit has an input side coupled with an electrically small antenna and an output side coupled with an amplifier having a low input impedance, the low input impedance of the amplifier being substantially lower than an impedance of the electrically small antenna, the input side having one of said at least a pair of cross coupled transistor devices associated therewith along and the output side also having one of said at least a pair of cross coupled transistor devices associated therewith, the inductors coupled with the one of said at least a pair of cross coupled transistor devices associated said input side having an combined larger inductance than the inductors coupled with the one of said at least a pair of cross coupled transistor devices associated said output side.

18. The method of claim 15 wherein the pair of cross coupled transistor devices comprise a pair of cross coupled field effect transistor devices, the current carrying electrodes of each of which comprise source and drain electrodes.

19. The method of claim 15 wherein the pair of cross coupled transistor devices comprise a pair of cross coupled bipolar transistor devices, the current carrying electrodes of each of which comprise collector and emitter electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1(a) and 1(b) are schematic diagrams showing two different matching circuits for use with electrically small antennas (ESAs).

(2) FIG. 2 is a schematic of a non-Foster circuit for synthesizing a negative capacitor, but where its resistors significantly degrade the circuit's noise performance.

(3) FIGS. 3(a) and 3(b) depict two examples of non-Foster implementation architectures proposed by J. G. Linvill.

(4) FIG. 4 is a schematic diagram of a typical non-Foster circuit with bias circuits depicted, which use either resistors or current sources for biasing.

(5) FIG. 5 is a schematic diagram of a modified version of the circuit of FIG. 4 where the prior art biasing circuits are replaced by inductors to realize a lower noise figure. FIG. 5. shows N-channel devices, but P-channel enhancement mode devices may be alternatively used, as is shown by the embodiment of FIG. 5-1.

(6) FIG. 5a is similar to FIG. 5, but shows additional detailsfor example, the ESA is modeled as an inductor series with a small capacitor.

(7) FIG. 6 is a graph showing a comparison of the noise factor from the non-Foster circuit with practical current source using transistors of FIG. 4 versus the noise factor from the non-Foster circuit with inductors in the bias circuit of FIG. 5.

(8) FIG. 7 depicts the circuit simulation methodology for the comparison made in FIG. 6.

(9) FIGS. 8(a) and 8(b) depict the performances (and this allow a comparison to be made) between a passive matching antenna and a low noise non-Foster matching an electrically short antenna with 50 ohm input impedance of a low noise amplifier (found in or associated with a receiver).

(10) FIG. 9 is a schematic diagram of a low noise, bipolar transistor based non-Foster circuit.

(11) FIG. 10 depicts an embodiment of a non-Foster circuit where current sources are still used in the non-Foster circuit to define the DC bias current of the circuit, but where inductors are added to reduce the circuit's noise factor.

(12) FIGS. 11(a) and 11(b) demonstrate the results of simulations to compare an unstable (prior art) non-Foster circuit (see FIG. 11(a)) which oscillates with a two-tone input with a stable non-Foster circuit with asymmetrical loads as disclosed herein which receives a two-tone input reliably without breaking into oscillation (see FIG. 11(b)).

DETAILED DESCRIPTION

(13) Among all the components available to a circuit designer, only the capacitor and the inductor do not generate appreciable noise. However, a capacitor cannot provide a DC path to conduct current, therefore, the only option to achieve a low noise biasing network is to use inductors in the bias circuit. FIG. 5 presents an embodiment of biasing circuit, where the bias resistors or current sources in the non-Foster circuit of FIG. 4 are replaced by four passive inductors L.sub.1-L.sub.4. The desired bias current can be achieved by a bias voltage V.sub.b applied to the gates of the two depicted transistors T.sub.1 and T.sub.2 through two large (>1 M ohm) resistors R.sub.1 and R.sub.2. A supply voltage V is applied to inductors L.sub.1 and L.sub.2.

(14) Due to the extremely low series DC resistance from the inductors L.sub.1-L.sub.4 (ideally inductors have no resistance, but actual inductors which are manufactured have some DC resistance, albeit extremely low), this configuration does not suffer from the current noise of the bias circuit of the prior art embodiment of FIG. 4. And while the two bias resistors R.sub.1 and R.sub.2 each have large resistances (>1 M ohm), their noise is attenuated by the resistive-divider ratio of the low impedance generated by the non-Foster circuit core formed by the connection of the transistors T.sub.1 and T.sub.2 divided by the large resistances R.sub.1 and R.sub.2. The two depicted transistors T.sub.1 and T.sub.2 are cross coupled by means of capacitors C.sub.1 and C.sub.2. Capacitors C.sub.1 and C.sub.2 are DC blocking capacitors used for proper biasing of the transistors; they allow the drain potential to be different than the gate potential on these transistors. These two capacitors are sized such that the impedance of these capacitors should be less than the impedance of the Z.sub.L at the frequencies of interest (and preferably much less than the impedance of the Z.sub.L at the frequencies of interest).

(15) The transistor symbols used in FIG. 5 are for N-channel enhancement mode devices, but P-channel enhancement mode devices may be alternatively used, as is shown by the embodiment of FIG. 5-1. Also depletion mode transistors may be instead of the depicted enhancement mode devices in either or both of the embodiments of FIGS. 5 and 5-1, if desired.

(16) Additionally, the loads provided by inductors L.sub.1 and L.sub.2 of the non-Foster circuit of FIGS. 5 and 5-1 are preferably designed asymmetrically to enhance the stability of the circuit and thereby further optimize its performance, especially when the non-Foster circuit is driving a low impedance, such as the 50 ohm input impedance of a typical receiver which, in this embodiment, has an optional Low Noise Amplifier (LNA) at its input, the LNA typically having a 50 ohm input impedance. With load asymmetry, the load inductor in the input side, L.sub.1, has a larger inductance than the load inductor at the output side, L.sub.2. This is because the input is connected to an electrically small antenna (ESA), typically having a relatively large impedance (greater than 50 ohms), and this load asymmetry enhances stability and performance as will now be explained in greater detail. Also inductors L.sub.3 and L.sub.4 preferably have nominally identical inductance values (to simplify the design), so the total (sum of) the inductance of the two inductors L.sub.1 and L.sub.3 connected in series with current carrying electrodes of transistor T.sub.1 (and the power supply V) is thus greater than the total (sum of) inductance of the two inductors L.sub.2 and L.sub.4 connected in series with current carrying electrodes of transistor T.sub.2 (and the power supply V).

(17) FIG. 5a is similar to FIG. 5 (and somewhat less similar to FIG. 5-1 due to the conductivity change of the transistors in the embodiment of FIG. 5-1), but it will be noted that in FIG. 5a the Antenna Model for an ESA is modeled as an inductor in series with a small capacitor, which typically presents a high impedance at low frequencies to the non-Foster circuit of FIG. 5a. Also, the LNA following the non-Foster is preferably a 50 ohm matched LNA, which typically presents a low impedance (about 50 ohms) to the non-Foster circuit. So FIG. 5a illustrates the non-Foster circuit of FIG. 5 interacting with both a relatively high input impedance due to the ESA and a relatively low output impedance due to the 50 ohm input impedance of the LNA.

(18) The inductor L.sub.1 acts as a choke providing a large impedance compared to the impedance of inductor L.sub.2, so the non-Foster circuit has different source impedances. The source impedance from the antenna side is relatively large and the source impedance from LNA side is relatively small, as shown in FIG. 5a and as discussed herein. These different source impedances may trigger the non-Foster circuit into an unstable regime unless Z.sub.L1 and Z.sub.L2 are configured as will now be described. In non-Foster matching, both arms (with T.sub.1 on the antenna side and with T.sub.2 on the LNA side) of the non-Foster circuit contribute gain. The non-Foster matching delivers optimum performance when both arms of the non-Foster circuit contribute similar gain. To achieve this, we select the impedance Z.sub.L1 of inductor L.sub.1 and the impedance Z.sub.L2 of inductor L.sub.2 to enhance the stability of the non-Foster circuit. The values of Z.sub.L1 and Z.sub.L2 are selected such that the ratios Z.sub.L1/Z.sub.ant and Z.sub.L2/Z.sub.lna are approximately equal (and preferably a ratio of these two ratiosnamely Z.sub.L1/Z.sub.ant:Z.sub.L2/Z.sub.lnafalls within the range of 0.9 to 1.1 and more preferably in the range of 0.95 to 1.05.). Z.sub.ant is the impedance looking into the antenna while Z.sub.lna is the impedance looking into the LNA (or an amplifier immediately downstream of transistor T.sub.2 if no LNA is utilized).

(19) FIG. 6 is a graph showing a comparison of the noise factor from the non-Foster circuit with a conventional current source using transistors of FIG. 4 versus the noise factor from the non-Foster circuit with inductors in the bias circuit of FIG. 5, where the noise factor has been simulated using the circuit simulation methodology shown in FIG. 7. In FIG. 7 DC blocking capacitors are depicted. Whether they are needed in an actual implementation depends on the details of the antenna and the receiver (LNA) attached to the non-Foster circuit. FIG. 6 clearly shows that the low noise non-Foster circuit using inductors in a bias circuit demonstrates much better noise performance than the non-Foster circuit using conventional current source as a bias circuit.

(20) The low noise non-Foster circuit of FIGS. 5, 5-1 and 5a can be used as matching network for electrically small antennas. FIG. 8(a) shows the performance of a passive matching antenna (with 50 ohm input impedance low noise amplifier) which can be compared with FIG. 8(b) which shows the performance of the non-Foster matching circuit of FIG. 5. The simulation results suggest a non-Foster match using low noise non-Foster circuit of FIG. 5 can achieve 30 dB higher gain at 10 MHz and potentially 10 dB lower noise figure compared with passive matching of an ESA.

(21) The disclosed low noise non-Foster circuit design using inductors can be applied to other non-Foster circuit designs, including bipolar core based non-Foster circuit (shown in FIG. 9), JFET core based non-Foster circuit or other technology based non-Foster circuit. The low noise non-Foster design can also be extended to the other architectures. FIG. 10 depicts an embodiment of a non-Foster circuit where current sources CS are used in the non-Foster circuit to define the DC bias current of the circuit, but where large inductors or RF chokes are used as the degenerative circuits of the current sources to significantly reduce the noise contribution from the depicted current sources. For example, and not by way of limitation, the inductors L.sub.3 and L.sub.4 may be 1000 H, inductor L.sub.1 may be 220 H while inductor L.sub.2 may be 100 H in the embodiment of FIG. 10.

(22) The asymmetrical load approach disclosed herein can achieve a lower noise non-Foster circuit compared to the circuit without the inductors or RF chokes. A convenient by-product of this approach is that it also reduces the tendency of non-Foster circuits to oscillate. FIGS. 11(a) and 11(b) compare simulations for an unstable non-Foster circuit (FIG. 11(a)) which oscillates with a two-tone input with a stable non-Foster circuit with asymmetrical loads as disclosed herein is receiving the two-tone input reliably without breaking into oscillation (FIG. 11(b)).

(23) But having said that, there are instances when the asymmetrical load approach disclosed herein does not alone solve the oscillation problem. In such a situation, our previous stabilization circuit disclosed in U.S. patent application Ser. No. 13/542,654 filed Jul. 5, 2012, referenced above, can be utilized to help further stabilize such non-Foster circuits.

(24) Non-Foster circuits can either be a (i) Negative Impedance Inverter (NII) or (ii) a Negative Impedance Converter (NIC) and each of those can be either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS)before applying the improvements suggested herein. The disclosed embodiments depict Negative Impedance Converters (NICs) modified by utilizing four inductors L.sub.1-L.sub.4 to reduce noise. The depicted embodiments Open-Circuit-Stable (OCS) non-Foster circuits, but Short-Circuit-Stable (SCS) versions of the disclosed non-Foster circuits could be used instead and likewise Negative Impedance Inverters (NIIs) could be used instead.

(25) Without implying a limitation, the design herein according to the principals of the present inventions is for an antenna having an impedance of greater than 50 ohms. If the antenna impedance is less than 50 ohms then persons skilled in the art will know to adjust the circuit values accordingly.

(26) Having now described the invention in accordance with the requirements of the patent statute, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein.

(27) The foregoing Detailed Description of exemplary embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the patent statute. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will now be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean one and only one unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase means for . . . and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase comprising the step(s) of . . . .