ELECTRON SOURCE FOR GENERATING AN ELECTRON BEAM

Abstract

An electron source (2) for generating an electron beam (8) having a cathode (1) and an anode (4) in the form of a graphene layer (6, 12) epitaxially grown on a silicon carbide substrate (5). The invention is suitable for monolithic preparation of a miniaturized source of a high-energy focused electron beam, including its use as an on-chip X-ray source. All components can be prepared from or on a single silicon carbide chip.

Claims

1. An electron source for generating an electron beam with a cathode, wherein the electron source further comprises a substrate of the cathode featuring silicon carbide.

2. The electron source according to claim 1, wherein the cathode comprises a graphene layer epitaxially grown with the silicon carbide of the substrate.

3. The electron source according to claim 1, wherein the electron source further features an anode.

4. An electron source for generating an electron beam, comprising an anode featuring a graphene layer.

5. The electron source according to claim 3, wherein the anode is disposed on a substrate featuring silicon carbide.

6. The electron source according to claim 3, wherein the cathode and the anode are disposed on the same substrate.

7. The electron source according to claim 3, wherein the anode comprises a second substrate.

8. The electron source according to claim 3, wherein a graphene layer of the cathode is disposed such that electrons are emitted at an edge of the graphene layer of the cathode to be accelerated towards the anode.

9. The electron source according to claim 2, wherein the graphene layer of the cathode is configured as strip.

10. The electron source according to claim 3, wherein the cathode features a graphene-graphene tunnel contact or a graphene-graphene nanobridge which is arranged such as to emit electrons from the surroundings of the graphene-graphene tunnel contact or a graphene-graphene nanobridge to be accelerated towards the anode.

11. The electron source according to claim 1, wherein the cathode comprises a carbon nanotube.

12. The electron source according to claim 1, wherein the electron source features at least one electrostatic lens for focusing the electron beam.

13. The electron source according to claim 1, wherein the electron source features a dielectric resonance structure to accelerate the electrons of the electron beam.

14. The electron source according to claim 1, wherein the electron source comprises a target disposed and configured such that the electron beam impinges on the target to generate X-rays.

15. The electron source according to claim 3, wherein the electron source comprises power electronic components disposed on the same substrate as the cathode and/or the anode.

16. A method for generating an electron beam in which electrons are emitted from a cathode featuring a substrate comprising silicon carbide and/or accelerated towards an anode comprising a graphene layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Further advantageous embodiments are described in more detail below with reference to several examples of embodiments shown in the drawings, to which, however, the invention is not limited.

[0049] Schematically shown is in:

[0050] FIG. 1 the cathode of an electron source according to the invention;

[0051] FIG. 2 an electron source according to the invention with the cathode of FIG. 1, in which cathode and anode are disposed on a common substrate;

[0052] FIG. 3 the electron source of FIG. 2, further configured so that the graphene layers of the perforated anode of FIG. 2 are opposed by additional graphene layers; and

[0053] FIG. 4 an electron source according to the invention with a target for generating X-rays.

DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

[0054] In the following description of preferred embodiments of the present invention, identical reference numbers denote identical or comparable components.

[0055] FIG. 1 shows an embodiment of a cathode 1 of the electron source 2 according to the invention. The electron emission comes from an edge 3 of a graphene layer of the cathode 1, which is placed at a high negative potential. The edge 3 of the cathode 1 faces the anode 4 of the electron source 2, as shown in FIG. 2.

[0056] The electron source 2 shown in the figures is based on the material system epitaxial graphene on silicon carbide. The starting material is a silicon carbide substrate 5. Due to the material properties, an HPSI (high purity semiinsulating) 4H—SiC, which is commercially available, is particularly suitable. After wet-chemical cleaning of the semiconductor, the pedestal 9 for the emitting edge 3 is lithographically patterned and etched by a dry etching process in a reactive ion etching system (RIE). After another cleaning process, an epitaxial graphene layer 6 is subsequently prepared by thermal decomposition of the silicon carbide surface (silicon side) as known from the above cited paper by K. V. Emtsev et al, Towards wafer-size graphene layers by atmospheric pressure graphitization of silicon carbide, Nat Mater, 8 (2009) 203-207. For this purpose, the sample is heated in a furnace under argon atmosphere close to atmospheric pressure for 30 min to about 1 700° C. In a second lithography step, the graphene area 6 is defined on the pedestal and exposed by an oxygen plasma etching step. Because of this, excess graphene areas are removed. The metal contact 7 to the graphene emitter is realized in a final lithography step by vapor deposition of 5 nm titanium (Ti) and 50 nm gold (Au) followed by a lift-off process.

[0057] In an alternative embodiment of the cathode not shown in the figures, the cathode is spatially tapered by using epitaxially defined graphene strips. The graphene strips are a few nanometers wide. In operation, current flow occurs along the graphene strips, and the electrons are emitted from the edge, which is only a few nanometers short.

[0058] For preparing the graphene strips, the method described in the above-mentioned paper by M. Sprinkle et al., Scalable templated growth of graphene nanoribbons on SiC, Nature nanotechnology, 5 (2010) 727-731 can be used. Nanofacets are first produced on the (1-10n) crystal surface. This is done either by RIE dry etching of a step followed by an annealing step at about 1 200° C., as suggested by Sprinkle et al. or by a step-bunching process at 1 700° C. for a duration of 30 minutes, the sample being placed in a ceramic silicon carbide container. In a second annealing step without a silicon carbide container, graphene strips are grown on the nanofacets at a slightly lower temperature (approximately 1 400° C. to 1 500° C.). This takes advantage of the fact that graphene growth on these surfaces is faster than on the Si surface of the terraces. Further processing is carried out as described above.

[0059] The emitting edge(s) 3 of the cathode 1 shown in the figures or of the last described cathode made of graphene strips may be equipped with one or more carbon nanotubes. The method described in the afore-mentioned paper by J. R. Sanchez-Valencia et al., Controlled synthesis of single-chirality carbon nanotubes, Nature, 512 (2014) 61 is suitable for preparing these nanotubes.

[0060] In another alternative embodiment of the cathode not shown in the figures, the cathode is formed as a graphene-graphene tunnel contact or graphene-graphene nanobridge. The inventors have found that a spatially confined electron plasma, which can be used to extract electrons, is formed above the positive electrode of such a tunnel contact or nanobridge. Because of its light emission similar to blackbody radiation at 2 000 K, a corresponding energy dispersion (approximately 200 meV) is to be expected.

[0061] For preparing the graphene-graphene tunnel contact, two graphene surfaces are prepared on the pedestal using lithography and oxygen plasma etching in such a way that an only thin graphene channel of a width of approximately 50 nm connects the two graphene surfaces at the pedestal edge. Each graphene surface is contacted with a Ti/Au contact as described above. The thin graphene channel is then opened using an electroburning process so that a gap approximately one to 3 nm wide, also known as a nanogap, is formed. In the electroburning process, a voltage ramp of approximately 0 to 100 V is applied to the two Ti/Au contacts in air. This causes the current through the graphene channel to rise and to heat it up, resulting in a local “burnout” of the graphene channel. This is manifested by a drop in current at which point the voltage ramp is immediately interrupted. By repeating the process, the size of the nanogap can be adjusted via the ohmic resistance.

[0062] During operation of the electron source 2, the electrons of the electron beam 8 emitted from the cathode 1 are accelerated towards a perforated anode 4 using an extraction voltage. The simplest embodiment of such a perforated anode 4 is shown in FIG. 2. To produce this anode, both the pedestal 9 for the cathode 1 and an anode bar 10 with the interruption forming a channel 11 of the anode 4 are produced in the same RIE dry etching step. In the subsequent graphene patterning process (lithography and oxygen plasma etching), the graphene layer 12 is left on the anode bar 10 and contacted using Ti/Au contacts (not shown); no additional process step is required for this. To improve the perforated anode properties, the anode bar 10 can also be doped. For this purpose, an implantation mask for the anode bar 10 is defined lithographically prior to the graphene growth process and the latter is doped by ion implantation, for example with nitrogen ions, in such a way that a good conductivity is achieved; a suitable nitrogen concentration is 10.sup.19 cm.sup.−3. The sample is then covered with a carbon cap, the implantation damage is cured at 1 700° C. for a period of 30 minutes and the doping is activated. The carbon cap is then removed by oxidation in oxygen at 800° C. for a period of 30 minutes and the sample is cleaned again. Further preparation is as described above.

[0063] In order to realize a more exact equivalent of a conventional perforated anode, an enclosed structure can be produced by capping the previously described structure. For this purpose, a second silicon carbide substrate 13 is patterned in such a way that a mirror-image anode bar 14 for the upper side is formed, as shown in FIG. 3. This patterning is done using the same process steps as described before for the bottom side, including graphene growth. The two semiconductor wafers are then pressed together and clamped, glued, or bonded together by a wafer bonding process. As a result, the components of the electron source 2 are located inside the chip and are thus additionally protected against external influences. The electron beam 8 exits through the lateral opening of the perforated anode.

[0064] In the same way as this perforated anode, a second bar can be made (not shown in the figures) with appropriate contacts, which performs the function of a Wehnelt cylinder for adjusting the electron beam intensity.

[0065] FIG. 4 shows a further development of the electron source 2 shown in FIG. 2, which additionally features a target 15 in order to be able to be used for generating X-rays 16. For the preparation, an opening for the inclined target pedestal 17 is patterned in a further lithography step. This process step should be carried out before the patterning of the cathode pedestal 9 and the anode bar 10. The inclined target area is achieved either by an isotropic RIE dry etching step, i.e. at higher process pressure, by grayscale lithography or by selective electrochemical etching. In the latter method, aluminum is implanted under oblique incidence prior to graphene growth; the electrochemical process selectively removes the aluminum-doped areas. The target metallization is achieved by vapor deposition of metallic layers, for example copper or nickel, through a lithographically defined mask followed by a lift-off process. The metal and layer thickness depend on the specific applications. Typical layer thicknesses are in the range between 10 nm and μm1. The further process steps are carried out as described above.