METHOD AND CARRIER ELEMENT FOR PRODUCING A WAFER LAYER

Abstract

A method for producing a wafer layer, including the method steps of: A) providing a carrier element; B) making the carrier element porous on at least one surface in order to produce a separating layer; C) applying a wafer layer to the separating layer of the carrier element by epitaxy; and D) detaching the wafer layer from the carrier element, with method steps B to D being repeated at least once, preferably multiple times, with the carrier element. The method step A includes the additional method steps of: A1) providing a carrier substrate; and A2) applying a seed layer to at least one surface and at least one lateral face of the carrier substrate by epitaxy in order to produce the carrier element. A carrier element for producing a wafer layer and an intermediate product are also provided.

Claims

1. A method of producing a wafer layer (5), comprising the following method steps: A providing a carrier element (1); B porosifying the carrier element (1) on at least one surface for creation of a separation layer (4); C epitaxially applying a wafer layer (5) to the separation layer (4) of the carrier element (1); and D detaching the wafer layer (5) from the carrier element (1), wherein method steps B to D are repeated at least once with the carrier element (1); and method step A comprises the further method steps of A1 providing a carrier substrate (2); and A2 epitaxially applying a seed layer (3) to at least one surface and at least one lateral face of the carrier substrate (2) for production of the carrier element (1).

2. The method as claimed in claim 1, wherein the seed layer (3) is applied so as to ensheath the one surface and all of the lateral faces of the carrier substrate (2).

3. The method as claimed in claim 1, wherein the carrier substrate (2) and the seed layer (3) have been formed or are formed from silicon, germanium or gallium arsenide.

4. The method as claimed in claim 1, wherein the carrier substrate (2) is n-doped or p-doped, and a dopant concentration is in a region of less than 5×10.sup.19 cm.sup.31 3.

5. The method as claimed in claim 1, wherein the seed layer (3) is applied on the at least one surface of the carrier substrate (2) with a layer thickness (8) in a range from 10 μm to 250 μm.

6. The method as claimed in claim 1, wherein the seed layer (3) is dope , during the application with a dopant concentration in a range from 1×10.sup.16 cm.sup.−3 to 5×10.sup.19 cm.sup.−.

7. The method as claimed in claim 1, further comprising: applying, forming, or disposing a contact layer (6) on the surface of the carrier substrate (2) remote from the seed layer (3) before, during or after the application of the seed layer (3).

8. The method as claimed in claim 7, wherein the contact layer (6) has been formed or is formed from polycrystalline semiconductor.

9. The method as claimed in claim 7, wherein the contact layer (6) has a thickness in a range from 0.1 to 20 μm.

10. The method as claimed in claim 7, further comprising forming the contact layer (6) by diffusion of a diffusion layer on the surface of the carrier substrate (2) remote from the seed layer (3) into the carrier substrate (2).

11. The method as claimed in claim 1, wherein the seed layer (3) is applied to the carrier substrate (2) with an inhomogeneous layer thickness (8), and the inhomogeneous layer thickness (8) increases or decreases at least toward one, of two opposite ones of the lateral faces of the carrier substrate (2).

12. A carrier element (1) for production of a wafer layer (5), the carrier element comprising: a carrier substrate (2); an epitaxial seed layer (3) applied to at least one surface and at least one lateral face of the carrier substrate (2); and a separation layer (4) formed by porosifying of the at least one surface of the epitaxial seed layer (3).

13. The carrier element (1) as claimed in claim 12, wherein the seed layer (3) on the at least one surface of the carrier substrate (2) has a layer thickness (8) in a range from 10 μm to 250 μm.

14. The carrier element (1) as claimed in claim 12, wherein the seed layer (3) has a greater layer width (9) than layer thickness (8) on the at least one surface.

15. The carrier element (1) as claimed in claim 12, further comprising a contact layer (6) disposed on the surface of the carrier substrate (2) remote from the seed layer (3).

16. An intermediate product (10) comprising the carrier element (1) as claimed in claim 12 and an epitaxial wafer layer (5) disposed on the separation layer (4).

17. The method as claimed in claim 1, wherein the seed layer (3) is applied on the at least one lateral face of the carrier substrate (2) with a layer width (9) in a range from 10 μm to 600 μm.

18. The method as claimed in claim 7, wherein material the contact layer (6) is formed or disposed so as to protrude beyond the carrier substrate (2).

19. The method of claim 10, wherein the diffusion layer is formed by a holding element for holding the carrier substrate (2) during method step A2, or is applied prior to method step A2 on the surface of the carrier substrate (2) remote from the seed layer (3).

20. The carrier element (1) as claimed in claim 12, wherein the seed layer (3) on the at least one lateral face of the carrier substrate (2) has a layer width (9) in the range from 10 μm to 600 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0091] Further advantageous features and configurations are elucidated hereinafter with reference to working examples and the figures. The figures show:

[0092] FIGS. 1A to 1D one working example of a method of the invention for production of a wafer layer;

[0093] FIG. 2 one working example of a carrier element of the invention; and

[0094] FIGS. 3A and 3B further working examples of a carrier element of the invention.

DETAILED DESCRIPTION

[0095] All figures are schematic diagrams that are not true to scale. In the figures, identical reference numerals denote elements that are the same or have the same effect. In FIGS. 1A-1D, 2, and 3A-3B, a surface of a carrier substrate 2 or of a carrier element 1 to which a seed layer 3 is applied is always at the top.

[0096] FIGS. 1A to 1D show a process of the invention for producing a wafer layer.

[0097] As shown in FIG. 1A, a seed layer 3 was deposited on a carrier substrate 2 provided in a method step A1, in a method step A2, by means of epitaxy to form a carrier element 1 which is used for production of a wafer layer 5. The seed layer 3 fully ensheaths the carrier substrate 2 on an upper surface and the lateral faces. The lower face of the carrier substrate 2 remote from the upper surface is not covered by the seed layer 3.

[0098] The carrier substrate 2 is a semiconductor, especially composed of silicon, which has been produced in a zone melting or crystal growing method. The thickness of the carrier substrate 2 is in the range from 250 μm to 1000 μm. The carrier substrate 2 has a square basic shape, the lateral edges of which have a length of 100 mm to 300 mm, especially of 140 to 170 mm. As well as a square basic shape, the carrier substrate 2 may also have a pseudo-square shape with tapered/rounded corners, or a round, oval or rectangular shape.

[0099] The carrier substrate 2, in lateral direction, has a dimension 12 adjoined by the layer width 9 of the seed layer 3 on the lateral faces of the carrier substrate 2, such that the carrier element 1 overall has a lateral dimension 11.

[0100] The seed layer 3 has been applied with a layer thickness 8 atop the surface of the carrier substrate 2. The layer thickness 8, as shown in FIG. 1A, is essentially identical to the layer width 9.

[0101] The seed layer 3 has been applied atop the carrier substrate 2 by means of epitaxy, especially by means of chemical gas phase deposition. By epitaxy, it is possible to form high-quality layers, which is a crucial starting point for the production of correspondingly high-quality seed layers 3. More particularly, by epitaxy, the seed layer 3 can be adjusted to the necessary requirements, especially with regard to crystal quality and electrical properties, for a downstream process.

[0102] In a process step B that follows the production of the carrier element 1, a porous separation layer 4 is formed on the surface and at least partly on the lateral edges of the carrier element 1 and hence on the surface and at least partly on the lateral edges of the seed layer 3, as shown in FIG. 1B. The separation layer 4 has a thickness of up to 3 μm, in the present case about 2 μm. The formation of the separation layer 4 on the carrier element 1 is effected by means of etching, especially porosification, and can be conducted, for example, as described in DE 10 2013 219 886 A1. The method described enables formation of the separation layer 4 over the full surface area of the carrier element 1.

[0103] In a further method step C, an epitaxial wafer layer 5 is deposited on the separation layer 4 of the carrier element 1. The wafer layer 5 partly overlaps the lateral faces of the carrier element 1 and can extend further even beyond some of the lateral faces of the carrier element 1. The broadened formation of the wafer layer 5 ensures a high quality of the wafer layer 5 virtually up to its edge region. This is shown in FIG. 1C.

[0104] The product comprising the carrier element 1 and the wafer layer 5 is also referred to as intermediate product 10.

[0105] In a further method step, the intermediate product 10 thus produced, composed of carrier element 1 and wafer layer 5, is trimmed at the lateral faces of the carrier element 1. The trimming removes portions 7 of the wafer layer 5 that protrude beyond the carrier element 1, and possibly also further portions of the wafer layer 5 adhering to the lateral faces of the carrier element 1, as shown in FIG. 1D.

[0106] The trimming is effected by a laser beam. Alternatively, the trimming can also be effected by mechanical processing such as sawing or grinding. More particularly, the trimming achieves the effect that portions of the wafer layer 5 adhering to the carrier element 1 are removed, so as to enable reuse of the carrier element 1. However, it is usually necessary for this purpose also to remove a minimal amount of the carrier element 1 at its lateral faces, so as to result in a lateral dimension 11′ lower than the original lateral dimension 11 after method step A.

[0107] After the trimming of the intermediate product 10, in a method step D, the wafer layer 5 is detached from the carrier element 1.

[0108] The carrier element 1, after the detachment of the wafer layer 5, again undergoes method steps B to D, as shown in FIGS. 1B to 1D, for production of a further wafer layer 5.

[0109] A lower lateral dimension 11′ of the carrier element 1 does not adversely affect the production of the wafer layer 5, provided that the carrier element 1 is free of residues of any previously applied wafer layer 5 and the lower lateral dimension 11′ of the carrier element 1 and especially preferably also the thickness of the carrier element 11 is not below a minimum dimension. Therefore, a cycle of method steps B and D is repeated as often as desired until the dimensions of the carrier element 1 are equal to or slightly below the minimum dimensions.

[0110] A lower limit for the minimum dimension is the lateral dimension 12 and also the thickness of the carrier substrate 2. As soon as the lateral dimension 11′ approaches the lateral dimension 12 or the corresponding thickness of the carrier element 1 approaches the thickness of the carrier substrate 2, the carrier element 1 is processed by the performance of method step A2 and the resulting new application of a seed layer 3 to the carrier element 1 or the carrier substrate 2.

[0111] Prior to the new performance of method step A2 on an already utilized carrier element 1, this carrier element 1 or the carrier substrate 2 may be subjected to a first processing operation, such that the formation of a high-quality seed layer 3 on the carrier element 1 that was already being utilized can in turn be enabled. For this purpose, the carrier element 1 provided for reuse, or the carrier substrate 2, can be processed by mechanical treatment such as polishing or grinding or chemical treatments such as etching or a combination of chemical and mechanical treatment prior to method step A2, such that this especially has a high-quality surface, atop which the seed layer 3 is subsequently applied.

[0112] If the dimension 11′ of the carrier element 1 essentially corresponds to the dimensions 12 of the carrier substrate 2, for reprocessing of the carrier element 1, a new seed layer 3 is formed on the previously used carrier substrate 2, such that it is reprocessed to give a carrier element 2 with its original lateral dimension 11, as shown in FIG. 1A. This reprocessed carrier element 1 is then utilized further for the production of wafer layers 5 without having to use a new carrier substrate 2 here. As a result of the reprocessing of the carrier element 1, a carrier substrate 2 can thus be used at least 50 times for the production of wafer layers 5, as shown in FIGS. 1B to 1D.

[0113] The layer thickness 8, and also the layer width 9, of the seed layer 3 is within a range from 10 μm to 250 μm, preferably in the range from 25 μm to 100 μm, more preferably in the range from 40 μm to 80 μm. A layer thickness 8, and also layer width 9, of the seed layer 3 as specified above has the advantage of generation of a high-quality seed layer 3 which is also producible within a period which is correspondingly acceptable in terms of the process.

[0114] In accordance with the defined parameters such as quality for the production of the wafer layer 5, the carrier substrate 2, and also the seed layer 3, may contain doping or not need any doping.

[0115] More particularly, the carrier substrate 2 has n-doping or p-doping with a dopant concentration in the region of less than 5×10.sup.19 cm.sup.−3, preferably in the region of less than 1×10.sup.18 cm.sup.−3, more preferably in the region of less than 1×10.sup.17 cm.sup.−3, most preferably in the region of less than 5×10.sup.15 cm.sup.−3, in the present case p-doping by means of boron as dopant with a dopant concentration of 1.5×10.sup.16 cm.sup.−3. The production of doped carrier substrates 2 by means of zone melting or crystal growing methods is associated with the input of extraneous matter into the crystal structure, especially of metallic, oxidic, nitridic or carbidic extraneous matter, and the formation of agglomerates, which ultimately lowers the overall quality and goodness of the carrier substrate 2 by virtue of extraneous matter and a nonuniform distribution of the dopants.

[0116] The starting point for high-quality layers is carrier substrates 2 and seed layers 3 that are already of high quality. Therefore, high-quality and therefore usually also high-value substrates should find use as carrier substrates 2, since the quality of the carrier substrate 2 ultimately also has a crucial influence on the quality of the wafer layer 5. Therefore, carrier substrates 2 having only a low dopant concentration preferably find use. The carrier substrates 2, if they are doped, have p-doping, especially with the element boron.

[0117] As a result of the much greater frequency of use of a carrier substrate 2 with up to 150 uses or more, the higher initial costs for a higher-quality carrier substrate 2 in the production of the wafer layers 5 are of no consequence, such that a further reduction in costs for the production of a wafer layer 5 is achieved with improved quality.

[0118] However, it is especially advantageous in method step B for the formation of the separation 4 when the carrier element 1 has doping. This is enabled in the present case by the doping, especially by p-doping, of the seed layer 3 on which the separation layer 4 is formed by porosification. The seed layer here has a dopant concentration in the range from 1×10.sup.16 cm.sup.−3 to 5×10.sup.19 cm.sup.−1, preferably in the range from 1×10.sup.17 cm.sup.−3 to 3×10.sup.19 cm.sup.−3, especially in the range from 1×10.sup.18 cm.sup.−3 to 1×10.sup.19 cm.sup.−3, in the present case p-doping with the doping element boron as dopant of 5×10.sup.18 cm.sup.−3.

[0119] The epitaxial formation of the seed layer 3 additionally results in more homogeneous doping of the seed layer with the doping element and with a distinctly reduced input of extraneous matter, especially by up to a factor of 100, since the doping elements or dopants in epitaxy are in a particularly high purity. Moreover, the input of oxygen, which is partly responsible for induced stacking defects in the wafer layer 5, into the crystal structure is also reduced by the epitaxy by up to a factor of 20. The more uniform doping also results in more uniform formation of the separation layer 4 on the seed layer 3, which in turn has a positive effect on the quality of the wafer layer 5 produced thereon.

[0120] FIG. 2 shows a particular embodiment of the carrier element 1. The carrier element 1 in turn has a carrier substrate 2 and a seed layer 3, with the seed layer 3 having been applied atop the carrier substrate 2 with a greater layer width 9 compared to the layer thickness 8.

[0121] After each production process of a wafer layer 5 in method steps B to D, the lateral dimension 11 of the carrier element 1, and also the layer thickness 8 of the seed layer, is reduced. The lateral dimensions 11′ of the carrier element 1 are reduced especially as a result of the trimming of the wafer layer 5 or of the carrier element 1 for assurance of the complete removal of the wafer layer 5 prior to the production of a further wafer layer 5. The layer thickness 8 of the seed layer 3 also decreases with each etching operation in method step B.

[0122] As a result of the trimming, the lateral dimension 11 of the carrier element 1 decreases more significantly with each wafer layer 5 than the layer thickness 8 of the seed layer 3 as a result of the porosification. More particularly, the trimming of the lateral faces of the carrier element is subject to greater fluctuation and also depends on the corresponding trimming device. For reduction of production costs for a wafer layer 5, trimming devices used are especially also those that have a greater tolerance in relation to the removal of material at the lateral faces of the carrier element 1 that are in the range from 2 μm to 20 μm, in the present case about 5 μm. In order to enable a maximum possible number of cycles for production of a wafer layer 5 with a single carrier element 1 prior to processing thereof, therefore, increased formation of the layer width 9 of the seed layer 3 compared to the layer thickness 8 of the seed layer 3 is advantageous.

[0123] FIGS. 3A and 3B each show a carrier element 1 having a contact layer 6 on the surface of the carrier substrate 1 remote from the seed layer 3.

[0124] The contact layer 6, prior to the application of the seed layer 3, has been applied to or bonded to the carrier substrate 2 by means of gas phase deposition or diffusion. Alternatively, application of the contact layer 6 during or after the application of the seed layer 3 is within the scope of the invention. The contact layer 6 is applied prior to method step B, since good contacting of the carrier element 1 is important for the process of porosification in method step B.

[0125] The contact layer 6 is formed from a polycrystalline semiconductor material, especially from polysilicon, which enables good dry contactability during the porosification of the carrier element 1. For good contactability, especially good dry contactability, of the contact layer, it has electrical properties at least similar to the electrical properties of a metal.

[0126] The lateral dimension of the contact layer 6 corresponds approximately to the lateral dimension 12 of the carrier substrate 2, or even goes beyond the lateral dimension 12 of the carrier substrate 2. More particularly, the lateral dimension of the contact layer 6 may also be less than the lateral dimension 11 of the carrier element 1. The thickness of the contact layer 6 is within a range from 0.1 to 20 μm, in the present case about 10 μm, and is thus well below the thickness of the carrier substrate 2 and is also less than the layer thickness 8.

[0127] As shown in FIG. 3A, the contact layer 6 has a greater lateral dimension than the carrier substrate 2, which is identical to the lateral dimension 11 of the carrier element 1. This also results in a distinctly greater layer width 9 compared to the layer thickness 8. During one cycle of method steps B to D, the lateral decrease in size as a result of the trimming of the carrier element 1 and the subsequent detachment of the wafer layer 5 is greater than the reduction in layer thickness 8. It is therefore advantageous to apply the carrier element 1 with a greater layer width 9 compared to the layer thickness 8 on the carrier substrate 1.

[0128] The formation of the contact layer 6 over the full area always ensures good, especially dry, contacting irrespective of the reduction in the lateral dimensions 11 of the carrier element 1 after the detachment of a wafer layer 5.

[0129] List of Reference Numerals

[0130] 1 carrier element

[0131] 2 carrier element

[0132] 3 seed layer

[0133] 4 separation layer

[0134] 5 wafer layer

[0135] 6 contact layer

[0136] 7 portion

[0137] 8 layer thickness

[0138] 9 layer width

[0139] 10 intermediate product

[0140] 11, 11′ dimension of carrier element

[0141] 12 dimension of carrier substrate