Method for Producing Radiation-Emitting Semiconductor Chips, Radiation-Emitting Semiconductor Chip and Radiation-Emitting Component

Abstract

In an embodiment a method for producing radiation-emitting semiconductor chips includes providing a semiconductor wafer, applying first contact layers on the semiconductor wafer, applying a second dielectric layer on the semiconductor wafer and the first contact layers, attaching a carrier arrangement to the semiconductor wafer, singulating the semiconductor wafer into semiconductor bodies and applying second contact layers on the semiconductor bodies, wherein the second dielectric layer is formed such that it mechanically stabilizes itself.

Claims

1.-20. (canceled)

21. A method for producing radiation-emitting semiconductor chips, the method comprising: providing a semiconductor wafer; applying first contact layers on the semiconductor wafer; applying a second dielectric layer on the semiconductor wafer and the first contact layers; attaching a carrier arrangement to the semiconductor wafer; singulating the semiconductor wafer into semiconductor bodies; and applying second contact layers on the semiconductor bodies, wherein the second dielectric layer is formed such that it mechanically stabilizes itself.

22. The method according to claim 21, further comprising: forming a sacrificial layer in a single contiguous manner on the semiconductor wafer, wherein the carrier arrangement comprises a second carrier layer and a third carrier layer, and wherein the second carrier layer is applied to the sacrificial layer.

23. The method according to claim 21, further comprising, after applying the first contact layers, creating a sacrificial layer penetrated by openings on the semiconductor wafer, wherein the carrier arrangement is fixed to the sacrificial layer, wherein holding elements of the carrier arrangement are each formed in an opening of the sacrificial layer, and wherein the sacrificial layer is removed in such a way that the carrier arrangement is mechanically connected to the semiconductor bodies only in a region of the holding elements.

24. The method according to claim 21, further comprising: applying a first dielectric layer the semiconductor wafer; and creating first recesses in the first dielectric layer, wherein the first contact layers are arranged in each of the first recesses.

25. The method according to claim 24, wherein the second dielectric layer is applied to the first dielectric layer.

26. The method according to claim 25, further comprising: forming fourth recesses in the second dielectric layer, each fourth recess overlapping in lateral directions with one of the first recesses; and arranging first contacts in each of the fourth recesses, wherein each of the first contacts are in electrically conductive contact with one of the first contact layers in one of the fourth recesses.

27. The method according to claim 25, further comprising: forming fifth recesses spaced apart in lateral directions from the first recesses in the second dielectric layer; and arranging second contacts in each of the fifth recesses.

28. The method according to claim 27, further comprising: applying further second contact layers on side surfaces of the passivation layer, wherein the second contact layers and the further second contact layers each electrically conductively connect one of the second contacts with a respective one of the exposed semiconductor bodies.

29. The method according to claim 21, further comprising applying a passivation layer over the semiconductor bodies, after singulating the semiconductor wafer.

30. The method according to claim 29, further comprising: forming second recesses in the passivation layer, the second recesses being spaced apart in lateral directions from the semiconductor bodies; and forming third recesses, each overlapping in lateral directions with one of the semiconductor bodies in the passivation layer, wherein each of the third recesses exposes a region of one of the semiconductor bodies.

31. The method according to claim 30, wherein each of the second contact layers is applied to one of the exposed semiconductor bodies.

32. The method according to claim 29, further comprising applying further first contact layers on side surfaces of the passivation layer, wherein each of the further first contact layers is electrically conductively connected with one of the first contact layers in a respective one of the second recesses.

33. A radiation emitting semiconductor chip comprising: a semiconductor body configured to emit electromagnetic radiation; a first contact layer; a second contact layer; and a second dielectric layer arranged on the semiconductor body and the first contact layer, wherein the second dielectric layer mechanically stabilizes itself, and wherein a current is impressable into the semiconductor body through the first contact layer and the second contact layer.

34. The radiation emitting semiconductor chip according to claim 33, wherein the first contact layer and the second contact layer comprise a transparent conductive material.

35. The radiation emitting semiconductor chip according to claim 33, wherein the first contact layer is arranged on a bottom surface of the semiconductor body, and wherein the first contact layer extends from the bottom surface of the semiconductor body into the semiconductor body.

36. A radiation emitting device comprising: the radiation emitting semiconductor chip according to claim 33; and a carrier comprising at least a first contact element, wherein the radiation emitting semiconductor chip is arranged on the carrier by a direct bond connection and/or an adhesive.

37. The radiation emitting device according to claim 36, wherein the carrier and/or the first contact element are configured to be transparent to the electromagnetic radiation emitted by the semiconductor body.

38. The radiation emitting device according to claim 36, wherein the first contact element is configured to be reflective for the electromagnetic radiation emitted by the semiconductor body.

39. The radiation emitting device according to claim 38, wherein the first contact element comprises a curved shape.

40. A radiation-emitting semiconductor chip comprising: a semiconductor body configured to emit electromagnetic radiation; a first contact layer; and a second contact layer, wherein a current is impressable into the semiconductor body through the first contact layer and the second contact layer, and wherein the radiation-emitting semiconductor chip exclusively comprises components which are configured to be transparent to the electromagnetic radiation emitted by the semiconductor body.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0112] In the following, the method for producing a radiation-emitting semiconductor chip, the radiation-emitting semiconductor chip, and the radiation-emitting device will be explained in more detail with reference to exemplary embodiments and the accompanying figures.

[0113] FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 show schematic sectional views of method stages in producing a radiation-emitting semiconductor chip according to an exemplary embodiment;

[0114] FIGS. 17, 18, 19, 20, 21, 22, and 23 show schematic sectional views of a radiation emitting semiconductor chip with a carrier arrangement according to an exemplary embodiment, respectively;

[0115] FIG. 24 shows schematic sectional views of a method stage in producing a radiation-emitting semiconductor chip according to an exemplary embodiment;

[0116] FIGS. 25 and 26 show schematic sectional views of a radiation emitting semiconductor chip according to an exemplary embodiment, respectively; and

[0117] FIGS. 27, 28, 29, 30, 31, and 32 show schematic sectional views of a radiation-emitting device according to an exemplary embodiment, respectively.

[0118] Elements that are identical, of the same kind or have the same effect are provided with the same reference signs in the figures. The figures and the proportions of the elements shown in the figures are not to be regarded as to scale. Rather, individual elements may be shown exaggeratedly large for better illustration and/or for better comprehensibility.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0119] According to FIG. 1, in a method step for producing a radiation-emitting semiconductor chip 1, a semiconductor wafer 2 is first provided. The semiconductor wafer 2 comprises a first semiconductor layer sequence 3 and a second semiconductor layer sequence 3. Here, the semiconductor wafer 2 is epitaxially grown on a growth substrate 16. The first semiconductor layer sequence 3 is p-doped in this exemplary embodiment, and the second semiconductor layer sequence 4 is n-doped in this exemplary embodiment.

[0120] A first dielectric layer 17 is applied onto the semiconductor wafer 2, in particular onto the first semiconductor layer sequence 3. The first dielectric layer 17 is in direct contact with the semiconductor wafer 2. Here, the first dielectric layer 17 comprises two first dielectric layers 17. In this case, the first dielectric layer 17 facing the semiconductor wafer 2 comprises silicon dioxide and has a thickness of at most 50 nm. The first dielectric layer 17 facing away from the semiconductor wafer 2 comprises aluminum oxide and also comprises a thickness of at most 50 nm.

[0121] According to FIG. 2, first recesses 18 are created in the first dielectric layer 17 in a further method step. The first recesses 18 completely penetrate the first dielectric layer 17 and expose the semiconductor wafer 2, in particular the first semiconductor layer sequence 3, in regions.

[0122] Subsequently, first contact layers 5 are applied onto the semiconductor wafer 2, in particular onto the first semiconductor layer sequence 3. In this exemplary embodiment, the first contact layers 5 are each arranged in one of the first recesses 18. The first contact layers 5 are in direct contact with the semiconductor wafer 2 in the region of the first recesses 18. In this exemplary embodiment, the first contact layers 5 comprise a TCO, such as ITO. A thickness of the first contact layers 5 in this case is at most 50 nm. Thus, the thickness of the first contact layers 5 is smaller than the thickness of the first dielectric layers 17.

[0123] In this exemplary embodiment, the first contact layers 5 cover a large extent of a top surface of the first semiconductor layer sequence 3. Here, to a large extent means that the first contact layers 5 each cover at least 70% of the top surface of the first semiconductor layer sequence 3.

[0124] In the method step as shown in FIG. 3, a second dielectric layer 20 is applied over the first dielectric layer 17 and the first contact layers 5. Here, the second dielectric layer 20 is in direct contact with the first dielectric layer 17 and the first contact layers 5. In this exemplary embodiment, the second dielectric layer 20 comprises silicon dioxide and has a thickness of about 1 μm.

[0125] In a further method step according to FIG. 4, fourth recesses 26 each overlapping in lateral directions with one of the first recesses 18 are created in the second dielectric layer 20. Further, fifth recesses 28 spaced apart in lateral directions from the first recesses 18 are created in the second dielectric layer 20. The fourth recesses 26 and the fifth recesses 28 completely penetrate the second dielectric layer 20. Here, the fourth recesses 26 expose the first contact layers 5 in regions and the fifth recesses 28 expose the first dielectric layers 5 in regions.

[0126] Further, first singulation trenches 39 are created in the second dielectric layer 20 that are spaced apart in lateral directions from the first recesses 18. The first singulation trenches 39 are each arranged here between one of the fourth recesses 26 and one of the fifth recesses 28. The first singulation trenches 39 completely penetrate the second dielectric layer 20. Further, the first singulation trenches 39 expose the first dielectric layers in regions.

[0127] As shown in FIG. 5, first contacts 27 are each arranged in one of the fourth recesses 26. The first contacts 27 completely cover the surfaces limiting the fourth recesses 26. Furthermore, second contacts 29 are arranged in one of the fifth recesses 28, respectively. The second contacts 29 completely cover the surfaces limiting the fifth recesses 28. The first contacts 27 and the second contacts 29 both comprise an electrically conductive metal. Furthermore, the first contacts 27 are each in electrically conductive contact with one of the first contact layers 5 in one of the fourth recesses 26.

[0128] In the method step according to FIG. 6, a sacrificial layer 6 is applied onto the semiconductor wafer 2, in particular onto the first semiconductor layer sequence 3. In this exemplary embodiment, the sacrificial layer 6 comprises silicon.

[0129] According to FIG. 7, openings 7 are created in the sacrificial layer 6, which completely penetrate the sacrificial layer 6 and expose the second dielectric layer 20 in regions.

[0130] On top of the sacrificial layer 6, a carrier arrangement 8 is attached to the sacrificial layer 6 in conjunction with FIGS. 8, 9 and 10.

[0131] As shown in FIG. 8, a first carrier layer 10 is applied over the sacrificial layer 6. The first carrier layer 10 completely covers the sacrificial layer 6 and is also arranged in the openings 7. In this exemplary embodiment, the first carrier layer comprises aluminum oxide and comprises a thickness of at least 50 nm and at most 500 nm.

[0132] Subsequently, as shown in FIG. 9, a second carrier layer 11 is applied over the first carrier layer 10. The second carrier layer 11 fills the openings 7 and projects vertically above the openings 7. In this exemplary embodiment, the second carrier layer comprises an adhesion promoting material, such as benzocyclobutene.

[0133] In a subsequent method step, a third carrier layer 12 is arranged over the second carrier layer 11, as shown in FIG. 10. In this exemplary embodiment, the third carrier layer 12 is an auxiliary carrier.

[0134] Furthermore, holding elements 9 arranged in the openings 7 are defined by the carrier arrangement 8. In this exemplary embodiment, the first carrier layer 10 and the second carrier layer 11 are arranged in the openings and form the holding elements 9.

[0135] In the method step according to FIG. 11, the growth substrate 16 is detached from the semiconductor layer sequence 2.

[0136] FIG. 12 shows a further method step in which the semiconductor wafer 2 is singulated to form semiconductor bodies 13. For example, the semiconductor wafer 2 is singulated into semiconductor bodies 13 by cuts in vertical direction through the semiconductor wafer 2. The cuts completely penetrate the semiconductor wafer 2 in this exemplary embodiment.

[0137] According to FIG. 13, a passivation layer 21 is applied over the semiconductor bodies 13 in this method step. The passivation layer 21 completely covers an outer surface of the semiconductor bodies 13 facing away from the carrier arrangement 8. Furthermore, the passivation layer 8 completely covers a bottom surface of the first dielectric layer 17 facing away from the carrier arrangement 8. In this exemplary embodiment, the passivation layer comprises silicon dioxide.

[0138] As shown in connection with FIG. 14, in a further method step, second recesses 22 spaced apart in lateral directions from the semiconductor bodies 13 are created in the passivation layer 21. In this exemplary embodiment, the second recesses 22 also completely penetrate the first dielectric layer 17. Here, the second recesses 22 expose a region of the second contact 29.

[0139] Furthermore, third recesses 23 each overlapping with one of the semiconductor bodies 13 in lateral directions are created in the passivation layer 21. The third recesses 23 penetrate the passivation layer 8 completely, for example. The third recesses 23 each expose one of the semiconductor bodies 13, in particular the second semiconductor layer sequence 4, in regions.

[0140] Furthermore, second singulation trenches 40 each overlapping in lateral directions with one of the first singulation trenches 39 are created in the first dielectric layer 17. The second singulation trenches 40 completely penetrate the first dielectric layer 17. Furthermore, the second singulation trenches 40 expose the sacrificial layer 6 in regions.

[0141] FIG. 15 shows another method step in which second contact layers 14 are applied onto the semiconductor bodies 13 exposed by the third recesses 23. Here, the second contact layers 14 are in direct contact with the semiconductor bodies 13, in particular the second semiconductor layer sequence 4. The second contact layers 14 completely fill the third recesses 23 and project beyond the passivation layer 21 in the vertical direction. Furthermore, the second contact layers 14 project beyond the third recesses 23 in lateral directions and are arranged on the passivation layer 21 in regions.

[0142] Furthermore, further second contact layers 30 are applied onto side surfaces of the passivation layer 21. The further second contact layers 30 completely fill the second recesses 22. The second contact layers 14 and the further second contact layers 30 each electrically conductively connect one of the second contacts 29 with a respective one of the exposed semiconductor bodies 13, in particular the second semiconductor layer sequence 4.

[0143] In this exemplary embodiment, the second contact layers 14 and the further second contact layers 30 comprise a TCO, such as ITO. In this case, the further second contact layers 30 on the side surface of the passivation layer 21a comprise a thickness of at least 50 nm and at most 20 nm. Furthermore, the further first contact layers 30 in this exemplary embodiment are formed on the side surfaces of the passivation layer 21a as a ridge, which comprises a width of at most 5 μm.

[0144] In a further step according to FIG. 16, the sacrificial layer 6 is removed in such a way that the carrier arrangement 8 is mechanically connected to the semiconductor bodies 13 only in the region of the holding elements 9. In this exemplary embodiment, the sacrificial layer 6 is removed by a chemical etching process.

[0145] The radiation-emitting semiconductor chips 1 are thus mechanically connected to the carrier arrangement 8 only through the holding element 9. Advantageously, the created semiconductor chips 1 can thus be printed on a terminal component by means of the carrier arrangement 8.

[0146] The radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 17, in contrast to the exemplary embodiment of FIG. 16, comprises first contact layers 5 which comprise a reflective, electrically conductive metal. Furthermore, the further second contact layers 30 are a reflective, electrically conductive metal. In this exemplary embodiment, the further first contact layers 30 cover the side surfaces of the passivation layer 21a to a large extent.

[0147] In this exemplary embodiment, the first contact layers 5 and the further second contact layers 30 are reflective to electromagnetic radiation generated in the semiconductor bodies 13.

[0148] In this exemplary embodiment, second contact layers 14 cover a large extent of a bottom surface of the second semiconductor layer sequence 4. Here, to a large extent means that the second contact layers 14 each cover at least 90% of the bottom surface of the second semiconductor layer sequence 4. Through such second contact layers 14, the radiation generated in the semiconductor bodies 13 can be coupled out.

[0149] The radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 18 comprises, in contrast to the exemplary embodiment of FIG. 17, further reflective mirrors 38 which partially cover side surfaces of the semiconductor bodies 13, in particular side surfaces of the first semiconductor layer sequence 3. The further reflective mirrors 38 are formed, for example, with the same materials as the first contact layers 5. Thus, in this exemplary embodiment, the further reflective mirrors 38 are formed to be reflective for electromagnetic radiation generated in the semiconductor bodies 13.

[0150] Advantageously, the reflectively formed first contact layers 5, the further second contact layers and the further reflective mirrors 38 each completely enclose a semiconductor body 13 except for the transparently formed second contact layers 14.

[0151] In the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 19, the first contacts 27 and the second contacts 29 are formed with a TCO, in contrast to the exemplary embodiment of FIG. 16.

[0152] In contrast to the exemplary embodiments of FIGS. 16, 17, 18 and 19, the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 20 does not comprise first contacts 27 and second contacts 29. Accordingly, fourth recesses 26 and fifth recesses 28 are also not arranged in the second dielectric layer 20.

[0153] In this exemplary embodiment, the second semiconductor layer 4 in the region per semiconductor body 13 can be electrically conductively contacted only by the second contact layers 14. Thus, the semiconductor chip 1 here comprises no further second contact layers 30.

[0154] Furthermore, further first contact layers 25 are arranged on side surfaces of the passivation layer 21a. The further first contact layers are also arranged on the bottom surface of the passivation layer 21.

[0155] The further first contact layers 25 are each electrically conductively connected with one of the first contact layers 5 in a respective one of the second recesses 22.

[0156] The further first contact layers 25 here comprise the same materials as the first contact layers 5, such as a TCO in this exemplary embodiment. The further first contact layers 25 are formed as a ridge on the side surfaces of the passivation layer 21a. In this case, the ridge comprises a width of 5 μm or less.

[0157] In the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 21, the further first contact layers 25 and the second contact layers 14 are formed with a reflective, electrically conductive metal, in contrast to the exemplary embodiment of FIG. 20.

[0158] Furthermore, a reflective mirror 31 is arranged between the semiconductor bodies 13, in particular the second semiconductor layer sequence 4, and the passivation layer 21.

[0159] According to the exemplary embodiment of FIG. 22, the second semiconductor layer 4 of each semiconductor body 13 is electrically conductively connected with a second contact 29 as in the exemplary embodiment of FIG. 16. However, the semiconductor chip 1 does not comprise any first contacts 27. Further second recesses 24 spaced apart in lateral directions from the semiconductor bodies 13 and the second recesses 22 are created in the passivation layer 21. The further second recesses 24 completely penetrate the passivation layer 21. Further first contact layers 25, arranged on a lateral surface of the passivation layer 21, are each electrically conductively connected with one of the first contact layers 5 in a respective one of the further second recesses 24.

[0160] In contrast to the exemplary embodiment of FIG. 22, the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 23 comprises first contacts 27.

[0161] In the method stage according to the exemplary embodiment of FIG. 24, the radiation-emitting semiconductor chip 1 is mechanically attached to a carrier arrangement 8, in contrast to the method stages according to the exemplary embodiment of FIGS. 15 to 16. Here, the carrier arrangement 8 comprises a second carrier layer 11 and a third carrier layer 12. The second carrier layer 11 is in direct contact with the sacrificial layer 6. Furthermore, the second carrier layer 11 provides a mechanically stable connection between the sacrificial layer 6 and the third carrier layer 12. The radiation-emitting semiconductor chip 1 can be non-destructively detached from the carrier arrangement 8 by laser radiation.

[0162] The radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 25 comprises a semiconductor body 13 configured to emit electromagnetic radiation. The semiconductor body 13 comprises a first semiconductor layer sequence 3 and a second semiconductor layer sequence 4. A first contact layer 5 is arranged on the first semiconductor layer sequence 3, and a second contact layer 14 is arranged on the second semiconductor layer sequence 4. Furthermore, a side surface of the semiconductor body 13 is completely covered with a passivation layer 21.

[0163] In this exemplary embodiment, the radiation-emitting semiconductor chip 1 exclusively comprises components that are formed transparent for the electromagnetic radiation emitted by the semiconductor body 13. Here, the first contact layer 5 and the second contact layer 14 are formed with a transparent conductive material, such as ITO. Furthermore, the passivation layer 21 is formed with silicon dioxide.

[0164] In contrast to the exemplary embodiment of FIG. 25, the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 26 does not comprise a passivation layer 21.

[0165] The radiation-emitting device 32 according to the exemplary embodiment of FIG. 27 comprises a radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 25. Here, the semiconductor chip 1 is applied onto a carrier 33, which comprises at least a first contact element 34. In this exemplary embodiment, the radiation-emitting semiconductor chip 1 is arranged with the second contact layer 14 on the first contact element 34 of the carrier 33 by means of an adhesive 35. In this case, the adhesive 35 is an electrically conductive adhesive 35.

[0166] In contrast to the exemplary embodiment of FIG. 27, the radiation-emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 28 is arranged with the first contact layer 5 on the first contact element 34 of the carrier 33 by means of an adhesive 35. In this case, the adhesive 35 is an electrically insulating adhesive 35.

[0167] The radiation-emitting device 32 according to the exemplary embodiment of FIG. 29 comprises an enveloping body 37 in contrast to the exemplary embodiment of FIG. 28. The enveloping body 37 is, for example, formed transparent for the radiation generated by the radiation-emitting semiconductor chip 1. The enveloping body 37 may be a resin, such as an epoxy, or a silicone, or a mixture of these materials. Furthermore, a first contact layer 5 also covers a top surface of the enveloping body 37, in particular completely.

[0168] According to the exemplary embodiment of FIG. 30, the first contact element 34 comprises a curved shape, in contrast to the exemplary embodiment of FIG. 28.

[0169] In this exemplary embodiment, the first contact element 34 comprises a cavity in which the radiation-emitting semiconductor chip 1 is completely arranged. Further, the radiation-emitting semiconductor chip 1 is completely enclosed by the first contact element 34 in lateral directions.

[0170] The first contact layer 14 and the second contact layer 5 of the radiation-emitting device 32 are arranged on a bottom surface of the semiconductor body 13, in particular of the second semiconductor layer sequence 4, according to the exemplary embodiment of FIG. 31. Here, the first contact layer 5 extends from the bottom surface of the semiconductor body 13 into the semiconductor body 13 to the first semiconductor layer sequence 3. Furthermore, the first contact layer 14 is arranged on a first contact element 34 and the second contact layer 5 is arranged on a second contact element 36. In this exemplary embodiment, the first contact element 34 and the second contact element 36 comprise a reflective, electrically conductive metal.

[0171] In contrast to the exemplary embodiment of FIG. 31, the first contact element 34 and the second contact element according to the exemplary embodiment of FIG. 32 are formed with a TCO.

[0172] The features and embodiments described in connection with the figures may be combined in accordance with further exemplary embodiments, although not all combinations are explicitly described. Furthermore, the exemplary embodiments described in connection with the figures may alternatively or additionally comprise further features according to the description in the general part.

[0173] The invention is not limited to the exemplary embodiments by the description based thereon. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments.