Differential amplifying circuit

Abstract

A differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.

Claims

1. A differential amplifier circuit comprising: a first differential transistor pair which receives a first input signal at a first .Iadd.P-channel .Iaddend.transistor, a second input signal at a second .Iadd.P-channel .Iaddend.transistor and an output signal as a third input signal at third and fourth .Iadd.P-channel .Iaddend.transistors; a second differential transistor pair which receives said first input signal at a fifth .Iadd.N-channel .Iaddend.transistor, said second input signal at a sixth .Iadd.N-channel .Iaddend.transistor and said output signal as a fourth input signal at seventh and eighth .Iadd.N-channel .Iaddend.transistors.Iadd.; and a first amplifier circuit comprised of said first differential transistor pair and said second differential transistor pair is configured to output an averaged voltage of two gradation voltages in an LCD driver.Iaddend..

2. The differential amplifier circuit according to claim 1, further comprising: an adder section which adds first output signals from said first differential transistor pair and second output signals from said second differential transistor pair; and an amplifying unit which amplifies an addition resultant signal from said adder section to produce said output signal and outputs said output signal to said first and second differential transistor pairs.

3. The differential amplifier .Iadd.circuit .Iaddend.according to claim 2, .[.wherein said first differential transistor pair comprises:.]. .Iadd.wherein said .Iaddend.first and second P-channel transistors .[.having.]. .Iadd.have .Iaddend.sources which are commonly connected, gates which respectively receive said first and second input signals, and drains which are commonly connected.[.; and.]..Iadd., wherein said .Iaddend.third and fourth P-channel transistors .[.having.]. .Iadd.have .Iaddend.sources which are commonly connected with said sources of said first and second P-channel transistors, gates which commonly receive said output signal, and drains which are commonly connected.[.; and.]..Iadd., .Iaddend. .[.wherein said second differential transistor pair comprises:.]. .Iadd.wherein said .Iaddend.fifth and sixth N-channel transistors .[.having.]. .Iadd.have .Iaddend.sources which are commonly connected, gates which respectively receive said first and second input signals, and drains which are commonly connected.[.; and.]..Iadd., wherein said .Iaddend.seventh and eighth N-channel transistors .[.having.]. .Iadd.have .Iaddend.sources which are commonly connected with said sources of said fifth and sixth N-channel transistors, gates which commonly receive said output signal, and drains which are commonly connected, wherein said first output signals are respectively output from said drains of said first and second P-channel transistors and said drains of said third and fourth P-channel transistors, and wherein said second output signals are respectively output from said drains of said fifth and sixth N-channel transistors and said drains of said seventh and eighth N-channel transistors.

4. The differential amplifier circuit according to claim 3, wherein said adder section comprises: a first current mirror circuit connected with said first differential transistor pair to receive said first output signals; a second current mirror circuit which is connected with said second differential transistor pair and outputs one of said second output signals to one of transistors of said first current mirror circuit; and a third current mirror circuit which is connected with said second differential transistor pair and outputs .[.the other.]. .Iadd.another .Iaddend.of said second output signals to .[.the other.]. .Iadd.another .Iaddend.of said transistors of said first current mirror circuit.

5. The differential amplifier .Iadd.circuit .Iaddend.according to claim 4, further comprising: first and second constant current sources, wherein said first and second P-channel transistors are connected in parallel to each other and said sources of said first and second P-channel transistors are connected with said first constant current source, and said drains of said first and second P-channel transistors are commonly connected with one of transistors of said first current mirror circuit to output one of said first output signals to said one .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit, said third and fourth P-channel transistors are connected in parallel to each other and said sources of said third and fourth .Iadd.P-channel .Iaddend.transistors are connected with said first constant current source, and said drains of said third and fourth .Iadd.P-channel .Iaddend.transistors are commonly connected with the .[.other.]. .Iadd.another .Iaddend.of .Iadd.said .Iaddend.transistors of said first current mirror circuit to output the other of said first output signals to said other .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit, said fifth and sixth N-channel transistors are connected in parallel to each other and said .[.source.]. .Iadd.sources .Iaddend.of said fifth and sixth N-channel transistors are .Iadd.commonly .Iaddend.connected .[.with said second constant current source.]., and said drains of said fifth and sixth N-channel transistors are commonly connected with one of transistors of said second current mirror circuit, and said seventh and eighth N-channel transistors are connected in parallel to each other and said sources of said seventh and eighth N-channel transistors are .Iadd.commonly .Iaddend.connected with said .[.second constant current.]. source .Iadd.of said fifth and sixth N-channel transistors.Iaddend., and said drains of said seventh and eighth N-channel transistors are commonly connected with one of transistors of said third current mirror circuit, wherein .Iadd.the .Iaddend.one of said second output signals is supplied from .[.the other transistor.]. .Iadd.another of said transistors .Iaddend.of said second current mirror circuit to said .[.other transistor.]. .Iadd.another of said transistors .Iaddend.of said first current mirror circuit, and the other of said second output signals is supplied from .[.the other transistor.]. .Iadd.another of said transistors .Iaddend.of said third current mirror circuit to said one .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit.

6. The differential amplifier circuit according to claim 2, wherein said adder section comprises: a fourth current mirror circuit which receives said second output signals; a fifth current mirror circuit which receives said first output signals; and a floating constant current source section connected between said fourth and fifth current mirror circuits, wherein said amplifying unit is driven based on a third output signal from said fourth current mirror circuit and a fourth output signal from said fifth current mirror circuit to output said addition resultant signal.

7. The differential amplifier circuit according to claim 6, wherein each of said fourth and fifth current mirror circuits is of a cascode connection type.

8. The differential amplifier circuit according to claim 6, wherein said floating constant current source section comprises: a first current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between one side of said fourth current mirror circuit and one side of said fifth current mirror circuit; and a second current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between .[.the other.]. .Iadd.another .Iaddend.side of said fourth current mirror circuit and .[.the other.]. .Iadd.another .Iaddend.side of said fifth current mirror circuit.

9. The differential amplifier circuit according to claim 6, wherein said amplifying unit comprises: a P-channel MOS transistor and an N-channel MOS transistor which are connected in series, said P-channel MOS transistor and said N-channel MOS transistor of .[.said.]. .Iadd.an .Iaddend.output stage circuit receive as said addition resultant signal, said third output signal from said fourth current mirror circuit and said fourth output signal from said fifth current mirror circuit respectively, and said output signal is outputted from a node between said P-channel MOS transistor and said N-channel MOS transistor of said output stage circuit.

10. The differential amplifier circuit according to claim 6, wherein said floating constant current source section comprises: a first current source section which comprises a P-channel MOS transistor and an N-channel MOS transistor which are connected in parallel and is connected between one side of said fourth current mirror circuit and one side of said fifth current mirror circuit.

11. The differential amplifier circuit according to claim 10, wherein said amplifying unit comprises: a P-channel MOS transistor and an N-channel MOS transistor which are connected in series, said P-channel MOS transistor and said N-channel MOS transistor of .[.said.]. .Iadd.an .Iaddend.output stage circuit receive as said addition resultant signal, said third output signal from said fourth current mirror circuit and said fourth output signal from said fifth current mirror circuit respectively, and said output signal is outputted from a node between said P-channel MOS transistor and said N-channel MOS transistor of said output stage circuit.

12. The differential amplifier circuit according to claim 5, wherein a mobility of each of said first to fourth P-channel .[.MOS.]. transistors is .sub.P, and a mobility of each of said fifth to eighth N-channel .[.MOS.]. transistors is .sub.N, a ratio of a gate width W of each of said first to fourth P-channel .[.MOS.]. transistors to a gate length L thereof is: ${\frac{W}{L}.Math.}_P$ a ratio of a gate width W of each of said fifth to eighth N-channel .[.MOS.]. transistors to a gate length L thereof is: ${\frac{W}{L}.Math.}_N$ when a gate oxide film capacitance per unit area of each of said first to fourth P-channel .[.MOS.]. transistors and said fifth to eighth N-channel .[.MOS.]. transistors is C.sub.0, .sub.P and .sub.N indicated by the following equations satisfy a relation of .sub.P=.sub.N: ${{{}_P=\frac{W}{L}.Math.}_P{}_P{C}_0{}_N=\frac{W}{L}.Math.}_P{}_N{C}_0.$

13. A differential amplifier circuit comprising: a first differential transistor pair which receives first and second input signals and an output signal as a third input signal; a second differential transistor pair which receives said first and second input signals and said output signal as a fourth input signal; an adder section which adds first output signals from said first differential transistor pair and second output signals from said second differential transistor pair; and an amplifying unit which amplifies an addition resultant signal from said adder section to output to said first and second differential transistor pairs, wherein said first differential transistor pair comprises: first and second P-channel transistors having sources which are commonly connected, gates which respectively receive said first and second input signals, and drains which are commonly connected; and third and fourth P-channel transistors having sources which are commonly connected with said sources of said first and second P-channel transistors, gates which commonly receive said output signal, and drains which are commonly connected, and said second differential transistor pair comprises: fifth and sixth N-channel transistors having .[.source.]. .Iadd.sources .Iaddend.which are commonly connected, gates which respectively receive said first and second input signals, and drains which are commonly connected; and seventh and eighth N-channel transistors having sources which are commonly connected with said sources of said fifth and sixth N-channel transistors, gates which commonly receive said output signal, and drains which are commonly connected, said first output signals are respectively outputted from said drains of said first and second P-channel transistors and said drains of said third and fourth P-channel transistors, and said second output signals are respectively outputted from said drains of said fifth and sixth N-channel transistors and said drains of said seventh and eighth N-channel transistors, said adder section comprises: a fourth current mirror circuit which receives said second output signals; a fifth current mirror circuit which receives said first output signals; and a floating constant current source section connected between said fourth and fifth current mirror circuits, and said amplifying unit is driven based on a third output signal from said fourth current mirror circuit and a fourth output signal from said fifth current mirror circuit to output said addition resultant signal.Iadd.; and a first amplifier circuit comprised of said first differential transistor pair and said second differential transistor pair is configured to output an averaged voltage of two gradation voltages in an LCD driver.Iaddend..

14. The differential amplifier circuit according to claim 13, wherein said adder section .Iadd.further .Iaddend.comprises: a first current mirror circuit connected with said first differential transistor pair to receive said first output signals; a second current mirror circuit which is connected with said second differential transistor pair and outputs one of said second output signals to one of transistors of said first current mirror circuit; and a third current mirror circuit which is connected with said second differential transistor pair and outputs .[.the other.]. .Iadd.another .Iaddend.of said second output signals to .[.the other.]. .Iadd.another .Iaddend.of said transistors of said first current mirror circuit.

15. The differential amplifier .Iadd.circuit .Iaddend.according to claim 14, further comprising: first and second constant current sources, wherein said first and second P-channel transistors are connected in parallel to each other and said sources of said first and second P-channel transistors are connected with said first constant current source, and said drains of said first and second P-channel transistors are commonly connected with one of transistors of said first current mirror circuit to output one of said first output signals to said one .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit, said third and fourth P-channel transistors are connected in parallel to each other and said sources of said third and fourth .Iadd.P-channel .Iaddend.transistors are connected with said first constant current source, and said drains of said third and fourth .Iadd.P-channel .Iaddend.transistors are commonly connected with the .[.other.]. .Iadd.another .Iaddend.of .Iadd.said .Iaddend.transistors of said first current mirror circuit to output the other of said first output signals to said other .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit, said fifth and sixth N-channel transistors are connected in parallel to each other and said .[.source.]. .Iadd.sources .Iaddend.of said fifth and sixth N-channel transistors are .Iadd.commonly .Iaddend.connected .[.with said second constant current source.]., and said drains of said fifth and sixth N-channel transistors are commonly connected with one of transistors of said second current mirror circuit, and said seventh and eighth N-channel transistors are connected in parallel to each other and said sources of said seventh and eighth N-channel transistors are .Iadd.commonly .Iaddend.connected with said .[.second constant current.]. source .Iadd.of said fifth and sixth N-channel transistors.Iaddend., and said drains of said seventh and eighth N-channel transistors are commonly connected with one of transistors of said third current mirror circuit, wherein one of said second output signals is supplied from .[.the other transistor.]. .Iadd.another of said transistors .Iaddend.of said second current mirror circuit to said other .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit, and the other of said second output signals is supplied from .[.the other transistor.]. .Iadd.another of said transistors .Iaddend.of said third current mirror circuit to said one .[.transistor.]. .Iadd.of said transistors .Iaddend.of said first current mirror circuit.

16. A differential amplifier circuit comprising: a first differential circuit of a first type which is responsive to first and second input signals and an output signal to convey a first node and a second .[.nodes.]. .Iadd.node.Iaddend., wherein said first and second input signals are received by first and second transistors, respectively, and said output signal is received by third and fourth transistors; a second differential circuit of a second type complementary to said first type which is responsive to said first and second input signals and said output signal to convey a third node and a fourth .[.nodes.]. .Iadd.node.Iaddend., wherein said first and second input signals are received by fifth and sixth transistors, respectively, and said output signal is received by seventh and eighth transistors.Iadd.; and wherein a first amplifier circuit comprised of said first differential circuit and said second differential circuit is configured to output an averaged voltage of two gradation voltages in an LCD driver.Iaddend..

17. The differential amplifier circuit according to claim 16, further comprising: a first current mirror circuit having a first terminal coupled to said second node; a second current mirror circuit having a first terminal coupled to said third node and having a second terminal coupled to said second node; a third current mirror circuit having a first terminal coupled to said fourth node and having a second terminal coupled to said first node; and an amplifier coupled to said second node to output said output signal.

.Iadd.18. The differential amplifier circuit according to claim 1, further comprising: a plurality of amplifier circuits each comprised of a same structure as that of the first amplifier circuit..Iaddend.

.Iadd.19. The differential amplifier circuit according to claim 13, further comprising: a plurality of amplifier circuits each comprised of a same structure as that of the first amplifier circuit..Iaddend.

.Iadd.20. The differential amplifier circuit according to claim 16, further comprising: a plurality of amplifier circuits each comprised of a same structure as that of the first amplifier circuit..Iaddend.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic block diagram showing the circuit arrangement of a conventional LCD source driver;

(2) FIG. 2 is a diagram showing an example of a specific circuit of a conventional amplifier employed in the LCD source driver;

(3) FIG. 3 is a circuit diagram showing a two-input amplifier according to a first embodiment of the present invention;

(4) FIG. 4 is a diagram showing an example of a specific circuit of a differential stage employed in the 2-input amplifier of FIG. 3;

(5) FIG. 5 is a diagram showing another example of a specific circuit of the differential stage employed in the 2-input amplifier of FIG. 3;

(6) FIG. 6 is a diagram showing an input/output characteristic of the 2-input amplifier shown in FIG. 4;

(7) FIG. 7 is a diagram showing an input/output characteristic of the 2-input amplifier shown in FIG. 5;

(8) FIG. 8 is a diagram showing an input/output characteristic of the 2-input amplifier shown in FIG. 3;

(9) FIG. 9 is a circuit diagram showing a two-input amplifier according to a second embodiment of the present invention;

(10) FIG. 10 is a circuit diagram showing a specific circuit of a current adder circuit employed in the 2-input amplifier of FIG. 9; and

(11) FIG. 11 is a circuit diagram showing another specific circuit of the current adder circuit employed in the 2-input amplifier of FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(12) Hereinafter, a differential amplifier of the present invention will be described in detail with reference to the attached drawings.

First Embodiment

(13) FIG. 3 is a diagram showing a circuit arrangement of an equivalent circuit of an operational amplifier having two inputs. FIG. 4 is a circuit diagram showing a specific circuit arrangement of a PMOS (P-channel MOS) transistor differential amplifier contained in the equivalent circuit shown in FIG. 3. FIG. 5 is a circuit diagram showing another specific circuit arrangement of an NMOS (N-channel MOS) transistor differential amplifier contained in the equivalent circuit shown in FIG. 3.

(14) The operational amplifier shown in FIG. 3 is constituted by combining the PMOS transistor differential amplifier shown in FIG. 4 and the NMOS transistor differential amplifier shown in FIG. 5. In order to easily understand the present invention, the circuit arrangement and operation of each of the PMOS transistor differential amplifier and the NMOS transistor differential amplifier will be described. Further, an equivalent circuit arranged by combining the NMOS transistor differential amplifier and the PMOS transistor differential amplifier will be described.

(15) Referring to FIG. 4, the PMOS transistor differential amplifier is composed of a source type constant current source CC2, PMOS transistors M1 to M4 and NMOS transistors MS and M6, and an amplifying unit A1. The PMOS transistor M1 has the gate as a first input terminal, and the PMOS transistor M3 has the gate as a second input terminal. The PMOS transistor M2 has the gate as an inversion input terminal, and the PMOS transistor M4 has the gate as the inversion input terminal. The NMOS transistor M5 and the NMOS transistor M6 constitute a current mirror circuit functioning as an active load, and an input of the amplifying unit A1 is connected to an output of the active load. Furthermore, the gates of the PMOS transistor M2 and PMOS transistor M4 are connected with the output of the amplifying unit A1 to constitute a voltage follower connection.

(16) More specifically, one terminal of the constant current source CC2 is connected to a power supply voltage V.sub.DD, and this constant current source CC2 supplies a current IR. The other terminal of the constant current source CC2 is connected to the sources of the PMOS transistor M3 and M1. A first input voltage V.sub.1 and a second input voltage V.sub.2 are applied to the gate of the PMOS transistor M3, and the gate of the PMOS transistor M1, respectively. The drain of the PMOS transistor M3 and the drain of the PMOS transistor M1 are connected to the drain of the NMOS transistor M5. The NMOS transistor M5 constitutes a current mirror in combination with the NMOS transistor M6. The characteristics of the NMOS transistor M5 are supposed to be identical to those of the NMOS transistor M6. The source of the NMOS transistor M5 and the source of the NMOS transistor M6 are connected to a ground voltage. The gate of the NMOS transistor M5 and the gate of the NMOS transistor M6 are connected to each other, and are further connected to the drain of the NMOS transistor M5. The drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M2 and the drain of the PMOS transistor M4. The source of the PMOS transistor M2 and the source of the PMOS transistor M4 are connected to the constant current source CC2. The gate of the PMOS transistor M2 and the gate of the PMOS transistor M4 are connected to the output of the amplifying unit A1 as an output V.sub.o.

(17) Characteristics of the PMOS transistor M2 and the PMOS transistor M4 are supposed to be substantially same to those of the PMOS transistor M3 and the PMOS transistor M1. The output voltage V.sub.o of the PMOS transistor differential amplifier having such a circuit arrangement is in a range of the voltage V.sub.1 and the voltage (V.sub.1+V.sub.2). When the constant current source CC2 flows the current I.sub.R, the PMOS transistor M1 and the PMOS transistor M3 flow a current I.sub.2P and a current I.sub.3P corresponding to the first input voltage V.sub.1 and the second input voltage V.sub.2, respectively. A summation of the current I.sub.2P and the current I.sub.3P is equivalent to a current I.sub.R/2 and flows through the NMOS transistor M5. Since the NMOS transistor M5 and the NMOS transistor M6 have the same characteristics and constitute the current mirror circuit, the current I.sub.R/2 flows through the NMOS transistor M6. The constant current source CC2 supplies the current I.sub.R/2 to the source of the PMOS transistor M2 and the source of the PMOS transistor M4. If the PMOS transistor M2 and the PMOS transistor M4 have the same characteristics, a current I.sub.1P flows through the PMOS transistor M2 and the PMOS transistor M4. Also, if the summation between the current flowing through the PMOS transistor M2 and the current flowing through the PMOS transistor M4 is coincident with the summation between the current flowing through the PMOS transistor M3 and the current flowing through the PMOS transistor M1, the current I1 is coincident with an averaged current between the current I2 and the current I3. If the characteristics of the PMOS transistor M2 and the PMOS transistor M4 are coincident with the characteristics of the PMOS transistor M3 and the PMOS transistor M1, the voltage at the gates of the PMOS transistor M2 and M4 is substantially equal to the averaged voltage between the first input voltage V.sub.1 and the second voltage V.sub.2, namely, the in-phase voltage ((V.sub.1+V.sub.2)/2).

(18) Assuming now that a voltage which is applied to one non-inversion input terminal is equal to V.sub.1 and another voltage which is applied to the other non-inversion input terminal is equal to V.sub.2, the in-phase voltage is correctly analyzed. In this case, a voltage V.sub.0 which is finally outputted can be expressed as follows. That is, when

(19) $\begin{array}{cc}=\frac{W}{L}{C}_o,& \left(1\right)\end{array}$
where is a mobility in an MOS transistor, W is a gate width of the MOS transistor, L is a gate length of the MOS transistor is L, CO is a gate oxide film capacitance, the finally outputted voltage V.sub.0 is expressed by the following equation (2):

(20) $\begin{array}{cc}{V}_o=\frac{V_1+V_2}{2}+\frac{-2\sqrt{\frac{2I_1}{}}+\sqrt{{\left(2\sqrt{\frac{2I_1}{}}\right)}^2-{\left(V_1-V_2\right)}^2}}{2}& \left(2\right)\end{array}$
where I1 is the current flowing through each of the PMOS transistor M2 and the PMOS transistor M4.

(21) Referring to FIG. 5, similarly to the PMOS transistor differential amplifier shown in FIG. 4, the NMOS transistor differential amplifier is provided with a constant current source CC1 for supplying a current I.sub.R, NMOS transistors M7 to M10, and PMOS transistors M11 and M12.

(22) One terminal of the constant current source CC1 is connected to the ground voltage, and the constant current source CC1 supplies the current I.sub.R to the ground terminal. The other terminal of the constant current source CC1 is connected to the sources of the NMOS transistors M9 to M10. A first input voltage V.sub.1 and a second input voltage V.sub.2 are applied to the gate of the NMOS transistor M9 and the gate of the NMOS transistor M7, respectively. The drain of the NMOS transistor M9 and the drain of the NMOS transistor M7 are connected to the drain of the PMOS transistor M11. The PMOS transistor M11 constitutes a current mirror circuit together with the PMOS transistor M12. The characteristics of the PMOS transistor M11 are supposed to be identical to those of the PMOS transistor M12. The source of the PMOS transistor M11 and the source of the PMOS transistor M12 are connected to the power supply voltage V.sub.DD. The gate of the PMOS transistor M11 and the gate of the PMOS transistor M12 are connected to each other, and are further connected to the drain of the PMOS transistor M11. The drain of the PMOS transistor M12 is connected to the drain of the NMOS transistor M8 and the drain of the NMOS transistor M10. The source of the NMOS transistor M8 and the source of the NMOS transistor M10 are connected to the constant current source CC1. An input of the amplifying unit A1 is connected with the drain of the PMOS transistor M12, and an output of the amplifying unit A1 is connected to the gate of the NMOS transistor M8 and the gate of the NMOS transistor M10 which are held to a same output voltage V.sub.o.

(23) The characteristics of the NMOS transistor M7 to M10 are supposed to be substantially identical to each other, and the characteristics of the PMOS transistor M11 are supposed to be substantially identical to those of the PMOS transistor M12. In this case, the output voltage V.sub.o of the NMOS transistor differential amplifier having such a circuit arrangement is substantially equal to an averaged voltage between the first input voltage V.sub.1 and the second input voltage V.sub.2, namely an in-phase voltage ((V.sub.1+V.sub.2)/2). The NMOS transistor M9 and the NMOS transistor M7 flow a current I.sub.2N and a current I.sub.3N corresponding to the first input voltage V.sub.1 and the second input voltage V.sub.2, respectively. A current I.sub.R/2 equal to a summation of the current I.sub.2N and the current I.sub.3N flows through the PMOS transistor M11. Since the PMOS transistor M11 and the PMOS transistor M12 constitute the current mirror circuit, the current I.sub.R/2 equal to that of the current flowing through the PMOS transistor M11 flows through the NMOS transistor M8 and the NMOS transistor M10. Since the NMOS transistor M8 and the NMOS transistor M10 have the same characteristics, a currents I.sub.1N flows through the NMOS transistor M8 and the NMOS transistor M10. Since a summation between the current flowing through the NMOS transistor M8 and the current flowing through the NMOS transistor M10 is coincident with a summation between the current flowing through the NMOS transistor M9 and the current flowing through the NMOS transistor M7, the current I.sub.1N is coincident with an averaged current between the current I.sub.2N and the current I.sub.3N. Further, since the characteristics of the NMOS transistor M8 and the NMOS transistor M10 are coincident with the characteristics of the NMOS transistor M9 and the NMOS transistor M7, the voltage at the gates of the NMOS transistor M8 and M10 is substantially equal to the averaged voltage of the first input voltage V.sub.1 and the second voltage V.sub.2, namely, the in-phase voltage ((V.sub.1+V.sub.2)/2).

(24) In other words, assuming now that a voltage which is applied to one non-inversion input terminal is equal to V.sub.1 and another voltage which is applied to the other non-inversion input terminal is equal to V.sub.2, a voltage V.sub.0 which is finally outputted from the NMOS transistor differential amplifier shown in FIG. 5 is expressed by the following equation (3):

(25) $\begin{array}{cc}{V}_o=\frac{V_1+V_2}{2}+\frac{2\sqrt{\frac{2I_1}{}}-\sqrt{{\left(2\sqrt{\frac{2I_1}{}}\right)}^2-{\left(V_1-V_2\right)}^2}}{2}& \left(3\right)\end{array}$
where is expressed by the following equation (1), like the PMOS transistor differential amplifier:

(26) $\begin{array}{cc}=\frac{W}{L}{C}_o& \left(1\right)\end{array}$
where I1 is a current which flows through each of the NMOS transistor M8 and the NMOS transistor M10.

(27) FIG. 6 is a diagram graphically showing an actual input/output characteristic of the PMOS transistor differential amplifier. Referring to FIG. 6, the output voltage V.sub.o of the PMOS transistor differential amplifier with the two inputs is nearly equal to:
V.sub.o=(V.sub.1+V.sub.2)/2.
When a difference between the two inputted voltages V.sub.1 and V.sub.2 is relatively small. However, when a difference between the two inputted voltages V.sub.1 and V2 becomes large, an error of the output voltage V.sub.o from (V.sub.1+V.sub.2)/2 becomes large.

(28) FIG. 7 is a diagram graphically showing an actual input/output characteristic of the NMOS transistor differential amplifier. Referring to FIG. 7, the output voltage V.sub.o of the NMOS transistor differential amplifier with the two inputs is nearly equal to:
V.sub.o=(V.sub.1+V.sub.2)/2.
When a difference between the tow inputted voltages V.sub.1 and V.sub.2 is relatively small. However, when a difference between the two inputted voltages V.sub.1 and V.sub.2 becomes large, an error of the output voltage V.sub.o from (V.sub.1+V.sub.2)/2 becomes large.

(29) Furthermore, when the input/output characteristic of FIG. 6 is compared with that of FIG. 7, it could be seen that polarities of errors are opposite to each other, when the difference between input voltages V.sub.1 and V.sub.2 becomes large in the PMOS transistor differential amplifier and the NMOS transistor differential amplifier.

(30) Referring now to FIG. 3, an input stage constitutes a differential amplifier having two non-inversion inputs. The differential amplifying circuit shown in FIG. 3 is composed of a PMOS transistor differential stage having a circuit arrangement similar to that of the above-described PMOS transistor differential amplifier, and an N differential stage having a circuit arrangement similar to that of the above-explained NMOS transistor differential amplifier, between which the amplifying unit A1 is shared.

(31) The PMOS transistor differential stage is formed from the constant current source CC1, the four PMOS transistors M1 to M4 and the two NMOS transistors M5 and M6. The sources of the four PMOS transistors M1 to M4 are commonly connected to each other, and the constant current source CC1 is inserted between the power supply voltage V.sub.DD and the drains of the four PMOS transistors. The drains of the PMOS transistors M1 and M3 are commonly connected to each other, and the drains of the PMOS transistors M2 and M4 are commonly connected to each other. The NMOS transistors M5 and M6 constitute the current mirror circuit and functions as the active load.

(32) The NMOS transistor differential stage is formed from the constant current source CC2, the four NMOS transistors M7 to M10 and the first and second current mirror circuits CM1 and CM2. Each of the first and second current mirror circuits CM1 and CM2 is formed from the PMOS transistors M11 and M12. The output of the PMOS transistor M11 in the first current mirror circuit is connected with the NMOS transistors M7 and M9, and the output of the PMOS transistor M12 is connected with drain of the NMOS transistor M6. Also, the output of the PMOS transistor M11 in the second current mirror circuit is connected with the NMOS transistors M8 and M10, and the output of the PMOS transistor M12 is connected with drain of the NMOS transistor M5. The sources of the four NMOS transistors M7 to M10 are commonly connected to each other, and the constant current source CC2 is inserted between the ground voltage and the drains of the four NMOS transistors. The sources of the NMOS transistors M7 and M9 are commonly connected to each other, and the sources of the NMOS transistors M8 and M10 are commonly connected to each other. In the N differential stage, the current mirror circuit CM1 and the current mirror circuit CM2 are provided in place of the current mirror circuit M11 and M12. The current mirror circuit CM1 supplies the current I.sub.R/2 from one output to the NMOS transistors M7 and M9, and the other output is connected to the drain of the NMOS transistor M6. Also, the current mirror circuit CM2 supplies the current I.sub.R/2 from one output to the NMOS transistors M8 and M10, and the other output is connected to the drain of the NMOS transistor M5.

(33) Furthermore, the output of the amplifying unit A1 is connected with the gate of the NMOS transistor M8 and the gate of the NMOS transistor M10 commonly and with the gate of the PMOS transistor M2 and the gate of the PMOS transistor M4 commonly, so as to constitute a voltage follower connection. The gate of the NMOS transistor M9 and the gate of the PMOS transistor M3 as a first input terminal are commonly connected with the first input voltage V.sub.1, and the gate of the NMOS transistor M7 and the gate of the PMOS transistor M1 as a second input terminal are commonly connected with the second input voltage V.sub.2.

(34) The gate of the NMOS transistor M5 is connected to the gate of the NMOS transistor M6, and the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5. The sources of the NMOS transistors M5 and M6 are connected to the ground terminal GND. The drain of the NMOS transistor M5 is connected to the drains of the PMOS transistor M1 and M3 and the current mirror circuit CM2. The drain of the NMOS transistor M6 is connected to the drains of the NMOS transistor M2 and M4, the input of the amplifying unit A1 and the current mirror circuit CM1.

(35) Assuming now that the voltage at the common source of the PMOS transistor differential stage is V.sub.MP, and the voltage at the common source of the NMOS transistor differential stage is V.sub.MN, a calculation is carried out. With reference to FIG. 3, assuming now that the current flowing through each of the PMOS transistor M2 and the PMOS transistor M4 is I.sub.1P, the current flowing through the PMOS transistor M3 is I.sub.2P, and the current flowing through the PMOS transistor M1 is I.sub.3P, the current 4I.sub.1P flows through the PMOS transistor differential stage and is expressed by the following equation (4):
4I.sub.1P=2I.sub.P+I.sub.2P+I.sub.3P (4)
Also, assuming now that the current flowing through each of the NMOS transistor M8 and the NMOS transistor M10 is I.sub.1N, the current flowing through the NMOS transistor M9 is I.sub.2N, and the current flowing through the NMOS transistor M7 is I.sub.3N, the current 4I.sub.1N flows through the NMOS transistor differential stage and is expressed by the following equation (5):
4I.sub.1N=2I.sub.1N+I.sub.2N+I.sub.3N (5)
In this case, since the currents flowing through the active load are equal to each other, the following equation (6) is given:
I.sub.2P+I.sub.3P+2I.sub.1N=I2N+I.sub.3N+2I.sub.1P (6).
At this time, assuming that a mobility in a PMOS transistor is .sub.P, a mobility in an NMOS transistor is .sub.N, and a ratio of a gate width W of the PMOS transistor to a gate length L thereof is:

(36) ${\frac{W}{L}.Math.}_P$
and a ratio of the gate width W of the NMOS transistor to the gate length L thereof is

(37) ${\frac{W}{L}.Math.}_N$
the following calculation is carried out by employing .sub.P and .sub.N which are expressed by the following equations (7) and (8) when a gate oxide film capacitance per a unit area of each of the PMOS and NMOS transistors is equal to CO;

(38) 0$\begin{array}{cc}{{}_P=\frac{W}{L}.Math.}_P{}_P{C}_o,& \left(7\right)\\ {{}_N=\frac{W}{L}.Math.}_N{}_N{C}_o.& \left(8\right)\end{array}$
Based upon a relation between a gate-to-drain voltage and a drain current, it is assumed that a common source-to-node voltage in the PMOS transistor differential stage is V.sub.MP, and a common source-to-node voltage in the NMOS transistor differential stage is V.sub.MN. Also, assuming now that a threshold voltage of the PMOS transistor is V.sub.TP and a threshold voltage of the NMOS transistor is V.sub.TN, currents which flow through the respective transistors are expressed as follows:

(39) $\begin{array}{cc}{I}_{1P}=\frac{{}_P}{2}{\left(V_{\mathrm{MP}}-V_o-V_{\mathrm{TP}}\right)}^2,& \left(9\right)\\ I_{2P}=\frac{{}_P}{2}{\left(V_{\mathrm{MP}}-V_1-V_{\mathrm{TP}}\right)}^2,& \left(10\right)\\ I_{3P}=\frac{{}_P}{2}{\left(V_{\mathrm{MP}}-V_2-V_{\mathrm{TP}}\right)}^2,& \left(11\right)\\ I_{1N}=\frac{{}_N}{2}{\left(V_o-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2,& \left(12\right)\\ I_{2N}=\frac{{}_N}{2}{\left(V_1-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2,& \left(13\right)\\ I_{3N}=\frac{{}_N}{2}{\left(V_2-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2.& \left(14\right)\end{array}$
If the above-described equations (9) to (14) are substituted for the above-explained equation (6), the following equation (15) is given:

(40) $\begin{array}{cc}\frac{{}_P}{2}\left\{{\left(V_{\mathrm{MP}}-V_1-V_{\mathrm{TP}}\right)}^2+{\left(V_{\mathrm{MP}}-V_2-V_{\mathrm{TP}}\right)}^2\right\}+{{}_N\left(V_o-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2=\frac{{}_N}{2}\left\{{\left(V_1-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2+{\left(V_2-V_{\mathrm{MN}}-V_{\mathrm{TN}}\right)}^2\right\}+{{}_p\left(V_{\mathrm{MP}}-V_o-V_{\mathrm{TP}}\right)}^2.& \left(15\right)\end{array}$
In this case, based upon a relation between the gate-to-source voltage V.sub.GS and the drain currents (I.sub.1P, I.sub.1N), the following equation can be satisfied in the PMOS channel differential stage:

(41) $V_{\mathrm{MP}}-V_{\mathrm{TP}}=\sqrt{\frac{2I_{1P}}{{}_P}}+V_o$
In other words, the following equal (16) can be satisfied:

(42) $\begin{array}{cc}{V}_{\mathrm{GS}}=V_{\mathrm{MP}}-V_o=\sqrt{\frac{2I_{1P}}{{}_P}}+V_{\mathrm{TP}}.& \left(16\right)\end{array}$
Similarly, the following equation can be satisfied in the NMOS channel differential stage:

(43) $V_{\mathrm{GS}}=V_o-V_{\mathrm{MN}}=\sqrt{\frac{2I_{1N}}{{}_N}}+V_{\mathrm{TN}}.$
In other words, the following equation (17) can be satisfied:

(44) $\begin{array}{cc}-V_{\mathrm{MN}}-V_{\mathrm{TN}}=\sqrt{\frac{2I_{1N}}{{}_N}}-V_o.& \left(17\right)\end{array}$
If these equations (16) and (17) are substituted for the above-mentioned equation (15), the following equation (18) is obtained:

(45) $\begin{array}{cc}{{}_P\left(\sqrt{\frac{2I_{1P}}{{}_P}}+V_o-V_1\right)}^2+{{}_P\left(\sqrt{\frac{2I_{1P}}{{}_P}}+V_o-V_2\right)}^2+2{}_N\frac{2I_{1N}}{{}_N}={{}_N\left(V_1+\sqrt{\frac{2I_{1N}}{{}_{N_o}}}-V_o\right)}^2+{{}_N\left(V_2+\sqrt{\frac{2I_{1P}}{{}_P}}-V_o\right)}^2+2{}_P\frac{2I_{1P}}{{}_P}.& \left(18\right)\end{array}$
When this equation (18) is expanded, the following equation (19) is obtained:
2{square root over (2.sub.PI.sub.1P)}(2V.sub.oV.sub.1V.sub.2)+.sub.P{(V.sub.oV.sub.1).sup.2+(V.sub.oV.sub.2).sup.2}
=2{square root over (2.sub.NI.sub.1N)}(V.sub.1+V.sub.22V.sub.o)+.sub.N{(V.sub.1V.sub.o).sup.2+(V.sub.2V.sub.o).sup.2} (19).
In this equation (19), if .sub.P=.sub.N, namely,

(46) $\frac{W}{L}{{.Math.}_P{}_P{C}_o=\frac{W}{L}.Math.}_N{}_N{C}_o$$\frac{W}{L}{{.Math.}_P{}_P=\frac{W}{L}.Math.}_N{}_N$
then the following equation can be satisfied under the condition that .sub.P=.sub.N=:

(47) $2\sqrt{2}\left(2V_o-V_1-V_2\right)\left(\sqrt{I_{1P}}+\sqrt{I_{\mathrm{IN}}}\right)+{\left\{{\left(V_o-V_1\right)}^2+{\left(V_{o-}{V}_2\right)}^{2\}-\left\{\right(}{V}_1-V_o\right)}^2+{\left(V_2-V_o\right)}^2\}=0.$
When this equation is solved, the following equation is given as follows:
2V.sub.oV.sub.1V.sub.2=0

(48) In other words, V.sub.0 is expressed by the following equation (20):

(49) 0$\begin{array}{cc}{V}_o=\frac{V_1+V_2}{2}.& \left(20\right)\end{array}$
As a consequence, in accordance with the differential amplifier described in this first embodiment, the desirable half voltage of the two input voltages can be outputted irrespective of the current flowing through the PMOS transistor differential stage and the current through the NMOS transistor differential stage.

(50) FIG. 8 is a diagram graphically showing the input/output characteristic of the differential amplifier shown in FIG. 3. With reference to FIG. 8, it could be readily understood that even when a difference between the first input voltage V.sub.1 and the second input voltage V.sub.2 becomes large, the voltage of (V.sub.1+V.sub.2)/2 is outputted as the output voltage V.sub.0 of the differential amplifier with the two inputs of this first embodiment.

(51) Also, if .sub.P is not equal to .sub.N, the following equation can be satisfied:

(52) $2\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)\left(2V_o-V_1-V_2\right)+{}_P\left\{2V_o^2-2V_o\left(V_1+V_2\right)+V_1^2+V_2^2\right\}-{}_N\left\{2V_o^2-2V_o\left(V_1+V_2\right)+V_1^2+V_2^2\right\}=0$
When a left side of this equation is expanded, an equation (21) is obtained:

(53) $\begin{array}{cc}2\left({}_P-{}_N\right)V_o^2-2V_o\left\{\left({}_P-{}_N\right)\left(V_1+V_2\right)-2\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)\right\}+\left({}_P-{}_N\right)\left(V_1^2+V_2^2\right)-2\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)\left(V_1+V_2\right)=0.& \left(21\right)\end{array}$
When this equation (21) is solved with respect to V.sub.o, the following equation (22) is obtained as follows:

(54) $\begin{array}{cc}{V}_o=\frac{V_1+V_2}{2}-\frac{\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)}{\left({}_P-{}_N\right)}\frac{\sqrt{16{\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{\mathrm{IN}}}\right)}^2-4{\left({}_P-{}_N\right)}^2{\left(V_1-V_2\right)}^2}}{4\left({}_P-{}_N\right)}.& \left(22\right)\end{array}$
In this equation, based upon the condition of V.sub.1=V.sub.2=V.sub.0 under V.sub.1=V.sub.2, symbol plus or minus becomes plus (+) in the above-explained equation (22). As a consequence, this equation (22) is transformed into the following equation (23):

(55) $\begin{array}{cc}{V}_o=\frac{V_1+V_2}{2}-\frac{\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)}{\left({}_P-{}_N\right)}+\frac{\sqrt{16{\left(\sqrt{2{}_P{I}_{1P}}-\sqrt{2{}_N{I}_{1N}}\right)}^2-4{\left({}_P-{}_N\right)}^2{\left(V_1-V_2\right)}^2}}{4\left({}_P-{}_N\right)}.& \left(23\right)\end{array}$
This equation (23) expresses an equation when the NMOS transistor differential stage and the PMOS transistor differential stage are not balanced, and the second term and the third term constitute an error from a desirable value.

(56) As indicated in the above-described equation (23), by using the differential amplifying circuit of this first embodiment, the precision of the averaged voltage of the 2-input amplifier can be considerably improved even when .sub.P is not equal to .sub.N.

Second Embodiment

(57) FIG. 9 is a diagram showing the circuit arrangement of a differential amplifier according to the second embodiment of the present invention. Referring now to FIG. 9, the differential amplifier of the second embodiment is formed from the 2-input PMOS transistor differential stage, the 2-input NMOS transistor differential stage, a current adder circuit and an amplifying unit A2. The 2-input PMOS transistor differential stage is composed of the constant current source CC2 and the PMOS transistors M1 to M4, like the PMOS transistor differential stage in the first embodiment. Also, the 2-input NMOS transistor differential stage is composed of the constant current source CC1 and the NMOS transistors M7 to M10, like the NMOS transistor differential stage in the first embodiment. The current adder circuit adds the outputs of the NMOS transistor differential stage and the outputs of the PMOS transistor differential stage, and outputs the addition result to the amplifying unit A2. The output of the amplifying unit A2 is commonly connected to the PMOS transistors M2 and M4 and the NMOS transistors M8 and M10 so as to construct a voltage follower.

(58) FIG. 10 is a specific circuit diagram of the current adder circuit. Referring now to FIG. 10, the current adder circuit contains a fourth current mirror circuit connected to a positive power supply voltage V.sub.DD2, a fifth current mirror circuit connected to the ground terminal GND, first and second floating constant current sources between the fourth and fifth current mirror circuit. In this case, the power supply voltage is V.sub.DD2 but may be V.sub.DD.

(59) The fourth current mirror circuit is a current mirror circuit of a low-voltage cascode connection. The fourth current mirror circuit contains PMOS transistors M21 to M24. The sources of the PMOS transistors M21 and M22 are connected to the positive power supply V.sub.DD2. The gate of the PMOS transistor M21 is connected to the gate of the PMOS transistor M22, and the gate of the PMOS transistor M23 is connected to the gate of the PMOS transistor M24. The drain of the PMOS transistor M21 is connected with the source of the PMOS transistor M23, and the drain of the PMOS transistor M22 is connected with the source of the PMOS transistor M24. The drain of the PMOS transistor M23 is connected with the gate of the PMOS transistor M21. The gates of the PMOS transistors M23 and M24 are connected to a bias terminal BP2. The source of the PMOS transistor M23 and the source of the PMOS transistor M24 are connected to a common node of the drains of the NMOS transistors M7 and M9 and to a common node of the drains of the NMOS transistors M8 and M10, respectively. The bias signal BP2 and the following bias signal BN2 are respectively set to a low level and a high level during the amplification.

(60) The fifth current mirror circuit is a current mirror circuit of a low-voltage cascode connection. The fifth current mirror circuit contains NMOS transistors M25 to M28. The sources of the NMOS transistors M25 and M26 are connected to the ground voltage GND. The gate of the NMOS transistor M25 is connected to the gate of the NMOS transistor M26, and the gate of the PMOS transistor M27 is connected to the gate of the NMOS transistor M28. The drain of the NMOS transistor M25 is connected with the source of the NMOS transistor M27, and the drain of the NMOS transistor M26 is connected with the source of the NMOS transistor M28. The drain of the NMOS transistor M27 is connected with the gate of the NMOS transistor M25. The gates of the NMOS transistors M27 and M28 are connected to a bias terminal BN2. The source of the NMOS transistor M27 and the source of the NMOS transistor M28 are connected to a common node of the drains of the PMOS transistors M2 and M4 and to a common node of the drains of the PMOS transistors M1 and M3, respectively.

(61) The first floating constant current source contains a PMOS transistor M30 and an NMOS transistor M29 which are connected in parallel. The source of the PMOS transistor M30 and the drain of the NMOS transistor M29 are connected to the drain of the PMOS transistor M23. Also, the drain of the PMOS transistor M30 and the source of the NMOS transistor M29 are connected to the drain of the NMOS transistor M27. The gate of the PMOS transistor M30 and the gate of the NMOS transistor M29 are connected to bias terminals BP3 and BN3, respectively. As a result, a constant current flows from the fourth current mirror circuit to the fifth current mirror circuit based on signals on the bias terminals BP3 and BN3.

(62) The second floating constant current source contains a PMOS transistor M32 and an NMOS transistor M31 which are connected in parallel. The source of the PMOS transistor M32 and the drain of the NMOS transistor M31 are connected to the drain of the PMOS transistor M24. Also, the drain of the PMOS transistor M32 and the source of the NMOS transistor M31 are connected to the drain of the NMOS transistor M28. The gate of the PMOS transistor M32 and the gate of the NMOS transistor M31 are connected to the bias terminals BP3 and BN3, respectively. As a result, a constant current flows from the fourth current mirror circuit to the fifth current mirror circuit based on signals on the bias terminals BP3 and BN3.

(63) In this current adder circuit, a node between the drain of the PMOS transistor M21 and the source of the PMOS transistor M23 commonly connected to each other, and a node between the drain of the PMOS transistor M22 and the source of the PMOS transistor M24 function as a positive current adding terminal. Also, a node between the drain of the NMOS transistor M25 and the source of the NMOS transistor M27 commonly connected to each other, and a node between the drain of the NMOS transistor M26 and the source of the NMOS transistor M28 function as a negative current adding terminal. A series circuit of capacitors C1 and C2 is connected between the drain of the PMOS transistor M22 and the drain of the NMOS transistor M28. A node between the capacitors C1 and C2 is connected with an output terminal OUT.

(64) An output stage circuit as the amplifying unit A2 contains a PMOS transistor M33 and an NMOS transistor M34 which are connected in series. The source of the PMOS M33 is connected to the positive power source terminal V.sub.DD2, and the source of the NMOS transistor M34 is connected to the negative power source terminal GND. The gate of the NMOS transistor M33 is connected to the drain of the PMOS transistor M24 as the output of the fourth current mirror circuit, and the gate of the NMOS transistor M34 is connected to the drain of the NMOS transistor M28 as the output of the fifth current mirror circuit. A node between the PMOS transistor M33 and the NMOS transistor M34 is connected with the output terminal OUT. The output stage circuit constitutes a so-called an AB class output circuit, and an idling current is determined based upon a voltage between the above-described bias terminals BP3 and BN3.

(65) In this current adder circuit, signals of transistors which are connected to respective current adding terminals are added to each other, and an adding result is outputted to an output terminal OUT. Since the differential amplifier shown in FIG. 9 is provided with the current adder circuit shown in FIG. 10, input currents are not added to each other in the active load, but are separately processed.

(66) In the second embodiment, the following calculation is carried out, assuming now that a voltage at the common sources of the PMOS transistor differential stage is V.sub.MP, and a voltage at the common sources of the NMOS transistor differential stage is V.sub.MN.
4I.sub.1P=2I.sub.1P+I2P+I.sub.3P (4)
4I.sub.1N=2I.sub.2N+I.sub.3N (5)
Since the current flowing through the active loads are equal to each other, the following equations (24) and (25) can be obtained:
I.sub.2P+I.sub.3P=2I.sub.1N (24)
I.sub.2N+I.sub.3N=2I.sub.1P (25)
Even if the left side of the equation (25) is added to the right side of the equation (24), and the right side of the equation (25) is added to the left side of the equation (24), the following equation (26) can be satisfied:
I.sub.2P+I.sub.3P+2I.sub.1N=I.sub.2N+I.sub.3N+2I.sub.1P (26)

(67) It could be understood that this equation (26) is completely the same as the equation (6) of the differential amplifier (namely, differential amplifier which adds the N-channel output to the P-channel output in the active load) in the first embodiment. Therefore, the calculation results become equal to each other. In other words, the differential amplifier shown in FIG. 9 outputs a desirable half voltage of the two input voltages.

(68) Moreover, since the circuit arrangement of the present invention is employed, an input Rail-to-rail can be realized. In FIG. 9, in order to realize the input Rail-to-rail as the entire characteristic of the differential amplifier, the circuit arrangement of the current adder circuit is important. This reason will now be described with reference to FIG. 9. First of all, in order to realize the input Rail-to-rail, all of the input stage transistors M1 to M4, or all of other transistors M7 to M10 are required to enter into a pentode region (namely, saturation region). This is because of the following reason. That is, if these transistors M1 to M4, or M7 to M10 enters into a triode region, the output resistance of the transistor is extremely lowered, and the mutual conductance gm of the transistor is also lowered, so that these transistors cannot carry out the normal differential stage transistor operation. A condition when an MOS transistor enters into the pentode region (saturation region) is expressed by the following equation (27), assuming now that a drain-to-source voltage is V.sub.DS, a gate-to-source voltage is V.sub.GS, and a threshold voltage is V.sub.T:
V.sub.DS>V.sub.GSVT (27).

(69) In this case, the condition under which the PMOS transistors M1 to M4 enters into the pentode region (saturation region) when the input voltage becomes the minimum voltage of GND (zero volt) is the gate voltage of GND (zero volt), since the source voltages of these PMOS transistor become equal to V.sub.GS. On the other hand, assuming now that a drain voltage is equal to V.sub.D, the source-to-drain voltage V.sub.DS is given by the following equation (28):
V.sub.DS=V.sub.GSV.sub.D (28).
Based upon the conditions defined by the above-described equation (27) and equation (28), the current adder circuit needs to be designed in such a manner that the following equation can be satisfied:
V.sub.GSV.sub.D>V.sub.GSV.sub.T,
namely,
V.sub.D<V.sub.T (29).
The voltage V.sub.D is a voltage of a node to which the drains of the MOS transistors M1 and M3, or the drains of the MOS transistors M2 and M4 are connected. Based upon this condition and the above-described equation (29), the input voltage of the current adder circuit must be set lower than or equal to VT. Now, as a specific value, since a threshold voltage VT of a general transistor is approximately 0.7 V, the input voltage of the current adder circuit needs to be lower than or equal to approximately 0.7 V in accordance with the equation (29).

(70) Similarly, the condition under which the NMOS transistors M7 to M10 enters into the pentode region (saturation region) when the input voltage is equal to the maximum potential of V.sub.DD is the gate voltages of V.sub.DD. Therefore, the source voltages of these NMOS transistors become equal to V.sub.DDV.sub.GS at this time. On the other hand, assuming now that the drain voltage is equal to V.sub.D, the source-to-drain voltage V.sub.DS is given by the following equation (30):
V.sub.DS=V.sub.D(V.sub.DDV.sub.GS) (30)
Based upon the conditions defined by the above-described equation (27) and equation (30), the current adder circuit is required to be designed in such a manner that the following equation can be satisfied:
V.sub.DV.sub.DD+V.sub.GS>V.sub.GSV.sub.T
namely,
V.sub.DDV.sub.D<V.sub.T (31).
The drain voltage V.sub.D is a terminal voltage of a node to which the drains of the NMOS transistors M7 and M9, or the drains of the NMOS transistors M8 and M10 are connected. Based upon this condition and the above-described equation (31), the input voltage of the current adder circuit must be set higher than or equal to V.sub.DDV.sub.T. Now, as specific value, the input voltage is required to be set higher than or equal to approximately (V.sub.DD0.7V). The current adder circuit of FIG. 9 is required to be designed in such a manner that the above-explained conditions can be satisfied. It should be noted that one example of the current adder circuits capable of satisfying the conditions is the circuit arrangement of the current adder circuit shown in FIG. 10.

(71) Next, the reason why this current adder circuit of FIG. 10 can satisfy the above-described conditions will now be explained. The input terminal voltage of the current adder circuit when the input voltage is equal to GND (zero volt) is drain voltages V.sub.D(M25/M26) of the NMOS transistors M25 and M26. Assuming now that the terminal voltage of the bias terminal BN2 is V.sub.BN2 and the gate-to-source voltage of each of the NMOS transistors M27 and M28 is V.sub.GS(M27/M28), this drain voltage V.sub.D(M25/M26) is given by the following equation (32):
V.sub.D(M25/M26)=V.sub.BN2V.sub.GS(M27/M28) (32).
In this case, this terminal voltage V.sub.BN2 of the bias terminal BN2 is generated by the gate-to-source voltage of the MOS transistor in a general design. Therefore, the above -equation (32) is modified as follows:
V.sub.D(M25/M26)=V.sub.GSV.sub.GS(M27/M28)<0.7 V (33).
As a consequence, this equation (33) can satisfy the above conditions. Similarly, when the input voltage is the maximum potential of V.sub.DD, the above-described conditions can be satisfied. Thus, if such a circuit arrangement is employed, the input Rail-to-rail can be realized. As a result, the use efficiency of the power supply can be increased, and the low voltage and the low power consumption can be realized.

(72) FIG. 11 is a diagram showing another specific circuit of the current adder circuit. Referring now to FIG. 11, this current adder circuit will be described. The current adder circuit shown in FIG. 11 is composed of a sixth current mirror circuit connected to the positive power supply, a seventh current mirror circuit connected to the ground terminal GND, and a third floating constant current source. This sixth current mirror circuit is composed of PMOS transistors M41 and M42. The gate of the PMOS transistor M41 is connected to the gate of the PMOS transistor M42, and the drain of the PMOS transistor M41. Also, the sources of the PMOS transistors M41 and M42 are connected to the positive power supply voltage V.sub.DD2. The drains of the PMOS transistor M41 and M42 are connected to a node of the drains of the NMOS transistors M7 and M9 and a node of the drains of the NMOS transistors M8 and M10, respectively.

(73) This seventh current mirror circuit is composed of NMOS transistors M43 and M44. The gate of the NMOS transistor M43 is connected to the gate of the NMOS transistor M44, and the drain of the NMOS transistor M43. Also, the sources of the NMOS transistors M43 and M44 are connected to the ground voltage GND. The drains of the NMOS transistor M43 and M44 are connected to a node of the drains of the PMOS transistors M2 and M4 and a node of the drains of the PMOS transistors M1 and M3, respectively.

(74) The third floating constant current source is composed of a PMOS transistor M52 and an NMOS transistor M51 which are connected in parallel. The source of the PMOS transistor M52 and the drain of the NMOS transistor M51 are commonly connected to the drain of the NMOS transistor M44. Also, the source of the PMOS transistor M52 and the drain of the NMOS transistor M51 are commonly connected to the drain of the PMOS transistor M42. The gate of the PMOS transistor M52 and the gate of the NMOS transistor M51 are connected with bias terminals BP3 and BN3, respectively.

(75) A series circuit of a constant current source CC3, capacitors C1 and C2, and a constant current source CC4 is provided between the positive power supply voltage V.sub.DD2 and the ground voltage GND. A node between the constant current source CC3 and the capacitor C1 is connected with the drain of the PMOS transistor M42. Also, a node between the constant current source CC4 and the capacitor C2 is connected with the drain of the NMOS transistor M44. A node between the capacitors C1 and C2 is connected with an output terminal OUT.

(76) An output stage circuit is composed of a PMOS transistor M53 and an NMOS transistor M54 which are connected in series between the power supply voltage V.sub.DD2 and the ground voltage GND. The gate of the PMOS transistor M53 is connected to the drain of the PMOS transistor M42 and the node between the constant current source CC3 and the capacitor C1. Also, the gate of the NMOS transistor M54 is connected to the drain of the NMOS transistor M44 and the node between the constant current source CC4 and the capacitor C2. A node between the PMOS transistor M53 and the NMOS transistor M54 is connected with the output terminal OUT. This output stage circuit constitutes a so-called AB class output circuit, and an idling current is determined based upon a voltage between the bias terminals BP3 and BN3. The constant current source CC3 flows a same current as the constant current source CC4 flows, and may be same as a current flowing through the third floating constant current source.

(77) In this current adder circuit shown in FIG. 11, current consumption becomes small, as compared with that of the current adder circuit of FIG. 10. The reason is in that the first floating constant current source of MOS transistors M29 and M30 can be omitted in the current adder circuit in FIG. 11 as well as the current flowing through the current path of the transistors M51/M52 can be reduced to a minimum current value in a design.

(78) As described above, in accordance with the present invention, the NMOS transistor differential amplifier and the PMOS transistor differential amplifier are combined with each other so as to cancel the errors in the respective differential amplifiers. As a result, when the two different input voltages V.sub.1 and V.sub.2 are supplied to the two input terminals, the averaged voltage, namely, (V.sub.1+V.sub.2)/2) can be correctly outputted.