Optical receiver

Abstract

A receiver has a differential transimpedance amplifier (4) with two inputs and two outputs. The differential transimpedance amplifier (4) provides a differential output and this is peak-detected (15, 16) to provide amplitude reference signals. The differential transimpedance amplifier output and the amplitude reference signals are fed to a differential summing amplifier (10), which provides a fully differential signal to a comparator, or to an automatic gain control circuit (5) to regulate the differential transimpedance amplifier gain. The differential summing amplifier (10) output is a fully differential signal, thereby having lower distortion for DC and burst mode receiver applications.

Claims

1. An optical receiver comprising: a differential transimpedance amplifier TIA having input cascodes, and being arranged to receive one or more photodiode inputs and to provide at least two outputs, positive and negative, a positive peak detector receiving the positive differential TIA output, a negative peak detector receiving the negative differential TIA output, and each providing a peak detection output as an amplitude reference signal, a differential summing amplifier arranged to receive the outputs of the differential TIA and the amplitude reference signals from the peak detectors, wherein said differential summing amplifier directly or indirectly provides an output for the optical receiver, wherein the receiver further comprises an automatic gain circuit for the differential transimpedance amplifier, and wherein the differential summing amplifier is connected at its output to the automatic gain circuit, and wherein the peak detector output is fed into the differential summing amplifier with less gain than gain of the differential TIA inputs into the differential summing amplifier.

2. The optical receiver as claimed in claim 1, wherein one photodiode is active and another photodiode is a dummy photodiode.

3. The optical receiver as claimed in claim 1, wherein the differential summing amplifier has linear gain.

4. The optical receiver as claimed in claim 1, wherein the differential summing amplifier is an active low pass filter.

5. The optical receiver as claimed in claim 1, wherein said gain of the peak detector output is less by approximately half.

6. The optical receiver as claimed in claim 1, wherein the differential summing amplifier is connected at its output to a decision circuit, preferably a comparator.

7. The optical receiver as claimed in claim 1, wherein the cascodes are regulated gate cascodes.

8. The optical receiver as claimed in claim 1, further comprising an output comparator linked with the output of the differential summing amplifier, and wherein the output comparator has built-in hysteresis.

9. The optical receiver as claimed in claim 8, wherein the output comparator has a DC offset level, with an offset level control input (V.sub.OFFSET.sub._.sub.ENABLE), which is controlled by the control circuit and is adapted to ensure that the output is low for a minimum light level received.

10. The optical receiver as claimed in claim 1 further comprising a reset control circuit configured to reset the peak detectors.

11. The optical receiver as claimed in claim 10, wherein the reset control circuit is configured to assert offset level control (V.sub.OFFSET.sub._.sub.ENABLE), and reset control (V.sub.RESET) after a set timeout period when no light is received.

12. An electronic or electro-optic device comprising a processing circuit linked to a receiver of claim 1.

13. An optical receiver comprising: a differential transimpedance amplifier TIA having input cascodes, and being arranged to receive one or more photodiode inputs and to provide at least two outputs, positive and negative, a positive peak detector receiving the positive differential TIA output, a negative peak detector receiving the negative differential TIA output, and each providing a peak detection output as an amplitude reference signal, a differential summing amplifier arranged to receive the outputs of the differential TIA and the amplitude reference signals from the peak detectors, wherein said differential summing amplifier directly or indirectly provides an output for the optical receiver, wherein the receiver further comprises an automatic gain circuit for the differential transimpedance amplifier, and wherein the differential summing amplifier is connected at its output to the automatic gain circuit, wherein the optical receiver further comprises an output comparator linked with the output of the differential summing amplifier, and wherein the output comparator has built-in hysteresis, and wherein the output comparator has a DC offset level, with an offset level control input (V.sub.OFFSET.sub._.sub.ENABLE), which is controlled by the control circuit and is adapted to ensure that the output is low for a minimum light level received.

14. An optical receiver as claimed in claim 13, further comprising a reset control circuit configured to reset the peak detectors, wherein the reset control circuit is configured to assert offset level control (V.sub.OFFSET.sub._.sub.ENABLE), and reset control (V.sub.RESET) after a set timeout period when no light is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

Brief Description of the Drawings

(1) The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:

(2) FIG. 1 is a set of representative plots showing light input signals and pseudo and fully differential outputs, as discussed above with reference to the prior art;

(3) FIG. 2 is a block diagram of a receiver of the invention;

(4) FIGS. 3(a) and 3(b) are circuit diagrams of positive peak detector and negative peak detector components of the receiver illustrated in FIG. 2;

(5) FIG. 4 is a circuit diagram of a differential summing amplifier of the receiver illustrated in FIG. 2;

(6) FIG. 5 is a series of plots showing stages of how the receiver provides a fully differential signal;

(7) FIG. 6 is a logic diagram for operation of the receiver for reset and DC offset level control; and

(8) FIG. 7 is a series of plots showing stages of how the receiver provides a fully differential signal, from a distorted TIA output.

DESCRIPTION OF THE EMBODIMENTS

(9) We describe various optical receivers which have lower distortion. In some embodiments this is achieved because the output crosses the zero line, thereby providing a fully differential output. The receiver has a differential transimpedance amplifier with two inputs and two outputs. The differential transimpedance amplifier, provides a differential output and this is peak-detected to provide amplitude reference signals. The differential transimpedance amplifier output and the amplitude reference signals are fed to a differential summing amplifier, which provides a fully differential output to a comparator, or an automatic gain control circuit to regulate the differential transimpedance amplifier gain.

(10) Referring to FIG. 2 an optical receiver 1 of the invention has regulated cascode (RGC) circuits 2 and 3 at the inputs to a first amplifier, in this case a differential TIA 4 with an AGC 5.

(11) A differential summing amplifier (DSA) 10 receives the TIA 4 positive and negative outputs TIA_plus and TIA_minus. However, in addition there are two peak detectors 15 and 16. They receive the TIA_plus and TIA_minus signals respectively and provide the amplitude reference PkDet_plus and PkDet_minus outputs to the DSA 10. The defined bandwidth of the DSA is designed to the required application to filter out high frequency noise or disturbances. A reset and control circuit 17 is provided for resetting the detectors 15 and 16, and for providing an offset enable V.sub.OFFSET.sub._.sub.ENABLE signal to a comparator 20 providing the output signal V.sub.out.

(12) The DSA 10 provides DSA_plus and DSA_minus signals as inputs to the comparator 20, and to the AGC (automatic gain control circuit) 5. The AGC 5 input requires a linear representation of the received optical light power to assist in the loop design and stability, which is provided by the linear DSA 10 gain.

(13) As shown in FIG. 3(a) the peak detector 15 comprises a first amplifier 30 feeding a second amplifier 31 via a diode 33. There is a capacitor C1 to ground providing a peak detected amplitude reference input to the amplifier 30. The reset signal is connected to the gate of a switch 32 which links the signal input to the second amplifier 31 to ground. The output PkDet_plus is provided by the output of the second amplifier 31.

(14) The negative peak detector 16 (FIG. 3(b)) has a similar architecture, with first and second amplifiers 35 and 36, a capacitor C2, a reset switch 37, and a diode 38. In most applications the amplifiers 30 and 35 can be identical, as can the amplifiers 31 and 36.

(15) The DSA 10 (FIG. 4) comprises an amplifier 40 with feedback links via resistors R.sub.FB from the DSA_minus and DSA_plus outputs, which ensures that the DSA gain is linear, which is of benefit when using an AGC. The peak detector inputs are passed through resistances which are greater than those of the TIA inputs, in this case double. This reduces the gain of the differential peak detector by half compared to the differential TIA signals. The amplifier 40 contains common mode feedback with the common mode reference set from the common mode output of the TIA outputs.

(16) In more detail, and referring again also to FIG. 2, the transducers are a signal receiving photodiode 51 and a dark photodiode 52, both of which are connected to the RGC 2 and 3, which feed into the differential TIA 4 whose gain may be adjusted with the AGC 5 control loop. The outputs of the differential TIA 4 feed into the DSA 10 and the two peak detectors 15 and 16 similarly connect into the DSA 10 with half the gain. The DSA stage 10 converts a pseudo differential input signal from the differential TIA 4 to a fully differential output signal which is connected to the comparator 20 and the AGC 5. The gain of the DSA is linear so that the AGC can automatically control the TIA gain, to ensure there is no saturation of the TIA. The comparator 20 may include a hysteresis function. The pseudo differential TIA output signals and the peak detected signals from the peak detector are fed into the DSA 10 almost simultaneously, and generate the fully differential output with minimum delay. The comparator may also include an offset level control input V.sub.OFFSET.sub._.sub.ENABLE which ensures the comparator will output a low until the input from the DSA is above an offset level. This can be used to ensure that the comparator outputs a low in static off mode, which is needed for receiving DC or low megahertz data. When light is being received V.sub.OFFSET.sub._.sub.ENABLE is disabled so that comparator has a zero crossover offset to achieve high quality PWD performance.

(17) FIG. 4 shows the DSA circuit with the output equal to:

(18) ${\mathrm{DSA}}_{\mathrm{diff}}={\mathrm{Gain}}_{\mathrm{DSA}}*\left[{\mathrm{TIA}}_{\mathrm{diff}}-\left(\frac{{\mathrm{PkDet}}_{\mathrm{diff}}}{2}\right)\right]$$\mathrm{where}$${\mathrm{DSA}}_{\mathrm{diff}}=\mathrm{DSA\_plus}-\mathrm{DSA\_minus},{\mathrm{TIA}}_{\mathrm{diff}}={\mathrm{TIA}}_{\mathrm{plus}}-\mathrm{TIA\_minus}$${\mathrm{PkDet}}_{\mathrm{diff}}=\mathrm{PkDet\_plus}-\mathrm{PkDet\_minus}$
are the differential outputs of the DSA, TIA and peak detector circuit, with the linear gain of the DSA circuit:

(19) ${\mathrm{Gain}}_{\mathrm{DSA}}=\frac{R_{\mathrm{FB}}}{R_{\mathrm{IN}}}.$

(20) The

(21) $\frac{{\mathrm{PkDet}}_{\mathrm{diff}}}{2}$
is achieved by having 2R.sub.IN at the peak detector inputs to the DSA circuit. Assuming R.sub.IN=R.sub.FB, Gain.sub.DSA=1 the output of the DSA is equal to:

(22) ${\mathrm{DSA}}_{\mathrm{diff}}=\left[{\mathrm{TIA}}_{\mathrm{diff}}-\left(\frac{{\mathrm{PkDet}}_{\mathrm{diff}}}{2}\right)\right]$

(23) Table 1 below describes the output states of the TIA, Peak Detector, DSA, DC Ref Level input, and comparator output, for static off, light on and off modes, assuming Gain.sub.DSA=1.

(24) TABLE-US-00001 TABLE 1 Outputs for static off, light on and off modes Static off mode Light On Light Off Comment Differential 0 TIA.sub.diff 0 TIA output Peak Detector 0 TIA.sub.diff_max where PkDet.sub.diff = TIA.sub.diff_max Output after 1st pulse of light Differential Summing Amplifier (DSA) output 0 $+\left(\frac{{\mathrm{TIA}}_{\mathrm{diff}}}{2}\right)$ $-\left(\frac{{\mathrm{TIA}}_{\mathrm{diff}}}{2}\right)$ $\begin{array}{c}\mathrm{where}{\mathrm{DSA}}_{\mathrm{diff}}=\\ \left[{\mathrm{TIA}}_{\mathrm{diff}}-\left(\frac{{\mathrm{PkDet}}_{\mathrm{diff}}}{2}\right)\right]\end{array}$ Offset Level Control Enabled Disabled Enabled only when waiting V.sub.OFFSET_ENABLE for 1.sup.st pulse Comparator Output Low High Low

(25) FIG. 5 illustrates the relevant signals from the block diagram in FIG. 2. The signals show the pseudo differential TIA output signals (TIA_plus, TIA_minus). The PkDet_plus signal is the maximum of the TIA_plus signal, and the PkDet_minus is the minimum of the TIA_minus signal. The TIA output signals, and the positive and negative peak detectors signals are all combined to create the fully differential DSA output signals (DSA_plus, DSA_minus). The DSA outputs (DSA_plus, DSA_minus) are used by the comparator to generate the digital comparator output (Comp Vout). The comparator has hysteresis controlled by V.sub.OFFSET.sub._.sub.ENABLE.

(26) The flow diagram of FIG. 6 describes the operation of the reset (V.sub.RESET) and offset level control (V.sub.OFFSET.sub._.sub.ENABLE) signals. Once in static off mode, if light is received then the V.sub.OFFSET.sub._.sub.ENABLE is disabled into the comparator. If no light is received for a timeout period then the V.sub.OFFSET.sub._.sub.ENABLE is enabled and the peak detectors are reset so the receiver returns to static off mode. This control of the V.sub.OFFSET.sub._.sub.ENABLE signal allows the receiver to receive DC to megahertz data.

(27) A major benefit of two peak detectors is that they balance the capacitive loading on the differential TIA, which improves the accuracy of the receiver architecture in EMI and noise rejection, and the accuracy for receiving low input power. When light is received the outputs of the TIA can be unbalanced. This means that the difference between the common mode of the TIA, and its outputs TIA_plus and TIA_minus signals may not be equal. This is illustrated by the deliberately distorted TIA outputs in FIG. 7. Combining the two peak detectors and the DSA helps to remove the majority of these unbalanced TIA outputs. With suitable DSA gain, the DSA output is a fully differential output with equal amplitudes for both light on and off cases, even though the TIA outputs are unbalanced. The removal of this distortion results in a low PWD output.

(28) The architecture in FIG. 2 has multiple advantageous roles: (a) Creation of a fully differential signal from the pseudo differential TIA outputs. (b) Provides equal loading on the TIA outputs, which keeps the architecture symmetric. (c) Reduces most of the possible imbalance in the TIA outputs for received light. (d) The DSA amplifies the signal from the TIA outputs for low received light power. (e) The DSA filters the signals to the required bandwidth so that no high frequency noise is fed through to the comparator 20. (f) The DSA provides a linear representation of the light received to the AGC, with the linear DSA gain. (g) Insofar as possible a symmetric differential architecture is created from the TIA outputs to the comparator inputs.

(29) It will be appreciated that the invention achieves a fully differential output without significant delay because of its ability to produce a fully differential signal on the first pulse, which is important in detecting a signal from a single high speed input pulse. The advantages of implementing with two peak detectors and a DSA, with reduced propagation delay ensures that the DSA output will respond with negligible delay to the differential TIA outputs, and with the benefit of a high tolerance to any TIA imbalances. The linear gain of the DSA allows the outputs to be used by an AGC, as it a linear representation of the light received.

(30) Also, there is reduced noise induced by EMI and other sources because the differential TIA architecture, the balanced load architecture of two peak detectors and the differential summing amplifier will reject any common interference. The differential summing amplifier can be used to amplify low amplitude TIA signals, and to filter the signals to the required bandwidth, which improves the signal to noise ratio of the inputs to the comparator.

(31) The invention is not limited to the embodiments described but may be varied in construction and detail. In one example the photodiodes are monolithic integrated photodiodes. This is advantageous because there is no wire-bond induced disturbances or noise for the receiver to reject, which would be the case for an external pin photodiode. The receiver may have transducers other than photodiodes and may in some cases be optical receivers.