Sigma-delta modulator

Abstract

Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.

Claims

1. A sigma-delta modulator circuit comprising: a loopfilter having at least one integrator or resonator section, and an output summation node after the integrator or resonator section; a feed-forward path configured to provide a feed-forward signal to the output summation node via a filter configured to implement a specific phase shift and compensate peaking behavior in a signal transfer function of the sigma-delta modulator, the feed-forward signal being taken from a circuit node before the at least one integrator or resonator section; and an ADC; wherein the output summation node is directly coupled to the ADC.

2. The circuit of claim 1, wherein the feed-forward signal is the sigma-delta modulator circuit input signal.

3. The circuit of claim 1, further comprising: a feedback path configured to combine an output signal of the sigma-delta modulator circuit with an input signal of the sigma-delta modulator circuit so as to provide the loopfilter input signal, wherein the feed-forward signal is the loopfilter input signal.

4. The circuit of claim 1, wherein the circuit node is within the loopfilter.

5. The circuit of claim 1, wherein the sigma-delta modulator circuit is a discrete-time sigma-delta modulator circuit, and wherein the filter is configured to implement a time delay.

6. The circuit of claim 1, wherein the ADC is a quantizer configured to quantize an output signal from the loopfilter.

7. The circuit of claim 1, further comprising: a second feed-forward path configured to provide a second feed-forward signal via a second filter, the second feed-forward path being different from the feed-forward path.

8. A circuit arrangement comprising: the sigma-delta modulator circuit as claimed in claim 1.

9. A switched-mode power supply comprising the sigma-delta modulator circuit as claimed in claim 1.

10. A method of operating a sigma-delta modulator circuit comprising a loopfilter having at least one integrator or resonator section, and an output summation node after the integrator or resonator section, wherein the output summation node is directly coupled to an ADC, the method comprising: providing a feed-forward signal to the output summation node via a filter configured to implement a specific phase shift and compensate peaking behavior in a signal transfer function of the sigma-delta modulator, wherein the feed-forward signal is taken from a circuit node before the at least one integrator or resonator section.

11. The method of claim 10, wherein the feed-forward signal is the sigma-delta modulator circuit input signal.

12. The method of claim 10, further comprising: combining an output signal of the sigma-delta modulator circuit with an input signal of the sigma-delta modulator circuit so as to provide the loopfilter input signal, wherein the feed-forward signal is the loopfilter input signal.

13. The method of claim 10, wherein the circuit node is within the loopfilter.

14. The circuit of claim 1, wherein the feed-forward signal is filtered but not amplified.

15. The circuit of claim 1, wherein the output summation node follows all of the integrator or resonator sections.

16. The circuit of claim 1, wherein the specific phase shift is implemented using a weighted vector summation of quadrature signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings in which:

(2) FIG. 1 shows a basic configuration of a conventional delta-sigma modulator;

(3) FIG. 2 is a schematic block diagram of a conventional 4.sup.th-order sigma-delta modulator having distributed feed-forward paths;

(4) FIG. 3 is shows a possible signal transfer function for the 4th-order sigma-delta modulator of FIG. 2;

(5) FIG. 4 is a schematic block diagram of a 3rd-order feed-forward sigma-delta modulator according to an embodiment of the invention;

(6) FIG. 5 is a schematic block diagram of a 3.sup.rd-order continuous-time sigma-delta modulator with a resonator implemented as a single-opamp biquad filter and a single signal feed-forward path;

(7) FIG. 6 shows a possible implementation for the signal feed-forward path of FIG. 5;

(8) FIG. 7 is schematic block diagram of a 4th-order feed-forward sigma-delta modulator according to an embodiment of the invention; and

(9) FIG. 8 is a graph illustrating the STF for the modified embodiment of FIG. 6.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(10) It is proposed to tune the peaking behaviour of the STF by adding a filter in the signal feed-forward path of a sigma-delta modulator.

(11) Referring to FIG. 4, there is shown a 3.sup.rd order feed-forward sigma-delta modulator according to an embodiment. The modulator comprises a series connection of three integrators Int1 to Int3. Feed-forward paths c.sub.1-c.sub.3 are provided from the output of each integrator to an output summation node 26 at the output of the loop filter. The output of the output summation node 26 is provided to a quantizer ADC 20.

(12) The digital output from the ADC 20 is converted to an analog feedback signal by a DAC 22, which is then subtracted from the input signal x at an input summation node 28 (which subtracts the analog feedback signal provided by the DAC 22 from the input signal x) to provide the loopfilter input signal Lx (i.e. the input of the first integrator Int1).

(13) It is further assumed that, in this example, the integrator stages Int1-Int3 are implemented as continuous-time integrators with a transfer function .sub.i/s, wherein .sub.i is the unity gain frequency of the i.sup.th integrator stage. For simplicity, it will be assumed that the unity gain frequency for each stage is equal to 1. In that case, the transfer function of the feed-forward path of the modulator of FIG. 4 can be as the following equation (Equation 1):

(14) $\begin{array}{cc}{H}_{\mathrm{FW}}=\frac{c_1{s}^2+c_{2}s+c_3}{s^3}& \left(\mathrm{Equation}1\right)\end{array}$
The STF peaking issue of the sigma-delta modulator can be resolved by eliminating the s terms in the numerator polynomial.

(15) An implementation to cancel the s-terms from the numerator has been applied to a conventional sigma-delta circuit to arrive at the circuit shown in FIG. 4, wherein additional signal feed-forward paths have been added.

(16) A first feed-forward path comprises a first filter k1 connected between the input signal x and the output of the first integrator Int1. A second feed-forward path comprises a second filter k2 connected between the input signal x and the output of the second integrator Int2. Thus, the output of the first filter k1 is combined with output of the first integrator Int1 at second summation node 29a, and the output of the second filter k2 is combined with output of the second integrator Int2 at third summation node 29b.

(17) Each feed-forward path is adapted to provide a feed-forward signal to the output of a respective integrator section via a respective filter. The feed-forward signal of each feed-forward path is taken from the input signal x of the sigma-delta modulator (from which the inputs of the first Int1 and second int2 integrators are derived).

(18) This modifies the feed-forward filter transfer function into the following equation (Equation 2):

(19) $\begin{array}{cc}{H}_{\mathrm{FW}}=\frac{\left(c_2.Math.k_1+c_3.Math.k_2+c_1\right)s^2+\left(c_3.Math.k_1+c_2\right)s+c_3}{s^3}& \left(\mathrm{Equation}.2\right)\end{array}$

(20) If the first k1 and second filters k2 are chosen to be as follows:

(21) $\begin{array}{cc}{k}_1=-\frac{c_2}{c_3}{k}_2=-\frac{c_1}{c_3}+{\left(\frac{c_2}{c_3}\right)}^2,& \left(\mathrm{Equation}3\right)\end{array}$
the forward transfer function is modified to the following equation (Equation 4):

(22) $\begin{array}{cc}{H}_{\mathrm{FW}}=\frac{c_3}{s^3},& \left(\mathrm{Equation}.4\right)\end{array}$
which does not give rise to STF peaking.

(23) It is noted here that different values for feed-forward paths k1 and or k2 may also result in elimination or reduction of the STF peaking.

(24) In certain situations, it may be that (due to the implementation of the loop filter, for example), certain nodes in the loopfilter are not physically accessible. This can be the case, for example, if a single-opamp biquad filter architecture is used to implement (part of) the loopfilter.

(25) An example is shown in FIG. 5, where the loopfilter consists of an integrator Int1 and a resonator 30. In this case, the resonator is implemented as a single opamp biquad filter (dashed box labelled 30).

(26) Here, the single opamp biquad filter 30 comprises the second Int2 and third Int3 integrators connected in series, with the output of the third integrator Int3 being provided to a feedback summation node 29c via a feedback path d1. The feedback summation node 29c sums the input of the single opamp biquad filter 30 with then feedback signal from the integrator d1 and provides the summation as the input signal of the second integrator Int2. A feedforward path is provided from the output (i.e. internal node w2) of the second integrator Int2 to an output summation node 29d via a feedforward integrator c2. The output summation node 29d combines (i.e. sums) the output from the feedforward integrator c2 with the output of the third integrator Int3 to provide the output signal of the biquad filter 30.

(27) As a result, the internal node w2 (although shown in FIG. 5) cannot be accessed and a second signal feed-forward path k2 as in FIG. 4 cannot be implemented. In this case the forward path transfer function may be represented by the following equation (Equation 5) (assuming d1=0 for simplicity):

(28) $\begin{array}{cc}{H}_{\mathrm{FW}}=\frac{\left(c_2.Math.c_3.Math.k_1+c_1\right)s^2+\left(c_3.Math.k_1+c_2.Math.c_3\right)s+c_3}{s^3}& \left(\mathrm{Equation}5\right)\end{array}$
Now, the forward transfer function can be simplified into the one of Eq. 4 in case k1 is a filter that is equal to Eq. 6:

(29) $\begin{array}{cc}{k}_1=-\frac{c_{1}s+c_2.Math.c_3}{c_2.Math.c_{3}s+c_3},& \left(\mathrm{Equation}6\right)\end{array}$
which has a pole and a zero.

(30) A possible implementation for the filter transfer of Equation 6 is shown in FIG. 6. The transfer function of this filter may be represented by the following equation (Equation 7):

(31) $\begin{array}{cc}H=-\frac{R_1{R}_2{C}_{1}s+R_2}{R_1{R}_2\left(C_1+C_2\right)s+R_1+R_2}& \left(\mathrm{Eq}.7\right)\end{array}$

(32) Other types of filter may also be implemented in the feed-forward path from the input of the modulator to the output of one of the integrator sections of the loop filter. Also, multiple filters may be implemented from the input of the modulator to the output of multiple integrator or resonator sections of the loop filter. Further, instead of the input signal x of the modulator, other signals may be fed-forward from different nodes of the loopfilter, for example the input signal Lx of the loopfilter.

(33) Referring to FIG. 7, there is shown a 4.sup.th-order feed-forward sigma-delta modulator according to an embodiment. The sigma-delta modulator circuit 100 is similar to that of FIG. 2 in that it comprises a series connection of four integrators Int1 to Int4. A feed-forward path is provided from the output of each of the integrators Int1, Int2, Int3 Int4 to output summation node 26 (which provides the input of the ADC 20). The digital output from the ADC 20 is converted to an analogue signal by a first DAC 22 which provides the analogue signal to the input summation node 28 (which subtracts the analog feedback signal provided by the DAC 22 from the input signal x) to provide the input of the first integrator Int1. Thus, a feedback path is provided which combines an output signal of the sigma-delta modulator circuit with an input signal of the sigma-delta modulator circuit so as to provide the input signal of the first integrator Int1.

(34) The digital output from the ADC 20 is also converted to an analogue signal at second DAC 24 which provides the analogue signal to the output summation node.

(35) The sigma-delta modulator circuit 100 of FIG. 7 differs from the conventional circuit of FIG. 2 in that there is provided a feed-forward path from the input x of the modulator to the output summation node 26.

(36) Here, it is noted that the feed-forward path takes the input signal x of the modulator and provides it to the output summation node 26.

(37) The feed-forward path includes a filter 150. In this example, the filter 150 is a simple phase shift filter that introduces a phase shift into the feed-forward path. For example, the phase shift introduced by the filter 150 may be 30, 90, 120, 150, 180, etc.

(38) FIG. 8 shows an example STF for the 4.sup.th-order sigma-delta modulator of FIG. 7. From the graph of FIG. 8, it can be seen that (compared to the STF of conventional circuit) the peaking observed in embodiment of FIG. 7 is reduced considerably at low frequencies. In other words, the embodiment of FIG. 7 mitigates STF peaking that is typically present in a feed forward sigma-delta topology.

(39) Other types of filter may also be implemented in the feed-forward path from the input of the modulator to the output of one of the integrator sections of the loop filter. For example, the phase shift may be implemented using a weighted vector summation of quadrature signals.

(40) Also, for a discrete-time sigma-delta modulator circuit, a filter in the feed-forward path may be implemented using a time delay. Depending on the time delay implemented, the circuit may be optimised for particular frequencies.

(41) Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.