POWER CONVERTER AND METHOD FOR CONTROLLING POWER CONVERTER

Abstract

[Problem] To provide a single-direction insulative DC-DC power converter using a single-direction switch circuit capable of realizing soft switching even with a simple circuit configuration and a method for controlling the DC-DC power converter. [Solution] A power converter comprising a primary circuit and a secondary circuit connected via a high-frequency transformer, wherein a circuit having a switching element is provided to the primary circuit, the secondary circuit has, connected in parallel, a DC capacitor and a diode rectifying circuit including four diodes U+, U−, V+, and V− each having a resonance capacitor C.sub.r connected in parallel, and a resonance circuit formed by the resonance capacitor C.sub.r and a leakage inductance L of a the high-frequency transformer is formed in the secondary circuit.

Claims

1. A power converter comprising a primary circuit and a secondary circuit connected via a transformer, wherein the primary circuit comprises a circuit having a switching element, the secondary circuit comprises a diode rectification circuit including four diodes each having a resonance capacitor connected in parallel, and a smoothing capacitor connected in parallel, and in the secondary circuit, a resonance circuit is formed by a leakage inductance of the transformer and the resonance capacitor.

2. The power converter according to claim 1, wherein the primary circuit comprises a capacitor and an H-bridge circuit connected in parallel, and the H-bridge circuit comprises the four switching elements.

3. The power converter according to claim 1, wherein in the primary circuit, both ends of two capacitors connected in series to input and a half bridge circuit are connected in parallel, the half bridge circuit comprises the two switching elements connected in series, and a DC neutral point between the two capacitors and a DC neutral point between the two switching elements are connected to the primary side of the transformer.

4. The power converter according to claim 1, wherein the switching element realizes soft switching using any one or both of a parasitic capacitance of the switching element and a capacitor connected in parallel to the switching element.

5. The power converter according to claim 1, wherein an core of the transformer is configured to be made separable into a primary circuit and a secondary circuit.

6. A power control method for the power converter according to claim 1, comprising inputting a control signal for generating a square wave voltage in the soft switching circuit.

7. A power control method for the power converter according to claim 1, comprising adjusting output power of the secondary circuit by controlling a frequency of the square wave voltage.

8. A power control method for the power converter according to claim 2, comprising controlling a period T.sub.d during which the voltage of the primary terminal of the transformer is zero to thereby adjust output power of the secondary circuit without changing the frequency of the soft switching circuit.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0021] FIG. 1 is a circuit diagram of a power converter according to a first embodiment.

[0022] FIG. 2 is a diagram illustrating a conducting state of each switch, and voltage and current waveforms of a high-frequency transformer.

[0023] FIG. 3 is a diagram illustrating each commutation operation of a secondary side diode rectification circuit.

[0024] FIG. 4 is a diagram illustrating characteristics of output power Pout versus a ratio f.sub.s/f.sub.o of a frequency of the high-frequency transformer to a resonance frequency.

[0025] FIG. 5 is a diagram illustrating operating modes of a primary circuit and a primary voltage waveform v.sub.1 of the high-frequency transformer when a switch R− or S+ is commutated to a switch R+ or S− of the primary circuit.

[0026] FIG. 6 is a circuit diagram of a power converter according to a second embodiment.

[0027] FIG. 7 is an operating waveform diagram illustrating a method for controlling output power according to mode switching timing (mode 2-2).

[0028] FIG. 8 is an operating waveform diagram illustrating a method for controlling output power according to mode switching timing (mode 2-3).

[0029] FIG. 9 is an output power characteristic diagram versus a period Td during which the primary voltage v.sub.1 is zero.

DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, none of the following embodiments is intended to limit the recognition of the gist of the present disclosure. Moreover, the same reference numerals may be used for the same or similar components and description thereof may be omitted.

[0031] Note that, for example, an H-bridge circuit or a half bridge circuit may be used for the soft switching circuit of the primary circuit, but without being limited to this, any circuit can be used.

Basic Conception of Present Disclosure

[0032] A basic circuit configuration of the present disclosure is characterized by the use of a unidirectional insulated DC-DC power converter adopting a circuit configuration in which a primary circuit for generating square wave or the like by a circuit provided with a switching element and a secondary circuit configured only of passive elements and constructed by combining a rectification circuit and an LC resonance circuit, and the primary and secondary circuits are electromagnetically coupled by a transformer. Although it is a simple circuit configuration, supply power can be adjusted by a switching frequency of the primary circuit and the secondary circuit side is constructed only of passive elements, and so there is an advantage that the primary circuit side and the secondary circuit side can be separated by an iron core of the transformer. Hereinafter, a specific circuit diagram will be described with reference to the accompanying drawings.

First Embodiment

[0033] FIG. 1 illustrates a circuit diagram of a power converter (10) of a first embodiment. The present circuit is a unidirectional insulated DC-DC power converter, an H-bridge circuit is provided on a primary circuit (1) side, a secondary circuit (2) side is constructed of a diode rectification circuit, and the primary and secondary circuits are coupled by a high-frequency transformer Tr. Note that the primary circuit and the secondary circuit may be simply denoted as “primary side” and “secondary side” respectively. The high-frequency transformer Tr may be simply denoted as “transformer.”

[0034] The primary side H-bridge circuit is constructed of four switching elements R+, R−, S+ and S−. An antiparallel diode is connected to each switching element. A parasitic capacitance (stray capacitance) of the switching element is denoted as Cs. The primary side H-bridge circuit converts an input DC voltage V.sub.in to a high-frequency square wave AC voltage v.sub.1.

[0035] Note that a leakage inductance of the high-frequency transformer Tr is denoted as L, a leakage inductance of the entire high-frequency transformer is denoted as a converted value on the secondary side. When the leakage inductance is small, a reactor is connected in series to the transformer, and the leakage inductance L (inductance L) includes a leakage inductance of the high-frequency transformer itself and the inserted reactor. When the numbers of turns of the primary wiring and the secondary wiring of the transformer are defined as n1 and n2 respectively, a secondary converted value of the primary voltage v.sub.1 is denoted as v.sub.1′ (=v.sub.1/a) using a turn ratio a (=n1/n2).

[0036] The secondary side diode rectification circuit is constructed of four diodes U+, U−, V+ and V− with a resonance capacitor C.sub.r connected in parallel to each other, and a smoothing capacitor C2. The capacitance of the resonance capacitor C.sub.r is a substantially large value (e.g., several tens of nF to 1 μF (F, more specifically, 100 nF to 1 μF, typically 500 nF to 1 μF) relative to the parasitic capacitance of the diode (e.g., on the order of several nF to 10 nF). The secondary side diode rectification circuit converts a high-frequency square wave voltage to an output DC voltage V.sub.out.

[0037] Note that by using a diode with a sufficiently large parasitic capacitance (e.g., several tens of nF to 1 μF) (diode designed to have a larger capacity), it is also possible to adopt a configuration in which the resonance capacitor C.sub.r is substantially incorporated in the diode. In this case, the resonance capacitor C.sub.r need not be provided outside the diode and can be configured in a small size.

[0038] The secondary circuit shown in the present embodiment is characterized by the use of resonance between the inductance L and the capacitor C.sub.r, and other configurations can be changed as appropriate depending on the application. Although a DC power supply is connected to the secondary side output, for example, in FIG. 1, a DC load may also be connected. In an application as a charging circuit for the secondary battery, it is denoted as a DC power supply as shown, for example, in FIG. 1, whereas when it is used as a DC-DC converter when power is converted, for example, from overhead rail lines to railroad, it is denoted as a DC load.

[0039] FIG. 2 illustrates a conducting state of each switch of the isolated DC-DC power conversion circuit shown in FIG. 1, and voltage and current waveforms of the high-frequency transformer. The horizontal axis in FIG. 2 represents time. For simplicity of description, FIG. 2 shows a case where a=1, where “a” is assumed to be the turn ratio of the high-frequency transformer and further V.sub.in=V.sub.out assuming that input and output DC voltages are equal. In the primary side H-bridge circuit, by shifting switching phases of R and S phases 180 degrees and energizing each switch with a duty of 50%, a square wave AC voltage having amplitude of the input DC voltage V.sub.in and a frequency f.sub.s (=1/2 T.sub.s; half cycle T.sub.s of the high-frequency waveform) is generated as the primary voltage v.sub.1. In the waveform of the primary voltage v.sub.1 in FIG. 2, periods from <mode 1-1> to <mode 1-4> are shown as operating modes due to changes in the primary voltage v.sub.1. The secondary voltage v.sub.2 is a voltage delayed with respect to the primary voltage v.sub.1. If an excitation current of the high-frequency transformer is ignored assuming that it is sufficiently small compared with the primary and secondary currents, a primary current i.sub.1 and a secondary current i.sub.2 of the high-frequency transformer are equal. Square wave currents shown in FIG. 2 as the primary current i.sub.1 and the secondary current i.sub.2 are obtained. Details of the waveforms will be derived in detail later. Periods from <mode 2-1> to <mode 2-4> are shown as operating modes due to commutation of the secondary side diode rectification circuit together with the waveforms of the primary current i.sub.1 and the secondary current i.sub.2.

[0040] FIG. 3 is a diagram illustrating each commutation operation of the secondary side diode rectification circuit, showing circuit operation in each mode when the diodes U− and V+ are commutated to the diodes U+ and V− respectively in the secondary side diode rectification circuit when the primary voltage is switched from negative to positive by switching of the H-bridge circuit. In <mode 2-1> before commutation in FIG. 3, the primary side switches R− and S+ are conducting, a primary voltage v.sub.1′ becomes an input DC voltage −V.sub.in (=−V.sub.out) and a negative current −I.sub.n flows as the secondary current i.sub.2 since the diodes U− and V+ are conducting. The secondary voltage v.sub.2 becomes an output DC voltage −V.sub.out, and since the primary voltage and the secondary voltage are equal, the secondary current i.sub.2 with the constant value −I.sub.n flows. The voltages of the parallel capacitors of the diodes U− and V+ are zero, and the parallel capacitors of the diodes U+ and V− are charged to the output DC voltage V.sub.out. At time t=t.sub.2 in FIG. 2, when the switch of the H-bridge circuit is switched from R−, S+ to R+, S− and the primary voltage v.sub.1′ is changed from −V.sub.in to V.sub.in, the mode is shifted to <mode 2-2>. Even when the mode is shifted to <mode 2-2> in FIG. 3, the diodes U− and V+ continue conducting due to continuity of the secondary current by the inductance L. A voltage formula of the secondary circuit in <mode 2-2> is given by the following formula.

[00001]$\begin{array}{cc}\begin{array}{cc}{v}_1^{\prime }=L\frac{{\mathrm{di}}_2}{\mathrm{dt}}-V_{\mathrm{out}}& \left(t_2\le t\le t_3\right)\end{array}& \left(1\right)\end{array}$

[0041] Here, by substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out and the initial secondary current value i.sub.2(t.sub.2)=−I.sub.n in <mode 2-2> into formula (1), a secondary current i.sub.2(t) in <mode 2-2> is obtained by the following formula.

[00002]$\begin{array}{cc}\frac{{\mathrm{di}}_2}{\mathrm{dt}}=\frac{2V_{\mathrm{out}}}{L}& \left(2\right)\end{array}$$\begin{array}{cc}{i}_2\left(t\right)=\frac{2V_{\mathrm{out}}}{L}\left(t-t_2\right)-I_n& \left(3\right)\end{array}$

[0042] As shown in FIG. 2, in <mode 2-2>, the secondary current i.sub.2(t) increases toward zero with a constant slope. When the secondary current i.sub.2(t) becomes zero at time t=t.sub.3, <mode 2-2> ends. A period T.sub.2=t.sub.3−t.sub.2 in <mode 2-2> is given by formula (3).

[00003]$\begin{array}{cc}{T}_2=t_3-t_2=\frac{{\mathrm{LI}}_n}{2V_{\mathrm{out}}}& \left(4\right)\end{array}$

[0043] When the secondary current i.sub.2(t.sub.3)=0 at time t=t.sub.3, all the diodes in the secondary circuit becomes non-conductive, and the mode is shifted to <mode 2-3> in FIG. 3. The initial voltages of the parallel capacitors of the diodes U− and V+ at time t=t.sub.3 when <mode 2-3> starts are both zero and the initial voltages of the parallel capacitors of the diodes U+ and V− are both V.sub.out. In <mode 2-3>, a resonance circuit is constructed of an inductor L and four capacitors C.sub.r. From symmetry of the circuit, half of the secondary current, i.sub.2/2, flows through each capacitor. A voltage formula in <mode 2-3> is given by the following formula.

[00004]$\begin{array}{cc}\begin{array}{cc}{v}_1^{\prime }=L\frac{{\mathrm{di}}_2}{\mathrm{dt}}+\frac{2}{C_r}{\int }_{t_3}^t\frac{i_2}{2}\mathrm{dt}-V_{\mathrm{out}}& \left(t_3\le t\le t_4\right)\end{array}& \left(5\right)\end{array}$

[0044] By substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out and the initial secondary current value i.sub.2(t.sub.3)=0 into formula (5) and solving the formula, the secondary current i.sub.2(t) in <mode 2-3> is obtained by the following formula.

[00005]$\begin{array}{cc}\begin{array}{c}2V_{\mathrm{out}}=L\frac{{\mathrm{di}}_2}{\mathrm{dt}}+\frac{1}{C_r}{\int }_{t_3}^t{i}_2\mathrm{dt}\\ i_2\left(t\right)=2V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\sin \frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}\end{array}& \left(6\right)\end{array}$

[0045] As the secondary current i.sub.2(t), a current of resonance angular frequency (o (=2(f.sub.o=1/√(LC.sub.r)) flows. The secondary voltage v.sub.2 is given by the following formula using the secondary current i.sub.2(t) in formula (6).

[00006]$\begin{array}{cc}\begin{array}{c}{v}_2\left(t\right)=v_1^{\prime }\left(t\right)-L\frac{{\mathrm{di}}_2}{\mathrm{dt}}\\ =V_{\mathrm{out}}\left(1-2\cos \frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}\right)\end{array}& \left(7\right)\end{array}$

[0046] The secondary current i.sub.2 and the secondary voltage V in formulas (6) and (7) have sinusoidal waveforms as shown in FIG. 2. When the secondary current i.sub.2 and the secondary voltage v.sub.2 become I.sub.n and V.sub.out respectively, the voltages of the parallel capacitors of the diodes U+ and V− are also both zero, and <mode 2-3> ends at time t=t.sub.4. In FIG. 2, the phase at time t=t.sub.4 is π/2, and amplitude I.sub.n of the secondary current i.sub.2 and the period T.sub.3=t.sub.4−t.sub.3 in <mode 2-3> are given by the following formula from formulas (6) and (7).

[00007]$\begin{array}{cc}{I}_n=2V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}& \left(8\right)\end{array}$$\begin{array}{cc}{T}_3=t_4-t_3=\frac{\pi }{2}\sqrt{{\mathrm{LC}}_r}& \left(9\right)\end{array}$

[0047] The secondary current i.sub.2 in <mode 2-2> in formula (3) and the period T.sub.2 in <mode 2-2> in formula (4) are rewritten as shown in the following formulas by substituting formula (8) into the respective formulas.

[00008]$\begin{array}{cc}{i}_2\left(t\right)=\frac{2V_{\mathrm{out}}}{L}\left(t-t_2-\sqrt{{\mathrm{LC}}_r}\right)& \left(10\right)\end{array}$$\begin{array}{cc}{T}_2=\sqrt{{\mathrm{LC}}_r}& \left(11\right)\end{array}$

[0048] At time t=t.sub.4, when the voltages of the parallel capacitors of the diodes U+ and V− are both zero, the diodes U+ and V− become conductive, and the mode is shifted to <mode 2-4> in FIG. 3. A voltage formula of the secondary circuit in <mode 2-4> is given by the following formula.

[00009]$\begin{array}{cc}\begin{array}{cc}{v}_1^{\prime }=L\frac{{\mathrm{di}}_2}{\mathrm{dt}}+V_{\mathrm{out}}& \left(t_4\le t\right)\end{array}& \left(12\right)\end{array}$

[0049] Here, by substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out and an initial secondary current value i.sub.2(t.sub.4)=I.sub.n in <mode 2-4> into formula (12), the secondary current i.sub.2(t) in <mode 2-4> is obtained by the following formula.

[00010]$\begin{array}{cc}\begin{array}{c}\frac{{\mathrm{di}}_2}{\mathrm{dt}}=0\\ i_2\left(t\right)=\mathrm{In}=2V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\end{array}& \left(13\right)\end{array}$

[0050] As shown in FIG. 2, in <mode 2-4>, the secondary current i.sub.2(t) becomes a constant value. When the H-bridge circuit is switched and the primary voltage is switched from positive to negative, <mode 2-4> ends.

[0051] Each diode is switched from the operation of the secondary circuit in a state in which each parallel capacitor voltage is zero. That is, since no diode recovery loss is generated, no power loss is generated, resulting in extremely high efficiency. The output power Pout can be obtained by the following formula using an output current i.sub.out as average power of the half cycle T.sub.s of the high-frequency transformer.

[00011]$\begin{array}{cc}\begin{array}{c}{P}_{\mathrm{out}}=\frac{1}{T_s}{\int }_{t_2}^{t_2+T_s}{V}_{\mathrm{out}}{i}_{\mathrm{out}}\mathrm{dt}\\ =V_{\mathrm{out}}{I}_n\left(1-\frac{1+\pi }{2T_s}\sqrt{{\mathrm{LC}}_r}\right)\\ =2V_{\mathrm{out}}^2\sqrt{\frac{C_r}{L}}\left(1-\frac{1+\pi }{2T_s}\sqrt{{\mathrm{LC}}_r}\right)\end{array}& \left(14\right)\end{array}$

[0052] Control of the output power Pot can be adjusted by the frequency f.sub.s of the high-frequency transformer. By rewriting the output power P.sub.out in formula (14) using the frequency f.sub.s (=1/2 T.sub.s) and the resonance frequency f.sub.o (=1/(2π√(LC.sub.r))) of the high-frequency transformer, the following formula is obtained.

[00012]$\begin{array}{cc}{P}_{\mathrm{out}}=2V_{\mathrm{out}}^2\sqrt{\frac{C_r}{L}}\left\{1-\left(\frac{1}{2}+\frac{1}{2\pi }\right)\frac{f_s}{f_o}\right\}& \left(15\right)\end{array}$

[0053] FIG. 4 illustrates characteristics of the output power P.sub.out versus a ratio f.sub.s/f.sub.o of the frequency of the high-frequency transformer to a resonance frequency based on formula (14). The resonance frequency f.sub.o is determined by a circuit parameter, is a constant value, and the output power P.sub.out can be reduced by increasing the frequency f.sub.s, of the transformer. In FIG. 4, at the ratio of the frequency of the high-frequency transformer to the resonance frequency (f.sub.s/f.sub.o)=1/4, a rated output P.sub.out is normalized to 1. A maximum frequency (f.sub.s/f.sub.o)max of the high-frequency transformer at which the output power P.sub.out in formula (14) holds corresponds to a case where the period of the current value I.sub.n in the waveform of the secondary current i.sub.2(t) in FIG. 2 becomes zero, and can be obtained by the following formula.

[00013]$\begin{array}{cc}{\left(\frac{f_s}{f_o}\right)}_{\max }=\frac{2\pi \sqrt{{\mathrm{LC}}_r}}{2\left(1+\pi /2\right)\sqrt{{\mathrm{LC}}_r}}=\frac{2\pi }{2+\pi }=1.22& \left(16\right)\end{array}$

[0054] The maximum frequency of the high-frequency transformer becomes (f.sub.s/f.sub.o)max=1.22 and in this case, the output power can be reduced down to 0.23 of the rated output in FIG. 4. If the frequency f.sub.s of the high-frequency transformer is set to a frequency higher than a value determined from the(f.sub.s/f.sub.o)max, formula (14) does not hold, but the output power P.sub.out can further be reduced.

[0055] Next, soft switching commutation of the H-bridge circuit will be described.

[0056] Although it has been described in FIG. 1 that the parallel capacitor C.sub.s of the switching element of the primary side H-bridge circuit is a parasitic capacitance, capacitors may be separately and externally attached in parallel to realize soft switching of the switch. Hereinafter, including a case where capacitors are externally attached in parallel, the parallel capacitance of the switching element will be described as C.sub.s.

[0057] FIG. 5 illustrates operating modes of the primary side H-bridge circuit and the primary voltage waveform v.sub.1 of the high-frequency transformer when the switch R−, S+ is commutated to the switch R+, S− of the circuit.

[0058] In <mode 1-1> before commutation, the switches R− and S+ are both conducting, and a negative input DC voltage −V.sub.in is generated as the primary voltage v.sub.1. As the primary current i.sub.1, a negative constant current −I.sub.n flows through the switches R− and S+. The voltages of the parallel capacitors of the switches R− and S+ are both zero and the voltages of the parallel capacitors of the switches R+ and S− are both charged to the input DC voltage V.sub.in. When the switches R− and S+ are set to non-conducting state, since the parallel capacitor voltages are zero, the switches R− and S+ are subjected to zero voltage switching (ZVS).

[0059] By setting the switches R− and S+ to the non-conducting state, the mode is shifted to <mode 1-2> in FIG. 5. In <mode 1-2>, from the continuity of the load current, the primary current i.sub.1 is kept at the negative current −I.sub.n and flows to the four parallel capacitors Cs. The voltages of the parallel capacitors of the switches R− and S+ increase from zero and the voltages of the parallel capacitors of the switches R+ and S− decrease. Due to the changes in the capacitor voltages, the primary voltage v.sub.1 changes from the negative input DC voltage −V.sub.in to a positive input DC voltage V.sub.in. When the primary voltage v.sub.1 becomes the positive input DC voltage V.sub.in, the parallel capacitor voltages of the switches R+ and S− become both zero and the parallel diodes of the switches R+ and S− are brought into conduction. The conduction of the parallel diodes of the switches R+ and S− causes the mode to be shifted to <mode 1-3>. During the period in <mode 1-3>, a gate signal is given to bring the switches R+ and S− into conduction. Since the parallel diodes are in a conducting state, even if a gate signal is given to the switches, the switches are reverse-biased and are not brought into conduction. As already mentioned, the primary current i.sub.1 increases toward zero with a constant slope. When the primary current i.sub.1 turns positive from negative, the mode is shifted to <mode 1-4>. When the sign of the primary current i.sub.1 changes from negative to positive and the switches R+ and S− are brought into conduction, the parallel capacitor voltages remain zero, making it possible to realize ZVS. Soft switching can also be realized likewise for other switching, making it possible to reduce switching losses.

[0060] As described above, according to the first embodiment, it is possible to obtain an effect of reducing switching losses efficiently with a simple circuit configuration.

[0061] As a further effect, power control on the output side can be easily performed, and in particular, controllability on the low output side improves. As described above, according to formula (14), although the power on the output side can be adjusted by a switching frequency, controllability when the P.sub.out value is equal to or less than 0.23 deteriorates and a slight frequency fluctuation may cause a considerable change in the output. According to the first embodiment, however, it is possible to control the power on the output side regardless of formula (14). As a result, it is also possible to control the power supply to an extremely small level after the charging level of an output power supply target, such as a battery, exceeds a certain value. A specific method thereof will be described in detail in a third embodiment.

Second Embodiment—Circuit Configuration with Primary Side Half Bridge Circuit

[0062] FIG. 6 illustrates a circuit in which the primary side H-bridge circuit in FIG. 1 according to the first embodiment is replaced with a half bridge circuit (1′). An input DC voltage is 2V.sub.in and two capacitors C1 are connected in series to provide a DC neutral point of the input DC voltage 2V.sub.in. The DC voltages of the two capacitors C1 are both V.sub.in. One of the two input terminals of the high-frequency transformer is connected to an R-phase output terminal and the other is connected to the DC neutral point. The half bridge is constructed of two switching elements R+ and R−. Each switching element incorporates an antiparallel diode and a parasitic capacitance of the switching element is C.sub.s.

[0063] The operating waveform of the insulated DC-DC power conversion circuit using the H-bridge circuit shown in FIG. 2 is applicable as it is, as an operating waveform of the circuit using the half bridge circuit in FIG. 6 if the S-phase switching signal is ignored. That is, by bringing the switching element R+ into conduction, the primary voltage v.sub.1 of the high-frequency transformer is connected to the upper capacitor C1 of the input DC voltage and becomes the capacitor voltage V.sub.in. By bringing the switching element R− into conduction, the primary voltage v.sub.1 of the high-frequency transformer is connected to the lower capacitor C1 of the input DC voltage and becomes the negative capacitor voltage −V.sub.in.

[0064] Therefore, as in the case of using the H-bridge circuit, a square wave AC waveform of amplitude V.sub.in can be obtained as the primary voltage v.sub.1. The high-frequency transformer and the secondary circuit in the circuit using the half bridge circuit is the same as the circuit using the H-bridge circuit in FIG. 1, and the respective waveforms of the secondary voltage v.sub.2, the primary current i.sub.1 and the secondary current i.sub.2 in FIG. 2 are obtained. The secondary circuit can operate highly efficiently without diode recovery losses.

[0065] As described in the first embodiment, the control of the output power P.sub.out can be adjusted by the frequency f.sub.s (=1/2 T.sub.s) of the high-frequency transformer according to formula (15). Furthermore, soft switching of the primary side half bridge circuit can also be realized.

[0066] Commutation from the switch R− to the switch R+ in the half bridge circuit in FIG. 6 will be described. While the switch R− is in a conducting state, the primary voltage v.sub.1 is a negative input DC voltage −V.sub.in and a negative current −I.sub.n flows through the switch R− as the primary current i.sub.1. The voltage of the parallel capacitor of the switch R− is zero. When the switch R− is set to non-conducting state, the voltage of the parallel capacitor of the switch R− is zero and ZVS is realized. When the negative current −I.sub.n flows following the primary current i.sub.1, the voltage of the parallel capacitor of the switch R+ decreases from V.sub.in, and when the voltage becomes zero voltage, the parallel diode of the switch R+ becomes conductive. The primary voltage v.sub.1 becomes a positive input DC voltage V.sub.in and the primary current i.sub.1 also increases toward zero from the negative current −I.sub.n. While the primary current i.sub.1 is negative, if a conduction signal is given to the switch R+, the primary current i.sub.1 changes from negative to positive, and even when a current is commutated from the diode to the switch R+, the voltage of the parallel capacitor is zero and ZVS is realized. Therefore, it is possible to realize soft switching in all commutations and reduce switching losses.

[0067] The secondary circuit shown in the present embodiment is the same as the one in the first embodiment and is characterized by the use of resonance between an inductance L and a capacitance C.sub.r. Therefore, other configurations can be changed as appropriate depending on the application. For example, although a DC power supply is connected to the secondary side output in FIG. 6, a DC load may be connected. For example, for an application such as a charging circuit of a secondary battery, it is represented as a DC power supply as shown in FIG. 6, but when it is used as a DC-DC converter, for example, when power is converted, for example, from overhead rail lines to railroad, it is represented as a DC load.

[0068] As described above, a DC-DC power converter can be configured even when a half bridge circuit is used as the primary circuit. According to the second embodiment, the configuration of the primary circuit is simpler than the first embodiment and it is possible to obtain a much smaller or lower-cost DC-DC power converter. Note that control of the power on the output side can be adjusted by switching frequency according to formula (15).

Third Embodiment—Method for Controlling Transmission Power by Controlling Ta

[0069] As described in the first and second embodiments above, power of the secondary circuit can be controlled by changing the switching frequency of the primary circuit according to formula (14) in all the circuit configurations. However, according to the circuit configuration described in the first embodiment, since the period Td during which the primary voltage v.sub.1 is zero can be controlled, the secondary power can be controlled regardless of frequency control.

[0070] In the present embodiment, a power control method realized by controlling the period T.sub.d during which the primary voltage v.sub.1 is zero in the circuit described in the first embodiment will be described.

[0071] (1) Power Reduction Control Method in <Mode 2-2>

[0072] A method for controlling output power P.sub.out by a switching pattern of a primary side H-bridge circuit when the frequency f.sub.s of the high-frequency transformer of the unidirectional insulated DC-DC power conversion circuit in FIG. 1 is a constant value will be described.

[0073] FIG. 2 illustrates the operating waveform at maximum output power, and a square wave AC waveform of amplitude V.sub.in is outputted as the primary voltage v.sub.1. FIG. 7 illustrates the operating waveform in the case where power is slightly reduced to adjust the output power P.sub.out. A basic conception of power reduction is a method of reducing an effective value of the primary voltage v.sub.1 by delaying switching timing of the S-phase switch by a period Td and providing the period T.sub.d during which the voltage is zero in the square wave waveform of the primary voltage v.sub.1. In the operating waveform in FIG. 7, a new mode has only been added to the period T.sub.d during which the primary voltage v.sub.1 is zero and waveforms other than the period T.sub.d are the same as the waveform at the time of maximum output power in FIG. 2. In the operating waveform in FIG. 7, the waveform is separated into two modes assuming that the period T.sub.d during which the primary voltage v.sub.1 is zero is <mode 2-21> and the period during which the primary voltage v.sub.1 is V.sub.in is <mode 2-22>. By substituting a primary voltage v.sub.1′=0, an initial secondary current value i.sub.2(t.sub.2)=−I.sub.n and formula (8) into the secondary circuit voltage formula in <mode 2-2> in formula (1), a secondary current i.sub.2(t) in <mode 2-21> is obtained by the following formula.

[00014]$\begin{array}{cc}\frac{{\mathrm{di}}_2}{\mathrm{dt}}=\frac{V_{\mathrm{out}}}{L}& \left(17\right)\end{array}$$\begin{array}{cc}\begin{array}{cc}{i}_2\left(t\right)=\frac{V_{\mathrm{out}}}{L}\left(t-t_2-2\sqrt{{\mathrm{LC}}_r}\right)& \left(t_2\le t\le t_2+T_d\right)\end{array}& \left(18\right)\end{array}$

[0074] That is, since a slope di.sub.2/dt of the secondary current in <mode 2-21> in formula (17) is ½ of the slope in <mode 2-2> in formula (2), the maximum period T.sub.d in <mode 2-21> is two times the period T.sub.2=√(LC.sub.r) in <mode 2-2>. Therefore, a range of a period T.sub.21=T.sub.d in <mode 2-21> is given by the following formula.

0≤T.sub.21≤2√{square root over (LC.sub.r)}>  (19)

[0075] Here, by substituting time t=t.sub.2+T.sub.d into formula (18), an initial secondary current value i.sub.2(t.sub.2+T.sub.d) in <mode 2-22> is obtained by the following formula.

[00015]$\begin{array}{cc}{i}_2\left(t_2+T_d\right)=\frac{V_{\mathrm{out}}}{L}\left(T_d-2\sqrt{{\mathrm{LC}}_r}\right)& \left(20\right)\end{array}$

[0076] By substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out, the initial secondary current value i.sub.2(t.sub.2+T.sub.d) in formula (20) and formula (8) into the secondary circuit voltage formula in <mode 2-2> in formula (1), a secondary current i.sub.2(t) in <mode 2-22> is obtained by the following formula.

[00016]$\begin{array}{cc}\begin{array}{cc}{i}_2\left(t\right)=\frac{2V_{\mathrm{out}}}{L}\left(t-t_2-\frac{T_d}{2}-\sqrt{{\mathrm{LC}}_r}\right)& \left(t_2+T_d\le t\le t_3\right)\end{array}& \left(21\right)\end{array}$

[0077] At end time t.sub.3 in <mode 2-22>, since the secondary current i.sub.2(t.sub.3)=0 in formula (21), the end time t.sub.3 and period T.sub.22 in <mode 2-22> are obtained by the following formulas.

[00017]$\begin{array}{cc}{t}_3=t_2+\sqrt{{\mathrm{LC}}_r}+\frac{T_d}{2}& \left(22\right)\end{array}$$\begin{array}{cc}{T}_{22}=t_3-\left(t_2+T_d\right)=\sqrt{{\mathrm{LC}}_r}-\frac{T_d}{2}& \left(23\right)\end{array}$

[0078] By calculating the output power P.sub.out based on the derived secondary current waveforms in all modes, the following formulas are obtained and the output power P.sub.out can be controlled by the period T.sub.d during which the primary voltage v.sub.1 is zero.

[00018]$\begin{array}{cc}\begin{array}{c}{P}_{\mathrm{out}}=V_{\mathrm{out}}^2\left\{2\sqrt{\frac{C_r}{L}}\left(1-\frac{1+\pi }{2T_s}\sqrt{{\mathrm{LC}}_r}\right)-\frac{T_d^2}{4{\mathrm{LT}}_s}\right\}\\ =2V_{\mathrm{out}}^2\sqrt{\frac{C_r}{L}}\left(1-\frac{1+\pi }{2T_s}\sqrt{{\mathrm{LC}}_r}-\frac{T_d^2}{8T_s\sqrt{{\mathrm{LC}}_r}}\right)\\ \end{array}& \left(24\right)\end{array}$

[0079] (2) Power Reduction Control Method in <Mode 2-3>

[0080] When the period T.sub.d during which the primary voltage v.sub.1 is zero reaches or exceeds 2 √(LC.sub.r), the primary voltage v.sub.1 is zero until the range of <mode 2-3> in FIG. 7, and the resonance waveform of the secondary current i.sub.2 in formula (6) changes. FIG. 8 illustrates respective waveforms of the secondary voltage v.sub.2, the primary current i.sub.1 and the secondary current i.sub.2 when the period T.sub.d during which the primary voltage v.sub.1 is zero reaches or exceeds 2 (LC.sub.r). The operating waveforms in FIG. 8 are divided, between times t.sub.3 and t.sub.4, into two modes: <mode 2-31> as a period T.sub.31 during which the primary voltage v.sub.1 is zero and <mode 2-32> as a period T.sub.32 during which the primary voltage v.sub.1 is V.sub.in. An absolute value I.sub.m of a current value −I.sub.m of the secondary current i.sub.2 in <mode 2-1> is smaller than I.sub.n(> I.sub.m) in formula (8).

[0081] <Mode 2-1> in FIG. 8 corresponds to the circuit connection in <mode 2-1> before commutation in FIG. 3, the primary switches R− and S+ are brought into conduction, the input DC voltage −V.sub.in is applied as the primary voltage v.sub.1′, and the diodes U− and V+ are brought into conduction and a negative current −I.sub.m flows as the secondary current i.sub.2. At time t=t.sub.2 in FIG. 8, when the switch of the H-bridge circuit is switched from R− to R+ and the primary voltage v.sub.1′ changes from −V.sub.in to 0, the mode is shifted to <mode 2-21>. By substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out and the initial secondary current value i.sub.2(t.sub.2)=−I.sub.m in <mode 2-21> into formula (1), the secondary current i.sub.2(t) in <mode 2-21> is obtained by the following formulas.

[00019]$\begin{array}{cc}\frac{{\mathrm{di}}_2}{\mathrm{dt}}=\frac{V_{\mathrm{out}}}{L}& \left(25\right)\end{array}$$\begin{array}{cc}{i}_2\left(t\right)=\frac{V_{\mathrm{out}}}{L}\left(t-t_2\right)-I_m& \left(26\right)\end{array}$

[0082] As shown in FIG. 8, in <mode 2-21>, the secondary current i.sub.2(t) increases toward zero with a constant slope. When the secondary current i.sub.2(t) becomes zero at time t=t.sub.3, <mode 2-21> ends. The period T.sub.21=t.sub.3−t.sub.2 in <mode 2-21> is given by formula (27).

[00020]$\begin{array}{cc}{T}_{21}=t_3-t_2=\frac{{\mathrm{LI}}_m}{V_{\mathrm{out}}}& \left(27\right)\end{array}$

[0083] When the secondary current i.sub.2(t.sub.3)=0 at time t=t.sub.3, all the diodes in the secondary circuit are placed in a non-conducting state, and the mode is shifted to <mode 2-31> in FIG. 3. At time t=t.sub.3 when <mode 2-31> starts, the initial voltages of the parallel capacitors of the diodes U− and V+ are both zero and the initial voltages of the parallel capacitors of the diodes U+ and V− are both V.sub.out. In <mode 2-3>, a resonance circuit with an inductor L and four capacitors C.sub.r is configured. Due to the symmetry of the circuit, a current i.sub.2/2, half the secondary current, flows to each capacitor and the voltage formula in formula (5) holds. By substituting the primary voltage v.sub.1′=0 and the initial secondary current value i.sub.2(t.sub.3)=0 into formula (5) and solving the formula, the secondary current i.sub.2(t) in <mode 2-31> is obtained by the following formula.

[00021]$\begin{array}{cc}{V}_{\mathrm{out}}=\frac{{\mathrm{di}}_2}{\mathrm{dt}}+\frac{1}{C_r}{\int }_{t_3}^t{i}_2\mathrm{dt}\begin{array}{cc}{i}_2\left(t\right)=V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\sin \frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}& \left(t_3\le t\le t_3+T_{31}\right)\end{array}& \left(28\right)\end{array}$

[0084] The secondary voltage v.sub.2 is obtained by the following formula using the secondary current i.sub.2(t) in formula (28).

[00022]$\begin{array}{cc}{v}_2\left(t\right)=v_1^{\prime }\left(t\right)-L\frac{{\mathrm{di}}_2}{\mathrm{dt}}=V_{\mathrm{out}}\cos \frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}& \left(29\right)\end{array}$

[0085] The secondary current i.sub.2 and the secondary voltage v.sub.2 in formulas (28) and (29) have sinusoidal waveforms as shown in FIG. 8. The secondary voltage v.sub.2 and the secondary voltage v.sub.2 at time t=t.sub.3+T.sub.31 are obtained by the following formula.

[00023]$\begin{array}{cc}{i}_2\left(t_3+T_{31}\right)=V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\sin \frac{T_{31}}{\sqrt{{\mathrm{LC}}_r}}& \left(30\right)\end{array}$$\begin{array}{cc}{v}_2\left(t_3+T_{31}\right)=-V_{\mathrm{out}}\cos \frac{T_{31}}{\sqrt{{\mathrm{LC}}_r}}& \left(31\right)\end{array}$

[0086] When the switch of the H-bridge circuit is switched from S+ to S− at time t=t.sub.3+T.sub.31, the primary voltage v.sub.1=V.sub.in increases stepwise, resulting in a new resonance operation. The voltage formula in <mode 2-32> is given by the following formula.

[00024]$\begin{array}{cc}{v}_1^{\prime }=L\frac{{\mathrm{di}}_2}{\mathrm{dt}}+\frac{2}{C_r}{\int }_{t_3}^t\frac{i_2}{2}\mathrm{dt}-v_2\left(t_3+T_{31}\right)\left(t_3+T_{31}\le t\le t_4\right)& \left(32\right)\end{array}$

[0087] By substituting the primary voltage v.sub.1′=V.sub.in=V.sub.out and the initial secondary current value i.sub.2(t.sub.3+T.sub.31) into formula (32) and solving the formula, the secondary current i.sub.2(t) in <mode 2-32> is obtained by the following formula.

[00025]$\begin{array}{cc}{i}_2\left(t\right)=V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\left\{\sin \frac{i-i_3-T_{31}}{\sqrt{{\mathrm{LC}}_r}}+\sin \left(\frac{t-t_3-T_{31}}{\sqrt{{\mathrm{LC}}_r}}+\frac{T_{31}}{\sqrt{{\mathrm{LC}}_r}}\right)\right\}=2V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\cos \frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}\sin \left(\frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}+\frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}\right)& \left(33\right)\end{array}$

[0088] The term of the first line in formula (33) is a resonance current generated by a change to the primary voltage v.sub.1′=V.sub.out at time t=t.sub.3+T.sub.31 and the term of the second line is the resonance current term from time t=t.sub.3+T.sub.31 or earlier. The third line is a formula expressing these two terms as one resonance current. The secondary voltage v.sub.2 in <mode 2-32> is obtained by the following formula using the secondary current i.sub.2(t) in formula (33).

[00026]$\begin{array}{cc}{v}_2\left(t\right)=v_1^{\prime }\left(t\right)-L\frac{{\mathrm{di}}_2}{\mathrm{dt}}=V_{\mathrm{out}}\left\{1-2\cos \frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}\cos \left(\frac{t-t_3}{\sqrt{{\mathrm{LC}}_r}}+\frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}\right)\right\}& \left(34\right)\end{array}$

[0089] When the secondary voltage v.sub.2(t.sub.4)=V.sub.out at time t=t.sub.4, the voltages of the parallel capacitors of the diodes U+ and V− become zero, the diodes U+ and V− are brought into conduction and <mode 2-32> ends. The second term of formula (34) becomes zero at time t=t.sub.4, and since it is possible to express a period t.sub.4−t.sub.3=T.sub.31+T.sub.32 using the period T.sub.32 in <mode 2-32>, the period T.sub.32 is obtained by the following formula.

[00027]$\begin{array}{cc}\frac{T_{31}+T_{32}}{\sqrt{{\mathrm{LC}}_r}}+\frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}=\frac{\pi }{2}& \left(35\right)\end{array}$$T_{32}=\frac{-3T_{31}+\pi \sqrt{{\mathrm{LC}}_r}}{2}$

[0090] Time t=t.sub.4 can be given by the following formula as a function of the period T.sub.31 using formula (35).

[00028]$\begin{array}{cc}{t}_1=t_3+T_{31}+T_{32}=t_3+\frac{-T_{31}+\pi \sqrt{{\mathrm{LC}}_r}}{2}& \left(36\right)\end{array}$

[0091] By substituting t.sub.4 in formula (36) into formula (33), a secondary current i.sub.2(t.sub.4)=I.sub.m is obtained by the following formula.

[00029]$\begin{array}{cc}{i}_2\left(l_4\right)=I_m=2V_{\mathrm{out}}\sqrt{\frac{C_r}{L}}\cos \frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}& \left(37\right)\end{array}$

[0092] As the period T.sub.31 gets longer, the secondary current value I.sub.m gets smaller, and transmission power can be reduced. Since the secondary current value I.sub.m=0 when the period T.sub.31=π√(LC.sub.r), the period T.sub.31 may be controlled in a range from zero to π√(LC.sub.r).

[0093] During a period t>t.sub.4 in <mode 2-4>, the voltage formula in formula (12) holds and di.sub.2/dt=0 from the primary voltage v.sub.1′=V.sub.in=V.sub.out, and the secondary current i.sub.2(t.sub.4)=I.sub.m of a constant value flows.

[0094] By substituting I.sub.m in formula (37) into formula (27), the period T.sub.21 is obtained by the following formula.

[00030]$\begin{array}{cc}{T}_{21}=2\sqrt{{\mathrm{LC}}_r}\cos \frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}& \left(38\right)\end{array}$

[0095] The period T.sub.d during which the primary voltage is zero is obtained by the following formula using the period T.sub.31.

[00031]$\begin{array}{cc}{T}_d=T_{21}+T_{31}=T_{31}+2\sqrt{{\mathrm{LC}}_r}\cos \frac{T_{31}}{2\sqrt{{\mathrm{LC}}_r}}& \left(39\right)\end{array}$

[0096] A maximum value T.sub.d max of the period during which the primary voltage is zero at the time of a maximum value v.sub.1(LC.sub.r) of the period T.sub.31 is obtained by the following formula.

T.sub.dmax=π√{square root over (LC.sub.r)}  (40)

[0097] From the secondary voltage v.sub.2 and the secondary current i.sub.2 in FIG. 8, the output power P.sub.out of the period T.sub.s is expressed by the following formula.

[00032]$\begin{array}{cc}{P}_{\mathrm{out}}=V_{\mathrm{out}}{I}_m\left(1-\frac{T_{31}+T_{32}+T_{21}/2}{T_s}\right)& \left(41\right)\end{array}$

[0098] By substituting I.sub.m in formula (37), T.sub.32 in formula (35) and T.sub.21 in formula (38) into formula (41), the output power P.sub.out can be expressed by the following formula.

[00033]$\begin{array}{cc}{P}_{\mathrm{out}}=2V\text{?}\sqrt{\frac{C_r}{L}}\text{?}\frac{\text{?}}{2\sqrt{{\mathrm{LC}}_r}}[1-\frac{1}{\text{?}}\text{?}+\sqrt{{\mathrm{LC}}_r}\left(\pi +2\cos \frac{\text{?}}{2\sqrt{{\mathrm{LC}}_r}}\right)\}]& \left(42\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0099] FIG. 9 illustrates the output power P.sub.out in formula (42) versus the period T.sub.d during which the primary voltage in formula (39) is zero. FIG. 9 shows a case where the ratio of the frequency of the high-frequency transformer to the resonance frequency: f.sub.s/f.sub.o=π√(LC.sub.r)/T.sub.s=¼, where T.sub.s=4π√(LC.sub.r). As the period T.sub.d during which the primary voltage is zero increases, the secondary current value I.sub.m decreases, and the output power P.sub.out also decreases. Therefore, the output power P.sub.out can be controlled by the period T.sub.d during which the primary voltage is zero.

[0100] Although a case has been described above where the turn ratio of the high-frequency transformer a=1, and further, input and output DC voltages are equal, V.sub.in=V.sub.out, similar operating waveforms can be obtained also when input and output DC voltages have a relationship of V.sub.in/a=V.sub.out. I.sub.n the case where input and output DC voltages have a relationship of V.sub.in/a=V.sub.out, there may be a case where, when the secondary current waveform has a constant value according to the above description, an error may occur: a slope is generated in the secondary current waveform due to a difference between the primary and secondary voltages, but the aforementioned basic functions can be obtained likewise.

Fourth Embodiment—Output Power Control and Separation of Primary Circuit from Secondary Circuit

[0101] I.sub.n the circuit configurations of the present disclosure in FIG. 1 and FIG. 6, since both secondary circuits are constructed of passive elements, the secondary circuits need not be controlled. Therefore, it is possible to detect the DC voltage V.sub.in and the primary current i.sub.1 of the primary circuit and control the output power P.sub.out by the frequency f.sub.s of the primary circuit or the zero-voltage period T.sub.d. Furthermore, the primary circuit and the secondary circuit can be physically separated if the primary and secondary circuits are made separable by the primary and secondary wiring cores of the high-frequency transformer. The primary circuit and the secondary circuit can be used in combination only for power transmission.

[0102] For example, power transmission (charging) is possible by placing the primary circuit, which is the power supply side, on the ground side and the secondary circuit on the vehicle side and bringing the primary and secondary iron cores of the high-frequency transformer closer to each other only when transmitting power (charging the vehicle). Except during power transmission, the cores of the transformer are physically separated (made independent), whereas during power transmission (charging), the primary and secondary cores can be coupled by an electromagnetic power acting between the cores and thus power transmission is possible. Thus, the present disclosure is also applicable to such non-radiating coupled magnetic field contactless power transmission.

INDUSTRIAL APPLICABILITY

[0103] The power converter according to the present disclosure can be widely used in all product areas such as secondary battery chargers, railroad and other industrial equipment depending on power to be transmitted, providing a wide range of applications and extremely large industrial applicability.

REFERENCE SIGNS LIST

[0104] 10 power converter [0105] 1 primary circuit (H-bridge circuit) [0106] 1′ primary circuit (half bridge circuit) [0107] 2 secondary circuit [0108] C1 capacitor [0109] C2 (smoothing) capacitor [0110] C.sub.r resonance capacitor [0111] C.sub.s parasitic capacitance [0112] U+, U−, V+, V− diode [0113] R+, R−, S+, S− switching element [0114] Tr transformer [0115] L inductance