DETERMINING INITIAL TRANSMISSION PHASE OFFSET IN AN NFC DEVICE

20220407565 · 2022-12-22

    Inventors

    Cpc classification

    International classification

    Abstract

    There is described a method of determining an initial transmission phase offset in an NFC device configured to operate in NFC card mode only, wherein the NFC device comprises an NFC chip and a matching circuit. The method comprises: determining an initial RF matching resonance frequency of the NFC device utilizing an internal oscillator of the NFC chip; reading correction data from a non-volatile memory of the NFC chip, the correction data being indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency; determining a corrected RF matching resonance frequency of the NFC device based on the initial RF matching resonance frequency and the correction data; and determining the initial transmission phase offset based on the corrected RF matching resonance frequency. Furthermore, a device and a method of manufacturing an NFC device are described.

    Claims

    1-15. (canceled)

    16. A method of determining an initial transmission phase offset in an NFC device configured to operate in NFC card mode only, wherein the NFC device comprises an NFC chip and a matching circuit, the method comprising determining an initial RF matching resonance frequency of the NFC device utilizing an internal oscillator of the NFC chip; reading correction data from a non-volatile memory of the NFC chip, the correction data being indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency; determining a corrected RF matching resonance frequency of the NFC device based on the initial RF matching resonance frequency and the correction data; and determining the initial transmission phase offset based on the corrected RF matching resonance frequency.

    17. The method according to claim 16, wherein the correction data comprises a first correction factor indicative of a frequency offset associated with a silicon process used to manufacture the NFC chip, and wherein determining the corrected RF matching frequency comprises applying the first correction factor to the initial RF matching frequency.

    18. The method according to claim 16, wherein the correction data comprises a second correction factor indicative of a frequency offset associated with an operating voltage of the NFC chip, and wherein determining the corrected RF matching frequency comprises applying the second correction factor to the initial RF matching frequency.

    19. The method according to claim 18, wherein the correction data further comprises a reference operating voltage, the method further comprises measuring an actual operating voltage of the NFC chip, and determining the corrected RF matching frequency is further based on a difference between the measured actual operating voltage of the NFC chip and the reference operating voltage.

    20. The method according to claim 16, wherein the correction data comprises a third correction factor indicative of a frequency offset associated with an operating temperature of the NFC chip, and wherein determining the corrected RF matching frequency comprises applying the third correction factor to the initial RF matching frequency.

    21. The method according to claim 20, wherein the correction data further comprises a reference operating temperature, the method further comprises measuring an actual operating temperature of the NFC chip, and determining the corrected RF matching frequency is further based on a difference between the measured actual operating temperature of the NFC chip and the reference operating temperature.

    22. The method according to claim 17, wherein the correction data further comprises a second correction factor indicative of a frequency offset associated with an operating voltage of the NFC chip, and wherein determining the corrected RF matching frequency comprises applying the second correction factor to the initial RF matching frequency, wherein the correction data further comprises a reference operating voltage, the method further comprises measuring an actual operating voltage of the NFC chip, and determining the corrected RF matching frequency is further based on a difference between the measured actual operating voltage of the NFC chip and the reference operating voltage, wherein the correction data further comprises a third correction factor indicative of a frequency offset associated with an operating temperature of the NFC chip, and wherein determining the corrected RF matching frequency comprises applying the third correction factor to the initial RF matching frequency, wherein the correction data further comprises a reference operating temperature, the method further comprises measuring an actual operating temperature of the NFC chip, and determining the corrected RF matching frequency is further based on a difference between the measured actual operating temperature of the NFC chip and the reference operating temperature, and wherein the corrected RF matching frequency is determined by adding (i) the initial RF matching frequency multiplied with the first correction factor, (ii) the initial RF matching frequency multiplied with the second correction factor and multiplied with the difference between the actual operating voltage of the NFC chip and the reference operating voltage, and (iii) the initial RF matching frequency multiplied with the third correction factor and multiplied with the difference between the actual operating temperature of the NFC chip and the reference operating temperature.

    23. The method according to claim 20, further comprising operating the NFC chip for a predetermined period of time in order to provide a stable operating temperature prior to determining the initial RF matching resonance frequency and measuring the actual operating temperature.

    24. The method according to claim 16, wherein the correction data is determined and written into the non-volatile memory during a silicon production test procedure.

    25. A device configured to operate in NFC card mode only, the device comprising: a matching circuit; and an NFC chip coupled to the matching circuit, the NCF chip comprising: an internal oscillator; a non-volatile memory storing correction data indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency; and an NFC processing unit, wherein the NFC processing unit is configured to: determine an initial RF matching resonance frequency of the NFC device utilizing the internal oscillator; read correction data from the non-volatile memory; determine a corrected RF matching resonance frequency of the NFC device based on the initial RF matching resonance frequency and the correction data; and determine an initial transmission phase offset based on the corrected RF matching resonance frequency.

    26. The device according to claim 25, wherein the correction data comprises a first correction factor indicative of a frequency offset associated with a silicon process used to manufacture the NFC chip, and wherein the NFC processing unit is further configured to determine the corrected RF matching frequency by applying the first correction factor to the initial RF matching frequency.

    27. The device according to claim 25, wherein the correction data comprises at least one of a second correction factor indicative of a frequency offset associated with an operating voltage of the NFC chip, and a reference operating voltage, the device further comprising a voltage sensor configured to measure an actual operating voltage of the NFC chip, and wherein the NFC processing unit is further configured to determine the corrected RF matching frequency based on at least one of the second correction factor, the reference operating voltage and the actual operating voltage measured by the voltage sensor.

    28. The device according to claim 25, wherein the correction data comprises at least one of a third correction factor indicative of a frequency offset associated with an operating temperature of the NFC chip, and a reference operating temperature, the device further comprising a temperature sensor configured to measure an actual operating temperature of the NFC chip, and wherein the NFC processing unit is further configured to determine the corrected RF matching frequency based on at least one of the third correction factor, the reference operating temperature and the actual operating temperature measured by the voltage sensor.

    29. The device according to claim 26, wherein the NFC processing unit is configured to determine the corrected RF matching frequency by adding the initial RF matching frequency multiplied with the first correction factor, the initial RF matching frequency multiplied with the second correction factor and multiplied with the difference between the actual operating voltage of the NFC chip and the reference operating voltage, and the initial RF matching frequency multiplied with the third correction factor and multiplied with the difference between the actual operating temperature of the NFC chip and the reference operating temperature.

    30. The device according to claim 28, wherein the NFC processing unit is configured to operate the NFC chip for a predetermined period of time in order to provide a stable operating temperature prior to determining the initial RF matching resonance frequency and measuring the actual operating temperature.

    31. The device according to claim 25, wherein the correction data is determined and written into the non-volatile memory during a silicon production test procedure.

    32. A method of manufacturing an NFC device configured to operate in NFC card mode only, the method comprising: manufacturing an NFC chip, the NFC chip comprising an internal oscillator, a non-volatile memory, and an NFC processing unit; determining, during a silicon production test procedure, correction data indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency; writing the determined correction data into the non-volatile memory; mounting the NFC chip in the NFC device and connecting the NFC chip to a matching circuit; determining an initial RF matching resonance frequency of the NFC device utilizing the internal oscillator of the NFC chip; reading the correction data from the non-volatile memory of the NFC chip; determining a corrected RF matching resonance frequency of the NFC device based on the initial RF matching resonance frequency and the correction data; and determining the initial transmission phase offset based on the corrected RF matching resonance frequency.

    33. The method according to claim 32, wherein the correction data includes at least one parameter selected from the group comprising: a first correction factor indicative of a frequency offset associated with a silicon process used to manufacture the NFC chip, a second correction factor indicative of a frequency offset associated with an operating voltage of the NFC chip, a reference operating voltage of the NFC chip, a third correction factor indicative of a frequency offset associated with an operating temperature of the NFC chip, and a reference operating temperature of the NFC chip.

    34. The method according to claim 32, further comprising measuring at least one of an actual operating voltage of the NFC chip and an actual operating temperature of the NFC chip.

    Description

    BRIEF DESCRIPTION OF THE DRAWING

    [0055] FIG. 1 shows a circuit diagram of an NFC device according to an exemplary embodiment of the present disclosure.

    [0056] FIG. 2 illustrates a method of determining an initial transmission phase offset in an NFC device in accordance with an exemplary embodiment of the present disclosure.

    [0057] FIG. 3 shows a relation between initial and corrected resonance frequency in accordance with exemplary embodiments of the present disclosure.

    [0058] FIG. 4 shows a wearable device incorporating an NFC device according to an exemplary embodiment of the present disclosure.

    [0059] FIG. 5 shows a block diagram of a method of manufacturing an NFC device in accordance with an exemplary embodiment of the present disclosure.

    DETAILED DESCRIPTION

    [0060] The illustration in the drawing is schematic. It is noted that in different figures, similar or identical elements are provided with the same reference signs or with reference signs, which differ only within the first digit.

    [0061] FIG. 1 shows a circuit diagram of an NFC device 100 according to an exemplary embodiment of the present disclosure. The device 100 comprises an NFC chip 110 (also referred to as NFC controller) coupled to a matching circuit 120 and an NFC antenna 130. The NFC chip 110 comprises an internal oscillator 111, a non-volatile memory 112, an NFC processing unit (CPU) 113, a multiplexer, a phase locked loop (PLL) 116, an RF modem 117, and one or more sensors 118. The internal oscillator 111 is coupled to provide an input frequency for the PLL 116 through multiplexer 116 during a self-phase compensation process as described in U.S. patent Ser. No. 10/237,000 B1. In this process, which is performed in a production environment, e.g., during testing of a product including the NFC device 100, a resonance frequency of the NFC device is determined by operating the RF modem 117 with a frequency sweep around the nominal operating frequency, e.g., 13.56 MHz. The initial transmission phase offset can then be determined from a mapping with the resonance frequency. For further details of this process, reference is made to aforementioned U.S. patent Ser. No. 10/237,000 B1, which is incorporated herein in its entirety by reference.

    [0062] Different from prior art devices, the NFC chip 110 does not comprise or have access to a high-precision frequency source, such as a crystal present in devices capable of operating in reader mode. The lacking high-precision frequency source is illustrated by the cross on frequency input line 115. This is only for purposes of illustration—the line 115 will not be used in actual implementations of the NFC chip 110 as described herein. Due to the limited precision of the frequency provided by internal oscillator 111, the determined resonance frequency will deviate from the actual resonance frequency. Hence, an initial transmission phase offset determined on the basis of this resonance frequency would not be able to meet the requirements in terms of precision.

    [0063] To overcome this problem, correction data stored in the non-volatile memory 112 is used to correct the resonance frequency before determination of the initial transmission phase offset. The correction data is generally indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency, and may in particular involve one or more of the following: (i) a first correction factor indicative of a frequency offset associated with a silicon process used to manufacture the NFC chip; (ii) a second correction factor indicative of a frequency offset associated with an operating voltage of the NFC chip; (iii) a reference operating voltage; (iv) a third correction factor indicative of a frequency offset associated with an operating temperature of the NFC chip; and (v) a reference operating temperature. The correction data is obtained (by corresponding measurements) during a silicon production test procedure applied to the NFC chip 110 and stored into the non-volatile memory 112. In other words, the correction data is obtained prior to assembly of the device 100, in particular prior to connection with the matching circuit 120, power supply (not shown), etc.

    [0064] In order to use the correction data to correct the determined (initial value of the) resonance frequency, the sensors 118 are configured to provide relevant information on actual operating voltage and actual operating temperature to the CPU 113.

    [0065] Although the NFC device 100 is designed for use in systems that only need NFC card mode, it may of course also be implemented in systems where an NFC reader mode is provided by another (separate) NFC controller.

    [0066] FIG. 2 illustrates a method of determining an initial transmission phase offset in an NFC device, such as NFC device 100 shown in FIG. 1 and discussed above, in accordance with an exemplary embodiment of the present disclosure. The various steps of the method as performed over time t are shown in the lower part 201 of FIG. 2. The corresponding operation of the NFC chip 110, in particular the RF modem 117, is shown in the upper part 202 of FIG. 2.

    [0067] The method begins at 240 with an initialization of the NFC device in order to prepare it for the actual measurements. The initialization 240 may involve turning on the NFC device 100 and, as an optional measure, operating the RF modem for a predetermined period of time in order to pre-heat the NFC chip 110 to a stable operating temperature. The latter is indicated at 241. If applicable, the actual operating temperature and/or actual operating voltage are also measured by sensors 118 as part of the initialization 240. Then, data collection 242 is performed by operating the PLL 116 to provide a frequency sweep 243 and measuring the resulting receiver signal as described in detail in U.S. patent Ser. No. 10/237,000 B1. At 244, the initial resonance frequency f.sub.ini is calculated or determined based on the collected data 242. Then, at 246, a corrected resonance frequency f.sub.cor is calculated or determined based on the correction data read from the non-volatile memory 112 and, if applicable, the measurement values from the sensors 118. As an example, a linear correction of the measured initial resonance frequency may be applied as follows:


    f.sub.cor=(α.sub.P+(α.sub.V−1).Math.(V.sub.meas−V.sub.ref)+(α.sub.T−1).Math.(T.sub.meas−T.sub.ref)).Math.f.sub.ini

    [0068] In the above formula, α.sub.P is the first correction factor and refers to the relative deviation that can be contributed to silicon process, α.sub.V is the second correction factor and refers to the relative deviation that can be contributed to operating voltage, α.sub.T is the third correction factor and refers to the relative deviation that can be contributed to the operating temperature, V.sub.meas is the measured actual operating voltage, V.sub.ref is the reference operating voltage comprised in the correction data, T.sub.meas is the measured actual operating temperature, and T.sub.ref is the reference operating temperature comprised in the correction data.

    [0069] Finally, at 248, the initial transmission phase offset of the NFC device 100 is determined on the basis of the corrected resonance frequency. The initial transmission phase offset is then stored in the configuration data of the NFC device 100 for future use as known in the art.

    [0070] FIG. 3 shows a relation 303 between initial and corrected resonance frequency in accordance with exemplary embodiments of the present disclosure. More specifically, FIG. 3 shows the measured signal amplitude A at various frequencies during the data collection 242 and frequency sweep 243 discussed above in conjunction with FIG. 2. As shown, the PLL 116 is controlled to provide a frequency sweep from a minimum nominal frequency value f.sub.MIN to a maximum nominal frequency value f.sub.MAX utilizing the internal oscillator 111 as reference frequency. Due to imprecision of the internal oscillator 111 frequency, the frequency sweep is displaced, as shown in the lower part of FIG. 3. The correction discussed above remedies this deviation by correction the measured initial resonance frequency f.sub.ini to f.sub.cor.

    [0071] FIG. 4 shows a wearable device in the form of a smart watch 404 incorporating an NFC device 400 according to an exemplary embodiment of the present disclosure, in particular NFC device 100 shown in FIG. 1. The NFC device 400 comprises NFC controller 410, matching circuit 420, and NFC antenna 430. Furthermore, the NFC device 400 comprises a power input 406 for receiving power from the wearable device 404, and a host interface 407 for exchanging data with the wearable device 404.

    [0072] FIG. 5 shows a block diagram of a method 505 of manufacturing an NFC device, such as NFC device 100 or 400, in accordance with an exemplary embodiment of the present disclosure. The method 505 begins at 550 with manufacturing an NFC chip 110. The NFC chip comprises an internal oscillator 111, a non-volatile memory 112, and an NFC processing unit 113. Then, at 552, the method continues by determining, during a silicon production test procedure, correction data indicative of a frequency offset of the internal oscillator relative to a nominal oscillator frequency. These correction data may correspond to the correction data discussed above. At 554, the method continues by writing the determined correction data into the non-volatile memory 112 of the NFC chip 110. The method further continues, at 556, by mounting the NFC chip 110 in the NFC device 100 and connecting the NFC chip 110 to a matching circuit 120. At 558, an initial RF matching resonance frequency f.sub.ini of the NFC device 100 is determined utilizing the internal oscillator 111 of the NFC chip 110. The method 505 then continues at 560 by reading the correction data from the non-volatile memory 112 of the NFC chip 110, and at 562 by determining a corrected RF matching resonance frequency f.sub.cor of the NFC device 100 based on the initial RF matching resonance frequency f.sub.ini and the correction data. Finally, at 564, the method is concluded by determining the initial transmission phase offset based on the corrected RF matching resonance frequency f.sub.cor.

    [0073] It should be noted that the frequency correction described above may also be used to perform other kinds of basic RF testing during production where a frequency close to 13.56 MHz is needed. For example, the internal oscillator (with frequency correction as described herein) may be used as an input to a PLL circuit in order to generate an RF frequency close to 13.56 MHz. Then, the RF modem is activated and internal sensors of the NFC IC perform measurements to detect if matching circuit and antenna are correctly connected. In this way, a simple detection of bad component assembly can be performed.

    [0074] It is noted that, unless otherwise indicated, the use of terms such as “upper”, “lower”, “left”, and “right” refers solely to the orientation of the corresponding drawing.

    [0075] It is noted that the term “comprising” does not exclude other elements or steps and that the use of the articles “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.