ACTIVE IMPEDANCE CONTROL

Abstract

A resonant inductive power transfer circuit has a power converter to supply to a load, and the converter is concurrently controlled to create a controlled reactance that substantially compensates for variability in the coupling with the another resonant inductive power transfer circuit and/or changes in the load supplied by the power converter.

Claims

1. A method of controlling a wireless power transfer circuit comprising a compensation circuit and a controllable power converter connected to the compensation circuit, the method comprising: switching the controllable power converter to provide a controlled reactance, which controlled reactance in combination with the reactance of the compensation network substantially compensates for variations in reactance seen at an input to the wireless power transfer circuit.

2. The method of claim 1 wherein the wireless power transfer circuit comprises a tuned wireless power transfer circuit, and the method further comprises operating the tuned wireless power transfer circuit to receive or transfer power wirelessly at a frequency that is not the tuned frequency of the tuned wireless power transfer circuit.

3. The method of claim 1 further comprising switching the controllable power converter to provide a controlled reactance to compensate for variations in reactance seen at an input to the wireless power transfer circuit while the wireless power transfer circuit is receiving power wirelessly from, or transferring power wirelessly to, another wireless power transfer circuit.

4. The method of claim 1 further comprising switching the controllable power converter to provide a controlled resistance.

5. The method of claim 1 further comprising switching the controllable power converter to at least one of minimize or cancel an impedance seen at an input to the wireless power transfer circuit.

6. The method of claim 1 further comprising switching the controllable power converter to control an angle between the AC voltage across the converter and the AC current into or out of the converter.

7. (canceled)

8. (canceled)

9. The method of claim 1 further comprising monitoring an output voltage or current of the wireless power transfer circuit and switching the controllable power converter to control the output voltage or current.

10. (canceled)

11. (canceled)

12. The method of claim 1 further comprising switching the controllable power converter to control a phase angle of the controllable power converter over a phase angle range to thereby provide a range of controlled reactance to compensate for a range of variations in reactance seen at the input to the wireless power transfer circuit.

13. The method of claim 12 further comprising switching the controllable power converter such that the reactance seen at the input to the wireless power transfer circuit is minimally inductive.

14. (canceled)

15. (canceled)

16. The method of claim 1 further comprising switching the controllable power converter to compensate for variations in the level of charge of a battery that is charged from the output.

17. (canceled)

18. A wireless power transfer circuit comprising: a compensation network; a controllable power converter connected to the compensation network, the controllable power converter being configured to supply a load and to provide a controlled reactance, which controlled reactance in combination with the reactance of the compensation network substantially compensates for variations in reactance seen at an input to the wireless power transfer circuit.

19. A wireless power transfer circuit as claimed in claim 18 wherein the compensation network comprises a first sub-network and a second sub-network, the first sub-network comprising a power transfer coil, and wherein the reactance of the first sub-network is substantially cancelled by the combined reactance of the second sub-network and the controlled reactance of the controllable power converter.

20. (canceled)

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. A wireless power transfer circuit as claimed in claim 18 wherein the controlled power converter is configured to control the phase angle to provide a range of controlled reactance.

26. A wireless power transfer circuit as claimed in claim 18 wherein the controlled power converter comprises one or more switches which are opened or closed to control the phase angle.

27. A wireless power transfer circuit as claimed in claim 19 wherein the first sub-network comprises a first branch of the compensation network and the second sub-network comprises a second branch of the compensation network.

28-37. (canceled)

38. A method comprising: a resonant inductive power pickup receiving power wirelessly from an inductive power primary, operating a power converter to rectify power received from the inductive power primary for supply to a load that is connected to the resonant inductive power pickup, and concurrently controlling the power converter to create a controlled reactance that substantially compensates for variability in the coupling with the inductive power transfer primary and/or changes in the load supplied by the power converter.

39. (canceled)

40. (canceled)

41. The method of claim 38, wherein the method comprises dynamically controlling a phase angle between a voltage across the converter and a current through the converter, concurrently with rectifying power for supply to the load, to adapt to changes in the load seen by the resonant inductive power pickup, or to create a controlled reactance that substantially compensates for variability in the coupling with the inductive power transfer primary and changes in the load supplied by the power converter.

42. (canceled)

43. (canceled)

44. The method of claim 38, wherein the method comprises controlling the power converter to concurrently regulate the power supplied to the load and control an impedance reflected, by the resonant inductive power pickup, onto the inductive power transfer primary.

45. The method of claim 44, wherein the method comprises controlling the power supplied to the load to regulate the charge in a battery connected to the resonant inductive power pickup.

46. The method of claim 44, wherein the method comprises controlling the power converter to substantially eliminate a reactive component of the reflected impedance.

47-51. (canceled)

Description

DRAWING DESCRIPTION

[0090] Examples or embodiments are described below with reference to the drawings in which:

[0091] FIG. 1 shows a schematic diagram of an IPT system;

[0092] FIG. 2 shows an IPT system pick-up having a controlled power converter with one switch;

[0093] FIG. 3 shows an IPT system pick-up having a controlled power converter with 2 switches;

[0094] FIG. 4 shows an IPT system pick-up having a controlled power converter with 4 switches;

[0095] FIG. 5 shows an IPT system pick-up having an Active Compression Network Using a generic power converter arrangement;

[0096] FIG. 6 shows an equivalent circuit for the circuits of FIGS. 2-5;

[0097] FIG. 7A shows exemplary waveforms for the circuit of FIG. 2 above;

[0098] FIG. 7B shows exemplary waveforms for the circuit of FIG. 3 above;

[0099] FIG. 8 shows another equivalent circuit for the circuits of FIGS. 2-6;

[0100] FIG. 9 shows an IPT system pick-up having an active impedance control topology;

[0101] FIG. 10 shows an IPT system primary having an active impedance control topology;

[0102] FIG. 11 shows an active impedance control topology in generic form;

[0103] FIG. 12 is an active impedance control equivalent circuit;

[0104] FIG. 13 shows a pick-up circuit which may be operated to provide a controlled impedance.

[0105] FIG. 14 shows voltage and current waveforms for the controlled power converter of FIG. 13;

[0106] FIG. 15 shows another equivalent circuit for the circuit of FIG. 13;

[0107] FIG. 16A shows a graph of the real component of impedance Zac vs. ψ & ϕ with Vout=350 V & Pout=7700 kW;

[0108] FIG. 16B shows the imaginary (reactive) component of impedance Zac vs. ψ & ϕ with Vout=350 V & Pout=7700 kW;

[0109] FIG. 17A shows the real component of impedance Zs vs. ψ with ϕ=π, Vout=350 V & Pout=7700 kW;

[0110] FIG. 17B shows the imaginary component of impedance Zs vs. ψ with ϕ=π, Vout=350 V & Pout=7700 kW;

[0111] FIG. 18A shows simulated waveforms at operating point A of FIGS. 17A and 17B;

[0112] FIG. 18B shows simulated waveforms at operating point F of FIGS. 17A and 17B.

DETAILED DESCRIPTION

[0113] This document discloses techniques that can be used to actively control the effective impedance of a WPT circuit, such as a primary or secondary power transfer circuit, or system in order to regulate power flow. These techniques include tuning the primary and/or pick-up compensation networks to facilitate active impedance matching, without significantly impacting the tuning of the system while operating at a fixed frequency. The phase of the voltage produced by the controlled power converter with respect to the current through the power converter (i.e. the power converter phase angle) is adjusted to create a controllable impedance, and in particular a controllable reactance. This controllable impedance, together with an appropriately tuned compensation network, allows control of the power flow while operating at a fixed frequency and without significantly impacting the tuning of the system. The new technique not only removes a conversion stage, but also can significantly improve efficiency by lowering conduction losses in the power converter and also facilitating soft-switching.

[0114] The examples provided in this disclosure are largely directed to implementing a method and system for active impedance control implemented via a pick-up or secondary circuit of a wireless power transfer system. However, it will be understood by a person of ordinary skill in the art that the method or system may equally be performed on a primary circuit of a WPT/IPT system, or across both primary and secondary circuits.

[0115] As described above, with prior art circuits, power factor is an issue. With the active impedance control of the present disclosure, power factor issues are addressed since impedance, specifically reactance, compensation allows a predominantly or solely resistive load to be seen looking into the circuit, so the power factor is essential unitary as the voltage and current appear, or are, in phase.

[0116] A typical WPT/IPT system is shown in FIG. 1, generally referenced 1, in which the primary circuit 2 has a power converter 3 connected between a DC source (or load) Vin and a compensation network 4 which includes a power transfer coil Lpt. Similarly, the pick-up or secondary circuit 5 has a compensation network 6 including a power transfer coil Lst, and a power converter 7 which is also connected to a load (or source) Vout.

[0117] This disclosure presents a number of illustrative configurations for circuits that include compensation networks and controlled power converters which allow control of the circuit impedance. FIGS. 2-5 show circuits in which the controlled power converter has a different configuration: one with only one diode replaced with a switch as in FIG. 2; one with two diodes replaced with switches as in FIG. 1; and one with all four diodes replaced as in FIG. 4. Alternatively, any other power converter can be used, as shown in FIG. 5. Therefore, reference to a controlled power converter in this document may include a number of separate controllable converters.

[0118] A controlled power converter, in this document, includes a switch converter that can be controlled, such as a controlled rectifier. A controlled power converter also includes a half or full bridge converter, as well as any other topologies referred to or disclosed herein.

[0119] In FIG. 2, a pick-up (or secondary) WPT circuit is shown, generally referenced 10. Vsr represents the voltage induced in power transfer coil Lst by a time varying magnetic field, generated from a primary WPT circuit for example. Lst, Csi, Cst and Xtmn form a known LCL topology compensation network. First branch 14 of the network is predominantly or entirely inductive, second branch 16 is predominantly or entirely capacitive and third branch 18 is predominantly or entirely inductive. In the example shown, branch 18 may comprise a TMN, however in other embodiments it may simply comprise an inductor, or an inductor and series connected capacitor for example. The compensation network has a first loop comprising first branch 14 and second branch 16. It has a second loop comprising second branch 16, third branch 18 and the components connected to that branch including the controlled power converter.

[0120] In prior art topologies, the compensation network 12 is typically connected to a power converter such as a rectifier, which may be controlled to provide Vout. However, in this example the output of the LCL compensation network is connected to power converters 30 and 32 via Lzc and Czc. It will be seen that the topology in this example, and in other examples such as FIGS. 2-4, provides for electrical energy from compensation network 2 to be supplied to the load R.sub.LDC (including DC filter capacitor C.sub.DC) through:

a) a first output branch 24 comprising L.sub.zc and controlled power converter 30; and
b) a second output branch 26 comprising C.sub.zc and controlled power converter 32.

[0121] Branches 14 and 16 are provided in parallel with each other. Inductance L.sub.zc is implemented in this example using two discrete inductors which each have an inductance of 0.5L.sub.zc. The series connection of the two inductors presents a total inductance of L.sub.zc. Similarly, Capacitance C.sub.zc is implemented in this example using two discrete capacitors which each have a capacitance of 2Czc. The series connection of the two capacitors presents a total capacitance of C.sub.zc.

[0122] The rectifiers 30 and 32 are controlled to provide both the controlled DC output Vout, and the impedance of the circuit by actively controlling the branches 24 and 26.

[0123] It will be seen that the circuits of FIGS. 2-4 may be expressed by the equivalent circuit shown in FIG. 5 in which the power converters are generally referenced 50. The different configurations of FIGS. 2-4 offer varied cost, control complexity, control freedom and effectiveness. The duty cycle of the power converter switches can be controlled to vary Lzc, Czc, RLac and RCac in order to regulate the power flow. The phase angle of the or each controlled power converter can be controlled to regulate the impedance of the impedance of the circuit as it appears at Vsr, i.e. as it appears to a primary circuit which is wirelessly supplying power to the circuits of FIGS. 2-4.

[0124] Several exemplary waveforms for the rectifiers that comprise the controlled power converters 30 and 32 of FIG. 1 are shown in FIG. 7A. Each rectifier comprises a bridge circuit. The waveforms demonstrate how the rectifiers can be controlled to regulate the reflected impedance from the pick-up. In the example shown in FIG. 6A, the switches in each of the rectifiers are operated by a controller 40 (for example a microprocessor) to ensure that turn-on occurs at zero voltage (ZVS) and the Vsi waveform lags the Isi waveform by a controllable amount (regulated by the duty cycle of the switches). The controller 40 is shown in FIG. 1, and may comprise inputs 42 and 44 such as Vout and/or Iout and outputs 46 which provide signals to control the switches D.

[0125] The first waveform, shown at the top of FIG. 7A, represents the current (Isi) flowing through the rectifiers. The next waveform represents the voltage (Vsa) across the return diode on the left leg of the bridge. The middle waveform represents the voltage across the switch D (that replaces the return diode on the right leg of the bridge). The fourth waveform represents the conducting state of the switch (D). And the final waveform, shown at the bottom of FIG. 6A, represents the voltage across the rectifier (Vsi).

[0126] The rectifier current (Isi) is approximated by a sinusoidal waveform. During the first half cycle, current (Isi) enters the rectifier via the left leg of the bridge, flows through the load (RL,dc), and returns via the switch (D). This creates a voltage (Vsa) across the return diode on the left leg of the bridge that corresponds with the positive period of the current (Isi) waveform. The diode voltage (Vsa) is approximated by the square waveform shown immediately below the rectifier current (Isi) waveform in FIG. 7A.

[0127] The voltage (Vsb) across the switch (D) is held at zero during the first half of the cycle while the switch (D) is conducting. During the second half of the cycle, the switch (D) is controlled to manipulate the phase angle between the rectifier current (Isi) and the rectifier voltage (Vsi). In FIG. 7A, the switch (D) continues to conduct for a period of time during the second half of the cycle when the current feed to the rectifier (Isi) reverses direction. The switch (D) short-circuits the rectifier during this period. The rectifier current (Isi) enters the rectifier via the right leg of the bridge, flows through the switch (D), and returns via the return diode on the left leg of the bridge.

[0128] Partway through the second half of the cycle, the switch (D) is switched to a non-conducting state by the controller. This causes the current (Isi) to flow through the load (RL,dc) and creates a voltage (Vsi) across the rectifier. The controller is configured to operate the switch (D) to manipulate the phase angle between the rectifier current (Isi) and the rectifier voltage (Vsi) and/or the rms voltage across the load. For example, the controller can modulate the time that the rectifier voltage (Vsi) is clamped during the second half of the cycle to control the voltage waveform of the rectifier.

[0129] Example operational waveforms for the two switch rectifiers of FIG. 2 are shown in FIG. 7B. In the example shown in FIG. 7B, the switches in each rectifier are operated by controller 20 (for example a microprocessor) in such a way that ZVS turn-on can be achieved and the Vsi waveform lags the Isi waveform by a controllable amount according to the duty cycle of the switches. Hence, the two rightmost branches in FIG. 6 can be expressed as a controllable capacitance in series with a controllable resistor, as shown in FIG. 8. In addition to the ability to control the power flow by changing the controllable resistor, at a sufficient quality factor Q, this controllable capacitance helps to regulate the power flow to the load whilst maintaining a power factor close to unity.

[0130] The first waveform, shown at the top of FIG. 7B, represents the current (Isi) flowing through the rectifiers. The next waveform represents the voltage (Vsa) across the switch (D1) on the left leg of the bridge. The third waveform represents the voltage (Vsb) across the switch (D2) on the right leg of the bridge. The fourth waveform represents the conducting state of the switch (D1). The fifth waveform represents the conducting state of the switch (D2). And the final waveform, shown at the bottom of FIG. 7B, represents the voltage across the rectifier (Vsi).

[0131] The rectifier current (Isi) is approximated by a sinusoidal waveform. Initially both switches (D1, D2) are in a conducting state, effectively bypassing the rectifier and introducing a phase difference between the current (Isi) waveform and the voltage (Vsi) waveform. Current (Isi) enters the rectifier via the left leg of the bridge, flows from the left switch (D1) to the right switch (D2), and exits via the right leg of the bridge. The voltage (Vsi) across the rectifier is clamped at zero volts and no power is transferred to the load (RL,dc).

[0132] Partway through the first half of the cycle, the left switch (D1) is switched to a non-conducting state by a controller. This causes current (Isi) to flow through the left diode to the load (RL,dc), and return via the right switch (D2). This creates a voltage (Vsa) across the left switch (D1) and the rectifier (Vsi). The switch voltage (Vsa) is approximated by the square waveform shown immediately below the rectifier current (Isi) waveform in FIG. 7B. The rectifier voltage is approximated by the waveform shown at the bottom of FIG. 7B.

[0133] The voltage (Vsb) across the right switch (D2) is held at zero during the first half of the cycle. During the second half of the cycle, the right switch (D2) is controlled to manipulate the converter phase angle between the rectifier current (Isi) and the rectifier voltage (Vsi). In FIG. 7B, the right switch (D2) continues to conduct for a period of time during the second half of the cycle when the current feed to the rectifier (Isi) reverses direction. The right switch (D2) short-circuits the rectifier during this period. The rectifier current (Isi) enters the rectifier via the right leg of the bridge, flows through the right switch (D2), and returns via the left switch (D1).

[0134] Partway through the second half of the cycle, the right switch (D2) is switched to a non-conducting state by the controller. This causes current (Isi) to flow through the right diode to the load (RL,dc). This creates a voltage (Vsb) across the right switch (D2) and the rectifier (Vsi).

[0135] The controller is configured to operate the switches (D1, D2) to manipulate the time during each cycle that the current is fed to the load (RL,dc). For example, the controller can modulate the time that the rectify voltage (Vsi) is clamped during each cycle to control the rms voltage across the load, and/or the phase angle between the rectifier current (Isi) and the rectifier voltage (Vsi).

[0136] The ability of the controlled power converter to control the converter phase angle between the rectifier current and voltage (according to the example of a pick-up or secondary as described above) means that the impedance of the converter can be controlled. Therefore, as shown in FIG. 8, Xac can be controlled. The compensation network comprising Cst and the components that are in parallel with Cst (i.e. those components comprising Xtmn, Xac ad R.sub.LC) comprise a controlled compression impedance network.

[0137] The techniques above can be further developed to provide active impedance control or matching, which provides the functional benefits of active compression and tuning but only requires a single inverter after the compensation network. This is shown by the circuits in FIGS. 9-11. In these figures the impedance of the third branch 8 of the compensation network 2 is represented as Xsi. As will be described further below, the reactances in the compensation network are provided so that the reactance of the first branch 2 is substantially cancelled by the combined reactance of the second branch 6, third branch 8 and the controllable power converter. This is described further below. FIG. 9 is an example of a WPT pick-up circuit that can implement the active impedance matching disclosed herein. FIG. 10 is an example of a WPT primary circuit that can implement the active impedance control and/or matching disclosed herein. The controlled power converter used for the circuit of FIG. 9 (or FIG. 10) can take a variety of forms (as suggested in FIGS. 2-4 above) and can thus be represented generically as shown in FIG. 11. For implementation in a primary circuit, such as FIG. 10, the DC input source may be a variable voltage, for example a solar panel, and the load may comprise the power being supplied to a secondary. Therefore, the power converter to which the variable source is connected, and the compensation network can be controlled to control the input impedance which in this example is the impedance seen by the variable input power source.

[0138] The principle of operation is based on that described above in that the power converter is operated such that the converter and load appear as a variable reactance and a resistor, as shown in FIG. 12. Again, this is achieved by making the Vsi waveform lag/lead the Isi waveform, effectively controlling the phase angle of the converter.

[0139] It is helpful to construct a model of the circuit as an example to illustrate the circuit design and functionality to the skilled addressee.

[0140] The full-bridge converter in FIG. 13 is controlled using the variables ϕ and ψ, as defined in FIG. 14. Variable ϕ corresponds to the duty cycle of the controllable power converter. Variable ψ is the angle between the voltage and current of the controllable converter and is thus the phase angle of the converter. This angle is controllable by control of the converter switch or switches as described by way of example above using controller 40.

[0141] It follows that the square wave voltage across the converter input is given by

[00001]$\begin{array}{cc}\text{?}=V_{\mathrm{out}}\frac{4}{\pi }\text{?}\frac{\sin \left(n\phi /2\right)}{n}\cos \left(n\omega t+n\psi \right)& \left(5\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0142] Using (5) and by assuming the converter is 100% efficient, it can be shown that

[00002]$\begin{array}{cc}{I}_{\mathrm{out}}=\frac{2\sqrt{2}}{\pi }{I}_{\mathrm{si},\mathrm{rms}}\sin \left(\phi /2\right)\cos \left(\psi \right)& \left(6\right)\end{array}$

[0143] Using (6) and by again assuming the converter is 100% efficient, it can be shown that

[00003]$\begin{array}{cc}\text{?}=\frac{8}{{\pi }^2}{\sin }^2\left(\phi /2\right){\cos }^2\left(\psi \right)R_{\mathrm{out}}& \left(7\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0144] where Rac is the real part of the impedance of the converter and battery. If Xac is defined as the imaginary part of the same impedance, it can be said that

[00004]$\begin{array}{cc}\text{?}=\frac{\text{?}\sin \left(\psi \right)}{I_{\mathrm{si},\mathrm{rms}}}& \left(8\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0145] Substituting (5) and (6) into (8) results in

[00005]$\begin{array}{cc}\text{?}=\frac{8}{{\pi }^2}{\sin }^2\left(\phi /2\right)\cos \left(\psi \right)\sin \left(\psi \right)R_{\mathrm{out}}& \left(9\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0146] In summary, the battery and full-bridge converter shown in FIG. 13 can be represented as an impedance with a real and imaginary component, as illustrated by FIG. 15.

[0147] Using the equivalent circuit in FIG. 15 and by defining

X.sub.eq=ωL.sub.si−1/(ωC.sub.si)+X.sub.ac;

the combined impedance of Cst, Lsi, the converter and the load is given by

[00006]$\begin{array}{cc}\mathrm{Re}\left\{Z_1\right\}=\frac{\text{?}}{{\left(1-\text{?}\right)}^2+\text{?}}& \left(10\right)\end{array}$$\mathrm{and}$$\begin{array}{cc}\mathrm{Im}\left\{Z_1\right\}=\frac{X_{\mathrm{eq}}\left(1-\text{?}\right)-\text{?}}{{\left(1-\text{?}\right)}^2+\text{?}}& \left(11\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0148] In addition, the total impedance seen by the induced voltage is given by

[00007]$\begin{array}{cc}{Z}_s=\text{?}+\frac{1}{\text{?}}+\mathrm{Re}\left\{Z_1\right\}+\mathrm{Im}\left\{Z_1\right\}& \left(12\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0149] Therefore, the circuit can be tuned for a given set of operating conditions by choosing Lst and Cst,s such that their combined impedance is equal to the value of Im{Z.sub.1} at those operating conditions. When this is the case, (12) reduces to

Z.sub.s≈Re{Z.sub.1}  (13)

[0150] The variable capacitance or inductance of a TMN is emulated using (7) and (9) for a fixed load (e.g. battery) voltage. Ideally, ψ can be varied with a fixed duty cycle ϕ in order to vary Xac with minimal change in Rac. For most values of battery voltage and output power, a fixed ϕ of π creates the largest variation in Xac with respect to iv, and therefore essentially functions as a TMN. Using a ϕ of π does, however, tend to produce the largest variation in Rac. The real and imaginary components of impedance for values of ϕ and ψ are shown in FIGS. 16A and 16B.

[0151] From (7 and (10) it can be seen that Reg{Z.sub.1} can be controlled by adjusting ψ. Therefore, according to (13), the real power delivered to the secondary can be controlled by ψ via Re{Z.sub.1}, and is given by

[00008]$\begin{array}{cc}\mathrm{Re}\left\{P_{\mathrm{sr}}\right\}=\frac{.Math.V_{\mathrm{sr}}^2.Math.}{\mathrm{Re}\left\{Z_s\right\}}=\frac{.Math.V_{\mathrm{sr}}^2.Math.}{\mathrm{Re}\left\{Z_1\right\}}& \left(14\right)\end{array}$

[0152] Therefore, it can be seen that control of the phase angle ψ of the controllable power converter (for example converter 50 in FIG. 13), in conjunction with the compensation network, allows active control of the impedance of the power transfer circuit. This in turn allows control of the converter phase angle to control the real power delivered to the power transfer circuit, and thus the power made available to the load.

[0153] The compensation network may be considered as two sub-networks. The first sub-network comprises the first branch 14, and the second sub-network comprises the second branch 16 and third branch 18. From (12) it can be seen that making the sub-network of the compensation circuit 12 have a reactance (or impedance) that at least ameliorates, or cancels, the combined reactance (or impedance) of the second sub-network in combination with the reactance of the controllable power converter allows active control of the impedance of the power transfer circuit.

[0154] This is achieved by using the compensation network and the power converter to partially or wholly cancel the power transfer circuit reactance. Thus, in the example of a secondary circuit, the impedance looking into the circuit is substantially or completely resistive. As explained further below the power transfer circuit can be designed to achieve this over a range of phase angle operation of the power converter.

[0155] Unlike conventional compensation networks which are tuned for resonance at the frequency at which power is transferred wirelessly, it can be seen that the compensation network herein is tuned to allow for a reactance of the controlled power converter.

[0156] It will also be seen that control of the reactance (or impedance) of the controlled power converter allows impedance compression to be implemented using LCL networks as disclosed herein (or variants of those networks). The second and third branches (i.e. branches 16 and 18 of the compensation network 12 are in parallel with each other. The third branch effectively has the impedance of the controlled power converter 50 and the load R) in series with it. As the load changes, the converter phase angle can be controlled to balance the overall impedance of the third branch 18 and its series connected elements to match or balance the impedance of the second branch 16. Since the branches are in parallel the effect of the change in the load is diminished or reduced when see looking into the power transfer circuit. Therefore, if the impedance compression is implemented in a secondary power transfer circuit as shown in FIG. 13, then the effect of a change is load supplied by the secondary is reduced as seen by a primary circuit which is supplying power to that secondary circuit.

[0157] To validate the foregoing, a 7.7 kW system has been designed. Due to the large number of variables in (10) and (11), the values of the passive elements were found graphically. It will be understood by the skilled addressee that the models provided above present sufficient information to select component values for a given set of required operating conditions, and the methodology below is but one illustrative example.

[0158] The real and imaginary components of Z.sub.1 were plotted against ψ for different combinations of Lsi and Cst. These combinations were then assessed against a set of criteria. First, there needs to be a range of ψ for which Im{Zs} is as flat as possible. This is helped by placing the range around the turning point of the curve to capitalise on the inherently lower gradients there, as shown in FIG. 17B. Second, for that range, it is desirable for the variation in Re{Zs} to be as large as possible. Third, there needs to be a value of Im{Zs} in the operating range that does not exceed the impedance of the available power transfer coil. Otherwise, there is no value of Cst,s that will result in zero Im{Zs}.

[0159] To select Cst,s, its combined impedance with Lst should equal the lowest value of Im{Zs}. This results in Im{Zs} being minimally inductive across the whole operating range. This in turn translates to an inductive load seen at the primary inverter output and soft switching of the primary switches. Additionally, this selection method ensures the point with the lowest value of Re{Z.sub.1} (point F in FIGS. 17A and 17B) is fully tuned. This is relevant because the same amount of mistuning would result in a lower power factor at this point.

[0160] Restricting the values of ψ to the closed interval (−π/2, 0) keeps Xac and thus Zac inductive from the perspective of the rectifier. Doing this ensures ZVS turn off for all secondary switches. The selected parameters are summarised in Table 1.

TABLE-US-00001 TABLE 1 Summary of Selected Parameters Parameter Value ϕ π L.sub.si 90 μH C.sub.st 100 nF L.sub.st 53.83 μH V.sub.out 350 V P.sub.out 7700 W

[0161] The system was modelled in LTspice by replacing the converter and battery with a sinusoidal voltage source equal to the fundamental component of V.sub.si. The variable ψ was controlled indirectly by changing e, defined as the angle between V.sub.sr and V.sub.si.

[0162] The predicted impedances of the selected operating points are shown in FIG. 17 and the corresponding simulation data in Table 2. The model has been subsequently refined by representing the battery and converter with a square wave source. FIGS. 18A and 18B show simulated waveforms for operating points A and F using the refined model.

[0163] The simulations show the system can tolerate a 2.27-fold voltage change between operating points A and F of FIGS. 17A and 17B with near-unity power factor (PF) (from the perspective of V.sub.sr) for all operating points. They also show good agreement with the mathematical models for most of the points tested, with the exception of point D. At this point, 7700 W was achieved at a ψ value 0.03 radians different from predicted. Additionally, for many of the unlabelled points between C & D and D & E, there was no ψ value that would yield 7700 kW. It is suggested that this is because L.sub.st and C.sub.st,s are detuned from C.sub.st,p, resulting in a reverse current being generated through L.sub.si.

[0164] From (14), having a large variation in Re{Z.sub.1} with respect to ψ is desirable, as it means that the system is able to handle large changes in V.sub.sr. However, increasing the variation in Re{Z.sub.1} also increases the variation in Im{Z.sub.1}, resulting in greater detuning as ψ is controlled.

[0165] Therefore, the values of L.sub.si and C.sub.st,p, that is, the variables that Re{Z.sub.1} depends on that are set, should be chosen carefully.

TABLE-US-00002 TABLE 2 Summary of Results Pt. Meas. P.sub.si V.sub.sr, pk I.sub.st, rms I.sub.si, rms Op. ψ (r) (W) (V) (A) (A) PF A 0.00 7695 259.72 41.19 24.36 1 B 0.13 7765 247.26 44.62 24.91 1 C 0.25 7651 233.81 47.05 25.28 0.99 D 0.64 7752 189.32 60.52 31.11 0.96 E 0.88 7690 147.36 76.56 39.91 0.97 F 1.07 7635 114.41 94.81 50.86 1

[0166] Control for the various illustrative logical blocks, modules, routines, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware (e.g., ASICs or FPGA devices), computer software that runs on computer hardware, or combinations of both. Moreover, the various illustrative logical blocks and modules described in connection with the embodiments disclosed herein can be implemented or performed by a machine, such as a processor device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor device can be a microprocessor, but in the alternative, the processor device can be a controller, microcontroller, or state machine, combinations of the same, or the like. A processor device can include electrical circuitry configured to process computer-executable instructions. In another embodiment, a processor device includes an FPGA or other programmable device that performs logic operations without processing computer-executable instructions. A processor device can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, a processor device may also include primarily analog components. For example, some or all of the rendering techniques described herein may be implemented in analog circuitry or mixed analog and digital circuitry. A computing environment can include any type of computer system, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computational engine within an appliance, to name a few. The elements of a method, process, routine, or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor device, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of a non-transitory computer-readable storage medium. An exemplary storage medium can be coupled to the processor device such that the processor device can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor device. The processor device and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In the alternative, the processor device and the storage medium can reside as discrete components in a user terminal.

[0167] Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements or steps. Thus, such conditional language is not generally intended to imply that features, elements or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without other input or prompting, whether these features, elements or steps are included or are to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list.

[0168] Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, and at least one of Z to each be present.

[0169] While the above detailed description has shown, described, and pointed out novel features as applied to various embodiments, it can be understood that various omissions, substitutions, and changes in the form and details of the devices or algorithms illustrated can be made without departing from the spirit of the disclosure. As can be recognized, certain embodiments described herein can be embodied within a form that does not provide all of the features and benefits set forth herein, as some features can be used or practiced separately from others. The scope of certain embodiments disclosed herein is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0170] Any routine descriptions, elements or blocks in the flow diagrams described herein and/or depicted in the attached figures should be understood as potentially representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or elements in the routine. Alternate implementations are included within the scope of the embodiments described herein in which elements or functions may be deleted, or executed out of order from that shown or discussed, including substantially synchronously or in reverse order, depending on the functionality involved as would be understood by those skilled in the art.

[0171] It should be emphasized that many variations and modifications may be made to the above-described embodiments, the elements of which are to be understood as being among other acceptable examples. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.