System on Chip Comprising a Connection Interface Between Master Devices and Slave Devices

Abstract

In an embodiment a system on chip includes at least one master device, at least one slave device, a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters, and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.

Claims

1. A system on chip comprising: at least one master device; at least one slave device; a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters; and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.

2. The system on chip according to claim 1, wherein the connection interface comprises: at least one input stage connected to the at least one master device; at least one output stage connected to the at least one slave device; and at least one decoder connected to the at least one input stage and to the at least one output stage.

3. The system on chip according to claim 2, wherein each of the at least one input stage, the at least one output stage and the at least one decoder are configured to operate according to the configuration parameters.

4. The system on chip according to claim 2, wherein the configuration bus is connected to each of the at least one input stage, the at least one output stage and the at least one decoder.

5. The system on chip according to claim 4, wherein the configuration bus is configured to deliver to each of the at least one input stage, the at least one output stage and the at least one decoder the new configuration parameters so as to define their operation.

6. The system on chip according to claim 2, wherein the at least one output stage includes an arbiter and an output logic circuit.

7. The system on chip according to claim 1, further comprising a memory connected to the configuration bus, wherein the memory is configured to store the new configuration parameters.

8. The system on chip according to claim 7, wherein the memory is a flash memory.

9. The system on chip according to claim 1, wherein the connection interface comprises a selection circuit configured to select the configuration parameters between the new configuration parameters and default configuration parameters.

10. The system on chip according to claim 9, wherein the selection circuit comprises a register, and wherein the default configuration parameters are stored in the register and are coded at a register-transfer level.

11. The system on chip according to claim 9, wherein the selection circuit further comprises a volatile register configured to store the new configuration parameters.

12. The system on chip according to claim 11, wherein the volatile register is further configured to store a guard bit, and wherein the selection circuit is configured to select a new configuration parameter according to a value of the guard bit guarantying that the new configuration parameter is valid.

13. The system on chip according to claim 9, wherein the selection circuit comprises a register, a MUX and an AND gate, wherein a first input of the MUX is connected to a non-volatile register of the register and a second input of the MUX is connected to a volatile register of the register, and wherein the MUX is controllable by an output of the AND gate.

14. The system on chip according to claim 13, wherein the AND gate is configured to: receive a reset signal, a disabling signal and a guard bit signal; and select a new configuration parameter only when the guard bit signal indicates that the new configuration parameter is valid, the guard bit storable in the volatile register.

15. The system on chip according to claim 13, wherein the register is configured to store a default gating bit in the non-volatile register and a new gating bit in the volatile register.

16. The system on chip according to claim 13, wherein an output of the MUX is connected to a first input of a second AND gate, and wherein a second input of the second AND gate is connected to a terminal configured to provide a signal to be gated.

17. The system on chip according to claim 16, wherein the second AND gate is configured to provide a gate signal according to a selected gate bit.

18. The system on chip according to claim 1, wherein the connection interface comprises: at least one input stage connected to the at least one master device; at least one output stage connected to the at least one slave device; and at least one decoder connected to the at least one input stage and to the at least one output stage, wherein each of the at least one input stage, the at least one output stage and the at least one decoder comprises a selection circuit configured to select the configuration parameters between the new configuration parameters and default configuration parameters.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other advantages and features of the invention will appear in the detailed description of embodiments and implementations, in no way restrictive, and the attached drawings in which:

[0024] FIG. 1 shows a system on chip comprising a plurality of master devices M and a plurality of slave devices;

[0025] FIG. 2 illustrates an example of two connections of a bus matrix according to an embodiment;

[0026] FIG. 3 illustrates a connection of a submatrix according to an embodiment; and

[0027] FIGS. 4 and 5 illustrate different selection circuits according to embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0028] FIG. 1 shows a system on chip SOC comprising a plurality of master devices M and a plurality of slave devices S. The system on chip can also comprise at least one memory MEM, for example a flash memory, with a flash interface to communicate with the memory. The system on chip can also comprise instruction caches I-cache.

[0029] The system on chip can also include a general-purpose direct memory access GPDMA.sub.1, different buses such as advanced high-performance buses AHB.sub.1, AHB.sub.4 and advanced peripheral buses APB, APB.sub.1, APB.sub.2, APB.sub.4.

[0030] For example, the system on chip can comprise different processing units as master devices M. The system on chip can comprise peripherals IP#1, . . . , IP#6 as slave devices S. The peripherals can be organized in different domains PHD and sub-domains.

[0031] The system on chip SOC also comprises different connection interfaces between the master devices and the slave devices. In particular, the system on chip comprises at least one bus matrix BM as a connection interface. The bus matrix BM is a connection interface that is connected on one side to the masters M and on the other side directly to the slave devices S or to a peripheral domain PHD.

[0032] The bus matrix BM is configured to route the signals between the master devices M and either the slave devices S or the peripheral domains PHD so as to allow a communication between the master devices M and either the slave devices S or the peripheral domain PHD.

[0033] The bus matrix BM is arranged in rows and columns. Each row is connected to one master port Mp.sub.O, . . . , Mp.sub.N of the bus matrix BM. Each column is connected to one slave port Sp.sub.O, . . . , Sp.sub.N of the bus matrix BM. In FIG. 1, the connections between the rows and the columns are represented with dots.

[0034] According to the connections defined by the bus matrix, each slave S can communicate with different masters M, and each master M can communicate with different slaves S. The bus matrix BM is hard coded.

[0035] A connection interface, named submatrix SM, is also included in each peripheral domain PDM or sub-domain. Such a submatrix SM comprises on a first side a port connected to the bus matrix BM and on the other side a port connected to the peripherals or to the subdomains.

[0036] FIG. 2 illustrates an example of two connections of a bus matrix. In particular, the bus matrix is configured to connect a master device Mj to a slave device Sk, and to connect a master device My to the slave device Sk. Thus, the bus matrix comprises two slave ports Spj and Spy connected respectively to the master devices Mj et My, and a master port Mpk connected to the slave device Sk.

[0037] The bus matrix also comprises an input stage ISBMj, ISBMy for each master device Mj, My connected to the bus matrix BM. Each input stage ISBMj, ISBMy is configured to register and hold an incoming transfer from the master device Mj, My connected to this input stage ISBMj, ISBMy. In particular, each input stage ISBMj, ISBMy is configured to hold the incoming transfer when the slave device Sk is busy.

[0038] The bus matrix also comprises a decoder DBMjk, DBMyk, for each connection between a slave port Spj, Spy and a master port Mpk (i.e. for each dot of the matrix). Each decoder is configured to select a slave device. In particular, the decoder implements a route table for each master device. The decoder is able to implement a remap mechanism and is further configured to route messages from the slave device connected to the decoder to the master.

[0039] The bus matrix BM comprises an output stage for each slave device S connected to the bus matrix. For example, in FIG. 2, the bus matrix comprises an output stage OSBMk connected to the master port My and the slave device Sk. The output stage OSBMk is connected to the decoders DBMjk and DBMyk and to all the other decoders DBMk of the row connected to the master port My.

[0040] Each output stage includes an arbiter ABT, configured to determine which slave port has access to the shared slave device, and output logic OLBM. The output logic OLBM is configured to decide when to communicate with the master device selected by the arbiter.

[0041] FIG. 3 illustrates a connection of a submatrix SM. The submatrix is configured to connect one master device to different slave devices. For example, the connection of the submatrix SM shown in FIG. 3 connects a master M to a slave device Sx. Thus, for each connection, the submatrix comprises one slave port Sp connected to the master device M, and a master port Mpx connected to the slave device Sx.

[0042] The submatrix SM comprises an input stage ISSM connected to a master port of the bus matrix. The input stage ISSM is configured to register and hold an incoming transfer from the bus matrix. In particular, the input stage ISSM is configured to hold the incoming transfer when the slave device S is busy.

[0043] The submatrix SM also comprises a decoder DSMx, for each connection between an input stage ISSM and an output stage OSSMx of the submatrix SM. The decoder DSMx is configured to select a slave device and to implement a map table.

[0044] Each output stage OSSMx includes an output logic OLSM. The output logic OLSM is configured to decide when to communicate with the master device.

[0045] The bus matrix BM and each submatrix SM are configured to operate according to configuration parameters. For example, the configuration parameters are used to define the operation of each input stage ISBM, ISSM. In particular, the configuration parameters can be used to disable a master device.

[0046] The configuration parameters are also used to define the operation of each decoder DBM, DSM. In particular, the configuration parameters can define the route map and the remap table of the bus matrix BM or of the submatrix SM.

[0047] The configuration parameters are also used to define the operation of each output stage OSBM, OSSM. In particular, the configuration parameters can be used to disable a slave device and to define the arbiter policy.

[0048] The system on chip is configured to modify the configuration parameters so as to adapt the operation of the bus matrix and of each submatrix. This allows the versality of the system on chip improved.

[0049] More particularly, the system on chip SOC comprises default configuration parameters coded at a register-transfer level (i.e. RTL coded). The default configuration parameters define a default operation of the bus matrix and of each submatrix. The default operation of the bus matrix and of each submatrix is chosen when designing the system on chip. In particular, the default configuration parameters are chosen to guarantee the functionality of the bus matrix and of each submatrix in all possible scenarios. Nevertheless, the configuration parameters can be modified during runtime to improve the performance and the flexibility of the bus matrix and of each submatrix.

[0050] Indeed, as shown in FIGS. 1 and 2, the bus matrix BM and each submatrix SM are connected to a configuration bus. More particularly, each input stage ISBM, ISSM, each decoder DBM, DSM and each output stage OSBM, OSSM of the bus matrix BM and of each submatrix SM is connected to a configuration bus CFB.

[0051] The configuration bus CFB is configured to deliver new configuration parameters to the bus matrix BM and to each submatrix SM. The new configuration parameters allow the operation of the bus matrix BM and of each submatrix SM to be modified and are stored in a memory MEM, such as a flash memory or a one-time programmable memory or a plurality of system configuration registers in a persistent domain.

[0052] In particular, the flash memory is configured to include a flash memory area devoted to storage of the new configuration parameters. This flash memory area can be protected so that only an authorized user can access them and modify their values.

[0053] Alternatively, the one-time programmable memory includes a memory area devoted to storage of the new configuration parameters for the connection interfaces. This memory area can also be protected

[0054] Alternatively, some configuration system registers in a persistent domain are devoted to storage of the new configuration parameters for the connection interfaces.

[0055] The bus matrix BM and each submatrix SM comprise selection circuits. FIGs. 4 and 5 illustrate different selection circuits SELC.sub.1, SELC.sub.2.

[0056] The selection circuits are configured to select the configuration parameters between the default configuration parameters DCFP and the new configuration parameters NCFP. In particular, each element of the bus matrix and of each submatrix comprises such a selection circuit.

[0057] More particularly, each input stage ISBM, ISSM comprises a selection circuit SELC.sub.1 and/or SELC.sub.2 configured to select the configuration parameters of this input stage.

[0058] Each decoder DBM, DSM also comprises a selection circuit configured to select the configuration parameters of this decoder.

[0059] Each output stage also comprises a selection circuit configured to select the configuration parameters of this output stage.

[0060] As shown in FIG. 4, each selection circuit SELC.sub.1 comprises relevant parameter registers.

[0061] The relevant parameter registers RPR.sub.1 are configured to store default configuration parameters DCFP coded at register-transfer level. These default parameters DCFP are associated to the element of the connection interface (i.e. the input stage, the decoder or the output stage) that includes the selection circuit SELC.sub.1 .

[0062] The relevant parameter registers RPR.sub.1 also comprise a volatile register CFVR.sub.1 connected to the configuration bus CFB and configured to store new configuration parameters NCFP received from the configuration bus CFG.

[0063] In particular, the system on chip can be configured to read the new configuration parameters NCFP stored in the memory MEM after a reset of the system on chip. Then, the system on chip can be configured to deliver the new configuration parameters to the volatile register CFVR.sub.1 through the configuration bus CFG.

[0064] The volatile register CFVR.sub.1 can also be configured to store a guard bit GB.sub.1. The guard bit GB.sub.1 is configured to validate the possibility of using the new configuration parameters. The value of the guard bit GB.sub.1 is defined according to a value of an error-correcting code of the memory MEM after the reading of the new configuration parameters NCFP. In particular, if the error-correcting code indicates that the new configuration parameters are corrupted, the value of the guard bit GB.sub.1 is set to prevent using the new configuration parameters. If the error-correcting code indicates that the new configuration parameters are not corrupted, the value of the guard bit GB.sub.1 is set to allow using the new configuration parameters.

[0065] The selection circuit SELC.sub.1 also comprises a multiplexer MUX.sub.1 . The multiplexer MUX.sub.1 comprises two inputs configured to receive the default configuration parameters DCFP and the new configuration parameters NFCP and one output configured to deliver the selected configuration parameters SCFP.

[0066] The multiplexer MUX.sub.1 also comprises a selector pin to select the configuration parameters between the default configuration parameters DCFP and the new configuration parameters NCFP. The selector pin is configured to receive a selection signal SEL.sub.1.

[0067] In particular, the selection circuit SELC.sub.1 comprises an AND logic gate ANDG.sub.1 used to generate the selection signal SEL.sub.1. The logic gate ANDG.sub.1 is further configured to receive the guard bit GB, a reset signal RST.sub.1 and a disabling signal DSB.sub.1. Thus, the selection signal SELC.sub.1 is configured to select the new configuration parameters NCFP only when the guard bit GB.sub.1 indicates that the new configuration parameters NCFP are valid. The selection circuit SELC.sub.1 can be coded at a register-transfer level.

[0068] As shown in FIG. 5, another selection circuit SELC.sub.2 can also be used to gate signals SGT. The selection circuit SELC.sub.2 is configured to gate the signals SGT according to a gating bit SGB.

[0069] More particularly, the selection circuit SELC.sub.2 includes relevant parameter registers RPR.sub.2 storing a default gating bit DGB coded at a register-transfer level. The relevant parameter registers RPR.sub.2 also includes a volatile register CFVR.sub.2 connected to the configuration bus CFB. This volatile register CFVR.sub.2 is configured to store a new gating bit NGB received from the configuration bus CFB and can also be configured to store a guard bit GB.sub.2. The guard bit GB.sub.2 is configured to validate the possibility of using the new gating bit NGB.

[0070] The selection circuit SELC.sub.2 further comprises an AND logic gate ANDG.sub.2 used to generate a selection signal SEL.sub.2. The logic gate ANDG.sub.2 is configured to receive the guard bit GB.sub.2, a reset signal RST.sub.2 and a disabling signal DSB.sub.2.

[0071] The selection circuit SELC.sub.2 also comprises a multiplexer MUX.sub.2. The multiplexer MUX.sub.2 comprises two inputs configured to receive the default gating bit DGB and the new gating bit NGB and one output configured to deliver the selected gating bit SGB. The multiplexer MUX.sub.2 also comprises a selector pin configured to receive the selection signal SEL.sub.2. Thus, the selection signal SEL.sub.2 is configured to select the new gating bit NGB only when the guard bit GB.sub.2 indicates that the new gating bit NGB is valid.

[0072] The selection circuit SELC.sub.2 also comprises an AND gate ANDG.sub.3 having a first input connected to the output of the multiplexer MUX.sub.2 to receive the selected gate bit SGB, and other inputs configured to receive the signals SGT to be gated. Therefore, the gate ANDG.sub.3 can gate the signals SGT according to the value of the selected gate bit SGB. These gated signals SGT can therefore be transmitted to a subcircuit SBC to be gated.

[0073] Thus, such a selection circuit SELC.sub.2 is configured to gate signals SGT in order to enable or disable some features or parameters of the bus matrix BM or the submatrix SM.

[0074] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.