METHOD FOR MANUFACTURING METAL GATE MOS TRANSISTOR

Abstract

The present application discloses a method for manufacturing a metal gate MOS transistor, comprising: step 1, forming metal gates; step 2, forming a first dielectric layer disposed on the metal gates and the zeroth interlayer film; step 3, forming an opening for the zeroth metal layer; step 4, forming a first Ti layer and a second TiN layer; and step 5, filling the opening of the zeroth metal layer with a metal material. After step 1 and before step 4, performing the first annealing at a first temperature to adjust a threshold voltage of the metal gate MOS transistor to a target value. After step 4 and before step 5, performing the second annealing at a second temperature lower than the first temperature to adjust on-resistance of the metal gate MOS transistor.

Claims

1. A method for manufacturing a metal gate MOS transistor, comprising following steps: step 1, forming metal gates on a semiconductor substrate, and forming a zeroth interlayer film in a spacing between adjacent two of the metal gates; step 2, forming a first dielectric layer on the metal gates and the zeroth interlayer film; step 3, selecting a region for forming a zeroth metal layer, and etching the first dielectric layer and the zeroth interlayer film in the region to form an opening for the zeroth metal layer; step 4, forming a first Ti layer and a second TiN layer on an inner side surface of the opening of the zeroth metal layer; and step 5, forming the zeroth metal layer by filling the opening with a metal material; to wherein the method further comprises, after the step 1 and before the step 4: performing a first annealing at a first temperature for adjusting a threshold voltage of the metal gate MOS transistor to a target value by setting the first temperature; and wherein the method further comprises, after step 4 and before step 5: performing a second annealing at a second temperature for adjusting an on-resistance of the metal gate MOS transistor and reducing the on-resistance by reducing the second temperature; wherein the second temperature is lower than the first temperature.

2. The method according to claim 1, wherein in step 1, the metal gates are formed by means of a gate-last process.

3. The method according to claim 2, wherein the gate-last process comprises: removing dummy polysilicon gates; and forming the metal gates where the dummy polysilicon gate are removed.

4. The method according to claim 2, wherein each one of the metal gates comprise a metal work function layer and a metal conductive material layer stacked in sequence.

5. The method according to claim 4, wherein a material of the metal conductive material layer comprises tungsten.

6. The method according to claim 5, wherein a material of the zeroth metal layer comprises tungsten.

7. The method according to claim 6, wherein the first temperature is in a range of 650° C.-700° C.

8. The method according to claim 7, wherein the second temperature is in a range of 550° C.-600° C.

9. The method according to claim 5, after forming the metal gates in step 1, further comprising a step of etching back the metal conductive material layer.

10. The method according to claim 9, before forming the first dielectric layer in step 2, further comprising: a step of forming a second dielectric layer to fill an etching-back region of the metal conductive material layer; wherein a material of the first dielectric layer is a same as a material of the zeroth interlayer film, and a material of the second dielectric layer comprises silicon nitride; and wherein the second dielectric layer is formed by means of a deposition process, and wherein the method further comprises performing planarization by means of a chemical mechanical polishing process after the deposition process.

11. The method according to claim 4, wherein in step 1, a gate dielectric layer is disposed between the metal gates and the semiconductor substrate.

12. The method according to claim 11, wherein the gate dielectric layer comprises a high dielectric constant layer.

13. The method according to claim 12, wherein the metal gate MOS transistor is a fin transistor, wherein fins are formed on the semiconductor substrate by patterning the semiconductor substrate; and wherein the metal gates are disposed on a top surface and side surfaces of one of the fins.

14. The method according to claim 13, wherein step 1 further comprises, forming a source region and a drain region in the fins on two sides of each one of the metal gates.

15. The method according to claim 4, wherein the metal gate MOS transistor comprises an NMOS and a PMOS.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The present application is described in detail below with reference to the drawings and specific implementations.

[0061] FIG. 1 is a process flow chart of an existing method for manufacturing a metal gate MOS transistor.

[0062] FIG. 2A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an NMOS device.

[0063] FIG. 2B is a chart comparing the threshold voltages on two wafers containing metal gate MOS transistors which are annealed at different temperatures for the zeroth metal layer, applying an existing process.

[0064] FIG. 3A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an PMOS device by the existing method.

[0065] FIG. 3B is a chart comparing the threshold voltages on two wafers containing metal gate MOS transistors which are annealed at different temperatures for the zeroth metal layer, applying an existing process.

[0066] FIG. 4 is a process flow chart of the method for manufacturing a metal gate MOS transistor, according to an embodiment of the present application.

[0067] FIGS. 5A-5I illustrate cross sections of the device structures in steps of the method for manufacturing a metal gate MOS transistor according to the embodiment of the present application.

[0068] FIG. 6A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an NMOS device, by the method for manufacturing the metal gate MOS transistor according to the embodiment of the present application.

[0069] FIG. 6B is a chart comparing the threshold voltages containing metal gate NMOS transistors on two wafers which are annealed at different temperatures for the zeroth metal layer, according to the embodiment of the present application.

[0070] FIG. 7A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an PMOS device, by the method for manufacturing the metal gate MOS transistor according to the embodiment of the present application.

[0071] FIG. 7B is a chart comparing the threshold voltages containing metal gate PMOS transistors on two wafers which are annealed at different temperatures for the zeroth metal layer, according to the embodiment of the present application.

DETAILED DESCRIPTION

[0072] FIG. 4 is a process flow chart of a method for manufacturing a metal gate MOS transistor according to an embodiment of the present application. FIGS. 5A-5I illustrate cross sections of the device structures in steps of the method for manufacturing a metal gate MOS transistor according to the embodiment of the present application. The method for manufacturing a metal gate MOS transistor according to this embodiment of the present application includes the following steps:

[0073] Step 1: forming a zeroth interlayer film 506 on a semiconductor substrate 501, patterning metal gates 503 in the zeroth interlayer film 506, wherein the zeroth interlayer film 506 is configured to be in a spacing region between adjacent two of the metal gates 503.

[0074] In this embodiment of the present application, the metal gates 503 are patterned by means of a gate-last process.

[0075] Referring to FIG. 5A, dummy polysilicon gates 503a are first formed in the forming regions of the metal gates 503 before the metal gates 503. A gate dielectric layer 502 is formed at the bottom of the dummy polysilicon gates 503a, and sidewalls 504 are formed on the side surfaces of the dummy polysilicon gates 503a. A source region and a drain region are formed in the semiconductor substrate 501 on two sides of each of the dummy polysilicon gates 503a. With shrinking of the critical dimension in the continuing process nodes, it is necessary to introduce a strain structure to the source region and the drain region, so as to improve the mobility of channel carriers. In FIG. 5A, an embedded epitaxial layer 505 is formed in regions for forming the source region and the drain region, so as to improve the mobility of channel carriers by means of the stress of the embedded epitaxial layer 505.

[0076] The metal gate MOS transistor includes an NMOS and a PMOS.

[0077] The material of the embedded epitaxial layer 505 of the NMOS includes SiP, and the material of the embedded epitaxial layer 505 of the PMOS includes SiGe.

[0078] The source region and the drain region are formed in the embedded epitaxial layer 505 on two sides of each of the dummy polysilicon gates 503a in a self-aligned manner by means of source-drain implantation. After the implantation of the source region and the drain region is completed and annealing is performed, the method further includes a step of forming the zeroth interlayer film 506 in the spacing region between the dummy polysilicon gates 503a.

[0079] The semiconductor substrate 501 includes a silicon substrate. The metal gate MOS transistor is a fin transistor (FinFET), and a fin is formed on the semiconductor substrate 501 by patterning the semiconductor substrate 501. Each of the dummy polysilicon gates 503a covers the side surfaces and the top surface of the fin, and the source region and the drain region are formed in the fins on two sides of each of the dummy polysilicon gates 503a.

[0080] The gate-last process includes the following:

[0081] Referring FIG. 5B, the dummy polysilicon gates 503a are removed.

[0082] The metal gates 503 are formed in a regions where the dummy polysilicon gates 503a are removed.

[0083] Each of the metal gate 503 includes a metal work function layer 5031 and a metal conductive material layer 5032 stacked in sequence. The material of the metal conductive material layer 5032 includes tungsten.

[0084] In this embodiment of the present application, a gate dielectric layer 502 is isolated between each one of the metal gates 503 and the semiconductor substrate 501. In this embodiment of the present application, the gate dielectric layer 502 adopts a HK-first process, that is, the gate dielectric layer 502 is formed before the dummy polysilicon gates 503a are formed and is remains after the dummy polysilicon gates 503a are removed. In other embodiments, the gate dielectric layer 502 can also be formed by means of a HK-last process, in which case a dummy gate dielectric layer is required to replace the gate dielectric layer 502 before the dummy polysilicon gates 503a are formed, the dummy gate dielectric layer needs to be removed after the dummy polysilicon gates 503a are removed, and then the gate dielectric layer 502 is formed.

[0085] The gate dielectric layer 502 includes a high dielectric constant layer.

[0086] The step of forming the metal gates 503 in step 1 corresponds to the replacement of metal gate (RMG) step S201 in FIG. 4, that is, the metal gates 503 are formed by means of a gate replacement process.

[0087] Referring to FIG. 5C, after forming the metal gate 503, the method further includes performing an etching-back process of the metal conductive material layer 5032, i.e., WEB in step S202, wherein WEB is the tungsten etching-back process. The etching-back process of the metal conductive material layer 5032 also removes the metal work function layer 5031 on two sides of the metal conductive material layer 5032.

[0088] Step 2. Referring to FIG. 5E, a first dielectric layer 5061 is disposed on the metal gates 503 and the zeroth interlayer film 506.

[0089] In this embodiment of the present application, referring to FIG. 5D, before forming the first dielectric layer 5061, the method further includes a step of forming a second dielectric layer 507 to fill the void region left by the etching-back process on the metal conductive material layer 5032 and the metal work function layer 5031.

[0090] The material of the first dielectric layer 5061 is the same as the material of the zeroth interlayer film 506, and the material of the zeroth interlayer film 506 includes an oxide layer or a low dielectric constant layer.

[0091] The material of the second dielectric layer 507 includes silicon nitride. The second dielectric layer 507 is formed by means of a deposition process, and after the deposition process, the method further includes performing planarization by means of a chemical mechanical polishing process, i.e., SAC SiN (a self-aligned contact and silicon nitride) Dep./CMP corresponding to step S203 in FIG. 4.

[0092] Step 3. Referring to FIG. 5F, regions for forming the zeroth metal layer is selected, and the first dielectric layer 5061 and the zeroth interlayer film 506 in the selected regions for are patterned to form openings 508 in the zeroth metal layer. FIG. 5F shows the openings 508 aligned to the top surface of the embedded epitaxial layers 505 for the source region and the drain region.

[0093] In this embodiment of the present application, step 3 is to prepare for the M0 Etch of step S205 in FIG. 4.

[0094] Referring to FIG. 5G, subsequently, first annealing process 601 is performed at a first temperature. The first annealing process 601 is applied for adjusting the threshold voltage of the metal gate MOS transistors, i.e., adjusting the threshold voltage of the metal gate MOS transistors to a target value by applying the first annealing temperature. The first annealing process 601 has the process term of Vt adjusting thermal as in the step S204 in FIG. 4, wherein Vt is the threshold voltage, and Vt adjusting thermal is the brief term of the adjustment of Vt by a thermal process.

[0095] In an example, the first annealing temperature is in the range of 650° C.-700° C.

[0096] In this embodiment of the present application, the first annealing process 601 is performed after the formation of the opening 508. In other embodiments, the first annealing process 601 first annealing process 601 can be performed after step 1 and before the formation of the opening 508, as long as the threshold voltage of the metal gate MOS transistor can be adjusted to the target value.

[0097] Step 4. Referring to FIG. 5H, a first Ti layer 509 and a second TiN layer 510 are formed on the inner side surface of the opening 508 of the zeroth metal layer.

[0098] In this embodiment of the present application, step 4 corresponds to Ti/TiN of step S206 in FIG. 4.

[0099] Referring to FIG. 5I, subsequently, second annealing process 602 is performed at a second temperature. The second annealing process 602 is used for adjusting on-resistance of the metal gate MOS transistor, i.e., reducing the on-resistance of the metal gate MOS transistor by lowering the second temperature. The second temperature is lower than the first temperature to ensure that the threshold voltage of the metal gate MOS transistor is determined by the first annealing process 601. The second annealing process 602 is represented by Rext adjusting annealing of the step S206 in FIG. 4, here Rext is the external resistance, which is usually determined by the contact resistance formed by the zeroth metal layer and the bottom doped region, and Rext adjusting annealing is the process term for reducing the on-resistance of the device by lowering the annealing process temperature.

[0100] Usually, the second annealing process 602 also affects the threshold voltage of the metal gate MOS transistor. However, in this embodiment of the present application, the first annealing process 601 at a higher temperature is performed before the second annealing process 602, so that the threshold voltage of the metal gate MOS transistor is completely determined by the first annealing process 601, thereby eliminating the adverse effect of the second annealing process 602 on the threshold voltage of the metal gate MOS transistors.

[0101] In an example, the second annealing temperature is in the range of 550° C.-600° C.

[0102] Step 5. The opening 508 into the zeroth metal layer is filled with a metal material to form the zeroth metal layer.

[0103] In this embodiment of the present application, the material of the zeroth metal layer includes tungsten (W). Step 5 is the step S207 of W fill in FIG. 4.

[0104] Then BEoL step S208, i.e., a back end of line process, is performed.

[0105] In this embodiment of the present application, during the process of forming the zeroth metal layer after the metal gates 503 are formed, the annealing process of the zeroth metal layer is divided into the first annealing process 601 performed before the formation of the first TiN layer and the second TiN layer 510 and the second annealing process 602 performed after the formation of the first Ti layer 509 and the second TiN layer 510. An annealing temperature of the first annealing process 601, i.e., the first annealing temperature, is configured to be greater than an annealing temperature of the second annealing process 602, i.e., the second annealing temperature, so as to ensure that the threshold voltage of the device is determined by the first annealing process 601, such that the configuration of the second annealing temperature is not limited by the requirement of satisfying the threshold voltage and the second annealing temperature can actually be lowered to satisfy the requirement of reducing the on-resistance of the device. Therefore, this embodiment of the present application can eliminate contradictory impacts of the annealing process for the zeroth metal layer on the on-resistance and the threshold voltage, and achieve appropriate on-resistance and threshold voltage at the same time.

[0106] FIG. 6A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an NMOS device, by the method for manufacturing the metal gate MOS transistor according to the embodiment of the present application. Curve 301 represents the on-resistance when the first annealing process 601 and the second annealing process 602 according to this embodiment of the present application are performed. The first annealing temperature and the second annealing temperature in FIG. 6A are 650° C. and 600° C., respectively. In FIG. 6A, 650° C.+600° C. applied to indicate that the first annealing process 601 and the second annealing process 602 of this embodiment of the present application are performed. Curve 302 represents an on-resistance obtained after the annealing process of the zeroth metal layer at 650° C. is performed. It can be seen that the value of the curve 301 is lower by about 5%. Therefore, in this embodiment of the present application, the on-resistance of the NMOS device can still be reduced by separately configuring the annealing temperatures of the annealing process of the zeroth metal layer.

[0107] FIG. 6B is a chart comparing the threshold voltages containing metal gate NMOS transistors on four wafers which are annealed at different temperatures for the zeroth metal layer, according to the embodiment of the present application. The threshold voltages of each data group are measured on each wafer, for example the threshold voltages corresponding to data groups 303a and 303b are threshold voltages of the device on the wafers that undergo the first annealing process 601 and the second annealing process 602.

[0108] In FIG. 6B, the devices on four wafers annealed at two temperatures show their resultant threshold voltages on the Y-axis as data groups 303a and 303b annealed at 650° C.+600° C. in both the first annealing process 601 and the second annealing process 602. The threshold voltages in data groups 304a and 304b on the two wafer that undergo the annealing process of the zeroth metal layer at 650° C. The threshold voltages of the data groups 303a and 303b are substantially similar to the threshold voltages of the data groups 304a and 304b, thus the method according to this embodiment of the present application can result in the threshold voltage of the NMOS reach the target value.

[0109] FIG. 7A is a chart of on-resistance (Ron) versus the inverse of gate voltage minus threshold gate voltage (Vg−Vtgm).sup.−1 at two different annealing temperatures at zeroth-metal-layer of an PMOS device, by the method for manufacturing the metal gate MOS transistor according to the embodiment of the present application. Curve 401 represents the on-resistance when the first annealing process 601 and the second annealing process 602 according to this embodiment of the present application are performed. The first anneal temperature and the second anneal temperature are 650° C. and 600° C., respectively. In FIG. 7A, 650° C.+600° C. is applied to indicate that the first annealing process 601 and the second annealing process 602 of this embodiment of the present application are performed. Curve 402 represents an on-resistance obtained after the annealing process of the zeroth metal layer at 650° C. is performed. The value of the curve 401 is lower by about 10%. Therefore, in this embodiment of the present application, the on-resistance of the PMOS device can still be reduced by separately configuring the annealing temperatures of the annealing process on the zeroth metal layer.

[0110] FIG. 7B is a chart comparing the threshold voltages containing metal gate PMOS transistors on two wafers which are annealed at different temperatures for the zeroth metal layer, according to the embodiment of the present application. In FIG. 7B the devices on four wafers annealed at two temperatures show their resultant threshold voltages on the Y-axis as data groups 303a and 303b annealed at 650° C.+600° C. in both the first annealing process 601 and the second annealing process 602. The threshold voltages of data groups are measured for each wafer, wherein the threshold voltages for data groups 403a and 403b from the respective wafers that undergo the first annealing process 601 and the second annealing process 602 of this embodiment of the present application. In FIG. 7B, 650° C.+600° C. is applied to indicate that the first annealing process 601 and the second annealing process 602. The threshold voltages corresponding to data groups 404a and 404b are threshold voltages of the device from the wafers that undergo the annealing process of the zeroth metal layer at 650° C. It can be seen that the threshold voltages of the data groups 403a and 403b are substantially similar to the threshold voltages of the data groups 404a and 404b, thus the method according to this embodiment of the present application enables the PMOS devices reach the target value of the threshold voltage.

[0111] The present application is described in detail above via specific embodiments, which, however, are not intended to limit the present application. Without departing from the principles of the present application, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present application.