TUNABLE ELECTRICAL RESISTOR

Abstract

An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer. The electrical resistor element further comprises a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

Claims

1. An electrical resistor element with tunable resistance, comprising: a first contact electrode; a second contact electrode; a ferroelectric layer arranged between the first contact electrode and the second contact electrode, the ferroelectric layer comprising: a first area having a first polarization direction; a second area having a second polarization direction, the first polarization direction being different to the second polarization direction; and a domain wall between the first area and the second area; a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer; and a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

2. An electrical resistor element according to claim 1, further comprising a second pinning element configured to stabilize the second polarization direction of the ferroelectric layer.

3. An electrical resistor element according to claim 1, wherein the control circuit is configured to: increase the resistance of the resistor element by applying electrical pulses of a first polarity; and decrease the resistance of the resistor element by applying electrical pulses of a second polarity, the second polarity being opposite to the first polarity.

4. An electrical resistor element according to claim 1, wherein the tunable resistance of the electrical resistor element is defined by the position of the domain wall.

5. An electrical resistor element according to claim 4, wherein the control circuit is configured to control the position of the domain wall by the pulse length of the electrical pulses.

6. An electrical resistor element according to claim 1, wherein the ferroelectric layer is embodied as ferroelectric thin film having a thickness of less than 10 nm.

7. An electrical resistor element according to claim 6, wherein: the first area has a first tunnel resistance and the second area has a second tunnel resistance; and the resistor element is configured to tune the resistance by the volume ratio of the first area having the first tunnel resistance and the second area having the second tunnel resistance.

8. An electrical resistor element according to claim 1, wherein the domain wall is a conductive domain wall.

9. An electrical resistor element according to claim 8, wherein the tunable resistance is determined by a total resistance of a serial arrangement of the first contact electrode, the conductive domain wall and the second contact electrode.

10. An electrical resistor element according to claim 8, wherein the conductive domain wall has side portions and a front portion and wherein the resistor element is configured to tune the resistance by the length of the side portions of the conductive domain wall.

11. An electrical resistor element according to claim 8, wherein the first contact electrode and the second contact electrode are embodied as resistive electrodes and wherein the resistor element is configured to tune the resistance by a length of a current path within the first and the second contact electrodes.

12. An electrical resistor element according to claim 1, comprising a piezoresistive layer adjacent to the ferroelectric layer, wherein the ferroelectric domain wall is configured to apply strain on the piezoresistive layer, thereby changing the electrical resistance of the piezoresistive layer and of the electrical resistor element.

13. An electrical resistor element according to claim 2, wherein: the first pinning element comprises a first set of static pinning electrodes configured to polarize a first ferroelectric pinning layer in the first polarization direction; and the second pinning element comprises a second set of static pinning electrodes configured to polarize a second ferroelectric pinning layer in the second polarization direction.

14. An electrical resistor element according to claim 2, wherein: the first pinning element comprises a first polarized interface configured to pole a first ferroelectric pinning layer in the first polarization direction and the second pinning element comprises a second polarized interface configured to pole a second ferroelectric pinning layer in the second polarization direction.

15. An electrical resistor element according to claim 3, wherein: the first pinning element comprises a first coupling electrode; the second pinning element comprises a second coupling electrode; the electrical resistor element is configured to apply, the electrical pulses of the first polarity in parallel to the first pinning element and to the first contact electrode; and the electrical pulses of the second polarity in parallel to the second pinning element and to the first contact electrode; and wherein a coupling resistance of the first coupling electrode and of the second coupling electrode is lower than a coupling resistance of the first contact electrode.

16. An electrical resistor element according to claim 1, wherein the ferroelectric layer comprises a material selected from the group consisting of: BaTiO3, BiFeO3, PbTiO3, LiNbO3, Pb[Zr.sub.xTi.sub.1-x]O.sub.3 and ferroelectric polymers.

17. A neuromorphic computing system, comprising: a plurality of electrical resistor elements as synapses each of the plurality of electrical resistor elements having tunable resistance, and each of the plurality of electrical resister elements including: a first contact electrode; a second contact electrode; a ferroelectric layer arranged between the first contact electrode and the second contact electrode, the ferroelectric layer comprising: a first area having a first polarization direction; a second area having a second polarization direction, the first polarization direction being different to the second polarization direction; and a domain wall between the first area and the second area; a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer; and a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

18. A method for tuning the resistance of an electrical resistor element, comprising: stabilizing, by a first pinning element, a first polarization direction of a ferroelectric layer of an electrical resistor element; and tuning, by a control circuit, a resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer, thereby moving a ferroelectric domain wall; the electrical resistor element, including: a first contact electrode; a second contact electrode; the ferroelectric layer arranged between the first contact electrode and the second contact electrode, the ferroelectric layer including: a first area having the first polarization direction; a second area having a second polarization direction, the first polarization direction being different to the second polarization direction; and the domain wall being between the first area and the second area.

19. A method according to claim 18, the method comprising: increasing the resistance of the resistor element by applying electrical pulses of a first polarity; and decreasing the resistance of the resistor element by applying electrical pulses of a second polarity, the second polarity being opposite to the first polarity.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0031] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. The various features of the drawings are not to scale as the illustrations are for clarity in facilitating one skilled in the art in understanding the invention in conjunction with the detailed description. The drawing are discussed forthwith below.

[0032] FIGS. 1a, 1b and 1c illustrate an electrical resistor element according to an embodiment of the invention in different resistance states.

[0033] FIGS. 2a, 2b and 2c illustrate an electrical resistor element according to another embodiment of the invention in different resistance states.

[0034] FIG. 3 shows a top view of an electrical resistor element according to an embodiment of the invention.

[0035] FIGS. 4a and 4b show 3-dimensional views of an electrical resistor element according to another embodiment of the invention.

[0036] FIG. 5 shows an electrical resistor element with a first configuration of pinning elements.

[0037] FIG. 6 shows an electrical resistor element with a second configuration of pinning elements.

[0038] FIG. 7 shows an electrical resistor element with a third configuration of pinning elements.

[0039] FIG. 8 shows an electrical resistor element with a fourth configuration of pinning elements.

[0040] FIG. 9 shows a block diagram of an exemplary design flow used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture.

[0041] FIG. 10 shows a neuromorphic computing system according to an embodiment of the invention.

[0042] FIG. 11 is a flow chart depicting a method for tuning the resistance of an electrical resistor element.

DETAILED DESCRIPTION

[0043] FIGS. 1a, 1b and 1c illustrate an electrical resistor element according to an embodiment of the invention in different resistance states.

[0044] Referring to FIG. 1a, an electrical resistor element 100 is shown having a first contact electrode 101, a second contact electrode 102 and a ferroelectric layer 103 arranged between the first contact electrode 101 and the second contact electrode 102.

[0045] The ferroelectric layer 103 comprises a first area 104 having a first polarization direction 105 and a second area 106 having a second polarization direction 107. The first polarization direction 105 is different to the second polarization direction 107 and in this example opposite to the second polarization direction 107. According to other embodiments, the first polarization direction 105 could be pointing in a +45 direction and the second polarization direction in a +135 direction (when looking at the cross sections).

[0046] The first area 104 and the second area 106 are separated by a domain wall 108.

[0047] The electrical resistor element 100 further comprises a first pinning element 111 configured to stabilize the first polarization direction 105 of the ferroelectric layer 103 and a second pinning element 112 configured to stabilize the second polarization direction 107 of the ferroelectric layer 103.

[0048] Furthermore, a control circuit 120 is configured to tune the resistance of the electrical resistor element 100 by applying electrical pulses to the ferroelectric layer 103 such that the ferroelectric domain wall 108 is moved.

[0049] The ferroelectric layer 103 is embodied as ferroelectric thin film. According to preferred embodiments, the thickness d of the ferroelectric layer is less than 10 nm. According to further preferred embodiments, the thickness d is less than 5 nm. According to further preferred embodiments, the thickness d is less than 2 nm.

[0050] According to the embodiments as illustrated in FIGS. 1a to 1c, the tunnel resistance of the electrical resistor element 100 is determined as resistance of the resistor element. The ferroelectric layer 103 has different specific tunnel resistances in dependence on the polarization direction and hence the first area 104 has a different tunnel resistance than the second area 106.

[0051] According to embodiments, the total resistance of the ferroelectric layer 103 may be assessed as follows.

[0052] It may be assumed/estimated that the first area 104 has a first tunnel resistance R.sub.tunnel1=.sub.tunnelup*L.sub.up1*A and the second area has a second tunnel resistance R.sub.tunnel2=.sub.tunneldown*L.sub.down1*A.

[0053] .sub.tunnelup is the specific resistance of the first area 104 having the first polarization direction 105 and .sub.tunneldown is the specific resistance of the second area 106 having the second polarization direction 107. L.sub.up1 is the length of the first area 104 in the x-direction and L.sub.up2 the length of the second area 106 in the x-direction. A is the cross section of the ferroelectric layer 103 in the y-z-plane.

[0054] The total tunnel resistance R.sub.tunneltot of the ferroelectric layer 103 between the first contact electrode 101 and the second contact electrode 102 may then be calculated as a parallel arrangement of the first tunnel resistance R.sub.tunnel1 and the second tunnel resistance R.sub.tunnel2:

[00001]$R_{\mathrm{tunneltot}}=\frac{1}{\left(\frac{1}{R_{{\mathrm{tunnel}}_1}}+\frac{1}{R_{{\mathrm{tunnel}}_2}}\right)}$

[0055] For reading out the respective tunnel resistance, a voltage V.sub.probe is applied to the first contact electrode 101 and the corresponding tunnel current I.sub.tunnel is measured.

[0056] In order to tune the resistance of the electrical resistor element 100, electrical pulses are applied to the first contact electrode 101. The direction of the resistance change may be determined by the polarity of the voltage pulse. This is illustrated in FIGS. 1b and 1c. In the following it is assumed that .sub.tunnelup>.sub.tunneldown. Furthermore, the tunnel resistances R.sub.tunneltot of the electrical resistor element 100 of FIGS. 1a, 1b and 1c are denoted as R.sub.1, R.sub.2 and R.sub.3.

[0057] Some background information about ferroelectric tunnel resistors may be found in the document by Chanthbouala et al., A ferroelectric memristor, Nat. Materials 2012.

[0058] FIG. 1b shows the electrical resistor element 100 after a positive voltage pulse 131 of a positive polarity has been applied. The positive voltage pulse 131 has shifted the domain wall 108 to the right. Accordingly, the first area 104 and its corresponding length L.sub.up2 have been increased as well as the resistance R.sub.2 of the electrical resistor element 100.

[0059] FIG. 1c shows the electrical resistor element 100 after a negative voltage pulse 132 of a negative polarity has been applied. The negative voltage pulse 132 has shifted the domain wall 108 back to the left. Accordingly, the first area 104 and its corresponding length L.sub.up2 have been decreased as well as the resistance R.sub.3 of the electrical resistor element 100.

[0060] In summary, R.sub.1R.sub.3R.sub.2.

[0061] As illustrated above, the resistor element is configured to tune the resistance by the volume ratio of the first area having the first tunnel resistance and the second area having the second tunnel resistance. By shifting the domain wall 108, this volume ratio can be changed. Hence the tunable resistance of the electrical resistor element 100 is defined by the position of the domain wall 108.

[0062] According to embodiments, the control circuit 120 can control the position of the domain wall 108 by the pulse length PL of the electrical pulses. The longer the pulse length PL, the greater the resistance change in the corresponding direction. Alternatively, a series of (short) pulses may be used to change the resistance.

[0063] FIGS. 2a, 2b and 2c illustrate an electrical resistor element according to another embodiment of the invention in different resistance states. According to this embodiment, the domain wall is embodied as conductive domain wall. Some background information about ferroelectric layers comprising domain walls may be found in the document by Crassous et al., Polarization charge as a reconfigurable quasi-dopant in ferroelectric thin films, Nature Nanotechnology 10, 614-618, 2015.

[0064] Referring to FIG. 2a, an electrical resistor element 200 is shown having a first contact electrode 201, a second contact electrode 202 and a ferroelectric layer 203 arranged between the first contact electrode 201 and the second contact electrode 202.

[0065] The ferroelectric layer 203 comprises a first area 204 having a first polarization direction 205 and a second area 206 having a second polarization direction 207. The first polarization direction 205 is opposite to the second polarization direction 207.

[0066] The first area 204 and the second area 206 are separated by a domain wall 208. The domain wall 208 is embodied as conductive domain wall.

[0067] The electrical resistor element 200 further comprises a first pinning element 211 configured to stabilize the first polarization direction 205 of the ferroelectric layer 203 and a second pinning element 212 configured to stabilize the second polarization direction 207 of the ferroelectric layer 203.

[0068] Furthermore, a control circuit 220 is configured to tune the resistance of the electrical resistor element 200 by applying electrical pulses to the ferroelectric layer 203 such that the conductive ferroelectric domain wall 208 is moved.

[0069] For reading out the respective tunnel resistance, a voltage V.sub.probe is applied to the first contact electrode 201 and the corresponding current I.sub.DW through the conductive domain wall 208 is measured. The tunable resistance of the resistive memory element 200 is determined by the total resistance of the serial arrangement of the first contact electrode 201, the conductive domain wall 208 and the second contact electrode 202.

[0070] According to this embodiment, the first contact electrode 201 and the second contact electrode 202 are embodied as resistive electrodes, i.e. they have a predefined resistance, preferably a predefined minimum resistance. The predefined resistance is chosen such that it allows to tune the resistance of the electrical resistor element 200 by the length of the current path within the first contact electrode 201 and the second contact electrode 202. The current path 240 is illustrated by a dotted line. The current path 240 extends from a contact point 245a, at which the first contact electrode 201 is contacted by the control circuit or (unit 220) and a contact point 245b at which the second contact electrode 202 is contacted by the control circuit 220. The current path 240 comprises a sub-path 241 within the first contact electrode 201, a sub-path 248 through the conductive domain wall 208 and a sub-path 242 within the second contact electrode 202.

[0071] The total tunable resistance R.sub.tune of the electrical resistor element 200 is given by

R.sub.tune=2.sub.contactL.sub.1A.sub.1+.sub.domain wallL.sub.2A.sub.2,

wherein .sub.contact is the specific resistance of the first contact electrode 201 and the second contact electrode 202, L.sub.1 is the length of the sub-path 241 and the length of the sub-path 242, .sub.domain wall is the specific resistance of the conductive domain wall 208, L.sub.2 is the length of the sub-path 248, A.sub.1 the cross section of the first contact electrode 201 and the second contact electrode 202 in the y-z-plane and A.sub.2 the cross section of the conductive domain wall 208 in the x-y-plane.

[0072] In order to tune the resistance of the electrical resistor element 200, electrical pulses are applied to the first contact electrode 201. The direction of the resistance change may be determined by the polarity of the voltage pulse. This is illustrated in FIGS. 2b and 2c. In the following the total tunable resistances of the electrical resistor element 200 of FIGS. 1a, 1b and 1c are denoted as R.sub.1, R.sub.2 and R.sub.3.

[0073] FIG. 2b shows the electrical resistor element 200 after a positive voltage pulse 231 of a positive polarity has been applied. The positive voltage pulse 231 has shifted the domain wall 208 to the right. Accordingly, the first area 204 and the its corresponding length L.sub.1 have been increased as well as the resistance R.sub.2 of the electrical resistor element 100.

[0074] FIG. 2c shows the electrical resistor element 200 after a negative voltage pulse 232 of a negative polarity has been applied. The negative voltage pulse 232 has shifted the domain wall 208 back to the left. Accordingly, the first area 204 and its corresponding length L.sub.1 have been decreased as well as the resistance R.sub.3 of the electrical resistor element 200.

[0075] In summary, R.sub.1R.sub.3R.sub.2.

[0076] Hence, according to the embodiments as illustrated in FIGS. 2a, 2b and 2c, the resistance of the electrical resistor element 200 can be tuned by the length L.sub.1. Accordingly, the tunable resistance of the electrical resistor element 200 is defined by the position of the domain wall 208.

[0077] According to embodiments, the control circuit 220 can control the position of the conductive domain wall by the pulse length PL of the electrical pulses. The longer the pulse length PL, the greater the resistance change in the corresponding direction. Alternatively, a series of (short) pulses may be used to change the resistance.

[0078] FIG. 3 shows a top view of an electrical resistor element 300 according to an embodiment of the invention. The electrical resistor element 300 comprises a ferroelectric layer 303 that is arranged between a first contact electrode and a second contact electrode which are not shown in FIG. 3 for ease of illustration. The ferroelectric layer 303 is surrounded by a ferroelectric layer 350, which is polarized in a first polarization direction (in this example down) and a ferroelectric layer 351, which is polarized in a second polarization direction (in this example up). The polarization of the ferroelectric layers 350, 351 is fixed by not shown pinning elements and will not be changed during the tuning of the resistance. The inner ferroelectric layer 303 comprises a first area 304 having a first polarization direction (down) and a second area 306 having a second, opposite polarization direction (up). The ferroelectric layer 303 comprises a ferroelectric domain wall 308, which has side portions 308b and 308c and a front portion 308a. The resistance of the electrical resistor element 300 between the not shown first and second contact electrodes (top/bottom contact electrodes) is dependent on the total length of the domain wall 308. Accordingly, the resistance can be tuned by the length L.sub.1 of the side portions 308b and 308c of the ferroelectric domain wall 308.

[0079] FIGS. 4a and 4b shows two 3-dimensional views of an electrical resistor element 400 according to another embodiment of the invention.

[0080] The electrical resistor element 400 comprises a first contact electrode 401, a second contact electrode 402 and a ferroelectric layer 403 arranged between the first contact electrode 401 and the second contact electrode 402. The electrical resistor element 400 comprises a piezoresistive layer 450 adjacent to the ferroelectric layer 403, the first contact electrode 401 and the second contact electrode 402. The ferroelectric layer 403 comprises areas of different polarization separated by a domain wall 408, which is schematically indicated by a dotted line.

[0081] The ferroelectric domain wall 408 applies strain on the piezoresistive layer 450. This changes the electrical resistance of the piezoelectric layer 450 and hence of the electrical resistor element 400. In other words, the piezoelectric layer 450 provides a bypath or shortcut between the first contact electrode 401 and the second contact electrode 402 at the position of the domain wall 408.

[0082] FIGS. 5 to 8 show electrical resistor elements 500, 600, 700 and 800 with different configurations of pinning elements.

[0083] The basic configurations of the resistor elements 500, 600, 700 and 800 is the same. More particularly, the resistor elements 500, 500, 700 and 800 comprise a first contact electrode 501, a second contact electrode 502 and a ferroelectric layer 503 arranged between the first contact electrode 501 and the second contact electrode 502.

[0084] The ferroelectric layer 503 comprises a first area 504 having a first polarization direction 505 and a second area 506 having a second polarization direction 507. The first area 504 and the second area 506 are separated by a domain wall 508.

[0085] Referring now to FIG. 5, the resistor element 500 comprises a first pinning element 511. The first pinning element 511 comprises a first set of static pinning electrodes 540 and a ferroelectric pinning layer 541. The second pinning element 512 comprises a second set of static pinning electrodes 542 and a ferroelectric pinning layer 543. The first set of static pinning electrodes 540 polarizes the first ferroelectric pinning layer 541 in the first polarization direction and the second set of static pinning electrodes 542 polarizes the second ferroelectric pinning layer 543 in the second polarization direction. The first pinning element 511 and the second pinning element 512 apply a higher coercive field on the ferroelectric layer 503 than the electrical pulses applied by the control unit.

[0086] Referring now to FIG. 6, the resistor element 600 comprises a first pinning element 611. The first pinning element 611 comprises a first polarized interface 640 which poles a first ferroelectric pinning layer 641 in the first polarization direction. The first polarized interface 640 is established at the boundary surface between the ferroelectric pinning layer 641 and the ferroelectric layer 503. In addition, the resistor element 600 comprises a second pinning element 612. The second pinning element 612 comprises a second polarized interface 642 which poles a second ferroelectric pinning layer 643 in the second polarization direction. The second polarized interface 642 is established at the boundary surface between the ferroelectric pinning layer 643 and the ferroelectric layer 503. The polarized interfaces 640, 642 may be embodied e.g. as dipoles established at the boundary surfaces between the ferroelectric pinning layers 641, 643 and the ferroelectric layer 503.

[0087] Referring now to FIG. 7, the resistor element 700 comprises a first pinning element 711. The first pinning element 711 comprises a first polarized interface 740, which poles a first ferroelectric pinning layer 741 in the first polarization direction. In addition, the resistor element 700 comprises a second pinning element 712. The second pinning element 712 comprises a second polarized interface 742, which poles a second ferroelectric pinning layer 743 in the second polarization direction. The polarized interface 740 is established at a boundary surface between the ferroelectric pinning layer 741 and a first bottom layer 747. The polarized interface 742 is established at a boundary surface between the ferroelectric pinning layer 743 and a second bottom layer 748. According to some embodiments, the first bottom layer 747 and the second bottom layer 748 may be embodied of different materials to provide polarized interfaces of different polarities. According to other embodiments, the first ferroelectric pinning layer 741 and the second ferroelectric pinning layer 743 may comprise different materials to provide polarized interfaces of different polarities.

[0088] Referring now to FIG. 8, the resistor element 800 comprises a first pinning element 811 and a second pinning element 812. The first pinning element 811 comprises a first ferroelectric pinning layer 841 and a first coupling electrode 840. The second pinning element 812 comprises a second ferroelectric pinning layer 843 and a second coupling electrode 842. The first coupling electrode 840 comprises a layer 840a with a low resistance and the second coupling electrode 842 comprises a layer 842a with low resistance.

[0089] The first coupling electrode 840 is coupled via a diode 850 to an input port 860 and the second coupling electrode 842 is coupled via a diode 851 to the input port 860. The input port 860 is configured to receive the electrical pulses to tune the resistance of the resistor element 800. Electrical pulses of a negative polarity are applied to the first pinning element 811 via the diode 850 and in parallel to the first contact electrode 501. Electrical pulses of a positive polarity are applied to the second pinning element 812 via the diode 851 and in parallel to the first contact electrode 501. The first contact electrode 501 comprises a layer with a high resistance. High resistance in this context shall mean a higher resistance than the low resistance of the layers 840a and 842a. As a result, the coupling resistance of the first coupling electrode 840 and of the second coupling electrode 842 is lower than the coupling resistance of the first contact electrode 501. The lower coupling resistance of the first coupling electrode 840 and the second coupling electrode 842 results in an increased electrical field of the electrical pulses in the area of the first coupling electrode 840 or the second coupling electrode 842. This stabilizes the corresponding polarization.

[0090] FIG. 9 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown e.g. in FIGS. 1 to 8. The design structures processed and/or generated by design flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).

[0091] Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera Inc. or Xilinx Inc.

[0092] FIG. 9 illustrates multiple such design structures including an input design structure 920 that is preferably processed by a design process 910. Design structure 920 may be a logical simulation design structure generated and processed by design process 910 to produce a logically equivalent functional representation of a hardware device. Design structure 920 may also or alternatively comprise data and/or program instructions that when processed by design process 910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 920 may be accessed and processed by one or more hardware and/or software modules within design process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIGS. 1 to 8. As such, design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

[0093] Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIGS. 1-8 to generate a Netlist 980 which may contain design structures such as design structure 920. Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.

[0094] Design process 910 may include hardware and software modules for processing a variety of input data structure types including Netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

[0095] Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in FIGS. 1 to 8. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in FIGS. 1-6, 8 and 10.

[0096] Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in FIGS. 1 to 8. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

[0097] FIG. 10 shows a neuromorphic computing system 1000 according to an embodiment of the invention. The neuromorphic computing system 1000 comprises a plurality of electrical resistor elements, e.g. the electrical resistor elements 100 as described with reference to FIG. 1 as synapses. The weight of the synapses can be symmetrically changed by applying electrical pulses as described above.

[0098] FIG. 11 shows method steps of a method for tuning the resistance of an electrical resistor element. In the following the method is described with reference to the electrical resistor element 100 of FIG. 1.

[0099] At a step 1110, the first pinning element 111 stabilizes the first polarization direction of the ferroelectric layer 103.

[0100] At a step 1120, the second pinning element 112 stabilizes the second polarization direction of the ferroelectric layer 103.

[0101] At a step 1130, it is checked whether the resistance shall be increased or decreased.

[0102] If the resistance shall be increased, the control circuit 120 applies at a step 1140 electrical pulses of the first polarity. As a result, the ferroelectric domain wall 108 moves in a first direction.

[0103] If the resistance shall be decreased, the control circuit 120 applies at a step 1150 electrical pulses of a second opposite polarity. As a result, the ferroelectric domain wall 108 moves in a second opposite direction.

[0104] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.