Method for limiting the current in devices of “H-bridge” type

Abstract

A method for limiting the current in a device of H-bridge type having a plurality of transistors including the following steps: detection of a failure in a transistor from among the plurality of transistors; disabling of the transistor in which a failure has been detected; detection in the transistors opposite to the transistor, of the discharging of the energy accumulated at output; and disabling of the other transistors of the plurality of transistors. A system for limiting the current in a device of H-bridge type having a plurality of transistors is also disclosed.

Claims

1. A method for limiting the current in an H-bridge device including a plurality of transistors (T1, T2, T3, T4), the method comprising: detecting a failure on one transistor from among said plurality of transistors; turning off said transistor on which a failure has been detected; after said transistor is turned off, detecting, on the transistors opposite said transistor, the discharge of the accumulated output power; and turning off the other transistors of said plurality of transistors.

2. The method as claimed in claim 1, wherein said failure is linked to a current having an excessively high magnitude.

3. The method as claimed in claim 1, wherein said failure is linked to a thermal phenomenon.

4. The method as claimed in claim 1, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a current detector on the opposite transistors.

5. The method as claimed in claim 1, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a voltage detector on the opposite transistors.

6. A system for limiting the current in an H-bridge device including a plurality of transistors (T1, T2, T3, T4), comprising means for: detecting a failure on one transistor from among said plurality of transistors; turning off said transistor on which a failure has been detected; after said transistor is turned off, detecting, on the transistors opposite said transistor, the discharge of the accumulated output power; and turning off the other transistors of said plurality of transistors.

7. The method as claimed in claim 2, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a current detector on the opposite transistors.

8. The method as claimed in claim 3, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a current detector on the opposite transistors.

9. The method as claimed in claim 2, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a voltage detector on the opposite transistors.

10. The method as claimed in claim 3, wherein said detection, on the transistors opposite said transistor, of the discharge of the accumulated output power is performed by a voltage detector on the opposite transistors.

11. A method for limiting the current in an H-bridge device including a plurality of transistors (T1, T2, T3, T4), the method comprising: detecting a failure on a transistor from among said plurality of transistors; turning off said transistor on which a failure has been detected, while maintaining other transistors of said plurality of transistors ON; detecting, on the other transistors of said plurality of transistors, the discharge of the accumulated output power; and in response to detecting the discharge, turning off the other transistors of said plurality of transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects of the invention will be better understood with the aid of the description, given hereinafter purely by way of explanation, of one embodiment of the invention, with reference to the figures, in which:

(2) FIG. 1 illustrates the method according to the present invention in one embodiment;

(3) FIG. 2 illustrates a system according to the prior art; and

(4) FIG. 3 illustrates the system implementing the method according to the present invention, in one embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) FIG. 1 illustrates the method according to an aspect of the present invention in one embodiment.

(6) The present invention, as illustrated in FIG. 1, relates to a method for limiting the current in an H-bridge device including a plurality of transistors T1, T2, T3, T4, including the following steps: Detecting 10 a failure on one transistor T from among said plurality of transistors T1, T2, T3, T4; Turning off 20 said transistor T on which a failure has been detected; Detecting 30, on the transistors opposite said transistor T, the discharge of the accumulated output power; and Turning off 40 the other transistors of said plurality of transistors T1, T2, T3, T4.

(7) In one embodiment, the failure is linked to a current having an excessively high magnitude, termed overcurrent.

(8) In one embodiment, the failure is linked to a thermal phenomenon.

(9) In one embodiment, the detection, on the transistors opposite said transistor T, of the discharge of the accumulated output power is performed by a current detector on the opposite transistors.

(10) In one embodiment, the detection, on the transistors opposite said transistor T, of the discharge of the accumulated output power is performed by a voltage detector on the opposite transistors.

(11) An aspect of the present invention also relates to a system for limiting the current in an H-bridge device including a plurality of transistors T1, T2, T3, T4. This system includes means for: Detecting a failure on one transistor T from among said plurality of transistors T1, T2, T3, T4; Turning off said transistor T on which a failure has been detected; Detecting, on the transistors opposite said transistor T, the discharge of the accumulated output power; and Turning off the other transistors of said plurality of transistors T1, T2, T3, T4.

(12) A description is given hereinafter of one exemplary embodiment of the present invention. Consideration is given to a device including four transistors T1, T2, T3 and T4. If a current having an excessively high magnitude is detected in the transistor T1, the transistor T1 is turned off, but the transistors T2, T3 and T4 are not turned off. To this end, detection is awaited, on the transistors opposite the transistor T1, of the discharge of the accumulated output power. It is only at this moment that the other transistors are turned off, in contrast to the prior art solutions. This method is similar if a current having an excessively high magnitude is detected in the transistor T2, T3 or T4.

(13) FIG. 3 illustrates the system implementing the method according to an aspect of the present invention, in one embodiment. In contrast to the prior art solution shown in FIG. 2, in the event of detection of a current having an excessively high magnitude, termed overcurrent, the transistors are not all turned off at the same time. To this end, detection is awaited, on the transistors opposite the first transistor, of the discharge of the accumulated output power.

(14) Thus, the method according to an aspect of the present invention makes it possible to eliminate or very greatly reduce freewheeling diode injection in the event of detection of a current having an excessively high magnitude, termed overcurrent, or of a thermal phenomenon outlined above.

(15) The method according to an aspect of the present invention makes it possible to implement a semiconductor process with low immunity to substrate injection.

(16) The method according to an aspect of the present invention also makes it possible to reduce phenomena, termed overshoot, of the supply voltage, and therefore to reduce the decoupling capacitances.

(17) An aspect of the present invention is applicable to all types of circuits having high sides or circuits having a plurality of MOSs with freewheeling diode phases.

(18) The invention is described above by way of example. It is understood that those skilled in the art are able to produce various variants of the invention without however departing from the scope of the patent.