IMAGING PIXEL TO MITIGATE CROSS-TALK EFFECTS

Abstract

An imaging pixel (2) to mitigate cross-talk effects comprises a voltage supply node (VN) to receive a supply voltage (VDD), and an output node (ON) to provide a pixel output signal. The imaging pixel (2) further comprises a photosensitive element (10), and a source follower transistor (31) having a control node coupled to the photosensitive element (10). The source follower transistor (31) is interposed between the voltage supply node (VN) and the output node (ON). The imaging pixel (2) comprises a clamping circuit (20) being interposed between the voltage supply node (VN) and the output node (ON).

Claims

1. An imaging pixel to mitigate cross-talk effects, comprising: a voltage supply node (VN) to receive a supply voltage (VDD); an output node (ON) to provide a pixel output signal, a photosensitive element (10); a source follower transistor (31) having a control node coupled to the photosensitive element (10), the source follower transistor (31) being interposed between the voltage supply node (VN) and the output node (ON); and a clamping circuit (20) being interposed between the voltage supply node (VN) and the output node (ON).

2. The imaging pixel of claim 1, comprising: a selection transistor (32) to select the imaging pixel (2) for reading out the pixel output signal, the selection transistor (32) being interposed between the source follower transistor (31) and the output node (ON).

3. The imaging pixel of claim 1, wherein the clamping circuit (20) is interposed between the voltage supply node (VN) and an internal node (IN) of the imaging pixel (2), the internal node (IN) being located between the source follower transistor (31) and the selection transistor (32).

4. The imaging pixel of claim 3, wherein the clamping circuit (20) is formed by a second source follower transistor (21) being interposed between the voltage supply node (VN) and the internal node (IN).

5. The imaging pixel of claim 2, wherein the clamping circuit (20) is arranged in parallel to a series connection of the source follower transistor (31) and the selection transistor (32).

6. The imaging pixel of claim 5, wherein the clamping circuit (20) is formed by a second source follower transistor (21) and a second selection transistor (22).

7. The imaging pixel of claim 6, wherein the selection transistor (32) and the second selection transistor (22) are arranged to be controlled by the same control signal.

8. The imaging pixel of claim 6, wherein the source follower transistor (31) and the second source follower transistor (21) are configured to be matched to each other.

9. An imaging sensor, comprising: a pixel array (40) including a plurality of the imaging pixels (2) as claimed in claim 1, wherein the pixel array (40) includes a plurality of column lines (41) and row lines (42), wherein the imaging pixels (2) are arranged in rows and columns of the pixel array (40) such that each row of the imaging pixels (2) is connected to a respective row line (42) to receive row control signals (RS), and each column of the imaging pixels (2) is connected to a respective column line (41) for reading out the pixel output signals from the imaging pixels (2) connected to the respective column line (41).

10. The imaging sensor of claim 9, comprising: a plurality of bias circuitries (80), wherein each of the bias circuitries (80) is connected to a respective column line (41) for supplying bias signals to the imaging pixels (2) connected to the respective column line (41).

11. The imaging sensor of claim 9, wherein each of the second source follower transistors (21) of the imaging pixels (2) comprises a clamp control node to receive a clamping control signal (VC1, . . . , VCn) to control an operation state of the respective second source follower transistor (21).

12. The imaging sensor of claim 11, comprising: a clamp control circuit (90) being configured to provide the respective clamping control signal (VC1, . . . , VCn) for each row (42) of the imaging pixels (2).

13. The imaging sensor of claim 11, comprising: a clamp control circuit (90) being configured to provide the respective clamping control signal (VC1, . . . , VCn) for each column (41) of the imaging pixels (2).

14. The imaging sensor of claim 11, comprising: a clamp control circuit (90) being configured to provide a respective clamping control signal (VC1, . . . , VCn) for each imaging pixel (2) of the pixel array (40).

15. An electronic device, comprising: an imaging sensor (1) as claimed in claim 9, wherein the electronic device (3) is embodied as a camera or a smartphone or a tablet computer or a video surveillance system or an automotive imaging system, and wherein the imaging sensor (1) is embodied as a photosensitive component of the electronic device (3).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are included to provide further understanding, and are incorporated in, and constitute a part of, the specification. As such, the disclosure will be more fully understood from the following detailed description, taken in conjunction with the accompanying figures in which:

[0036] FIG. 1 shows an embodiment of an imaging sensor comprising imaging pixels arranged in rows and columns of a pixel array;

[0037] FIG. 2 shows an embodiment of an imaging sensor comprising a pixel array, bias circuitries and clamping circuits according to a conventional technology;

[0038] FIG. 3 illustrates a respective voltage drop on supply lines of various rows of a pixel array for small and large photosensitive signals of imaging pixels for an imaging sensor according to a conventional technology;

[0039] FIG. 4 shows an embodiment of an imaging sensor comprising a pixel array having imaging pixels with a respective in-pixel clamping circuit;

[0040] FIG. 5 illustrates an embodiment of an imaging pixel to mitigate cross-talk effects through the supply voltage;

[0041] FIG. 6 illustrates a respective voltage drop on supply lines of various rows of a pixel array for small and large photosensitive signals of imaging pixels for an imaging sensor having imaging pixels with in-pixel clamping circuits;

[0042] FIG. 7A shows a first embodiment of an imaging sensor with a clamping control signal of imaging pixels being calibrated on a per row basis;

[0043] FIG. 7B shows an embodiment of an imaging sensor with respective clamping control signals of the imaging pixels being calibrated on a per column basis;

[0044] FIG. 7C shows an embodiment of an imaging sensor with respective clamping control signals of imaging pixels being calibrated on a per pixel basis; and

[0045] FIG. 8 shows an embodiment of an electronic device comprising an imaging sensor with imaging pixels to mitigate cross-talk effects through the supply voltage.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] FIG. 4 shows an imaging sensor 1 comprising a plurality of imaging pixels 2 being arranged in rows and columns of a pixel array 40. The pixel array 40 includes a plurality of column lines/buses 41 and row lines 42. The imaging pixels 2 are arranged in rows and columns of the pixel array 40 such that each row of the imaging pixels 2 is connected to a respective row line 42 to receive row control signals, and each column of the imaging pixels 2 is connected to a respective column line 41 for reading out the pixel output signals from the imaging pixels connected to the respective column line 41.

[0047] The imaging sensor 1 comprises a plurality of bias circuitries 80. Each of the bias circuitries 80 is connected to a respective column line 41 for supplying bias signals to the imaging pixels 2 connected to the respective column line/bus 41.

[0048] According to a possible embodiment shown in FIG. 4, the bias circuitries 80 comprise a source follower transistor 81 being controlled by control signal VBIAS, and an activation transistor 82 being controlled by control signal BIAS_EN to activate the respective bias circuitry 80 supplying bias signals, for example bias currents or bias voltages, to the respective column line 41 to which bias circuitry 80 is connected. Each bias circuitry 80 is arranged between a respective column line/bus 41 and reference potential VSS. As shown in FIG. 4, the bias circuitries 80 are located on the edge, i.e. on the top or bottom side of pixel array 40.

[0049] For reasons of simplified illustration, control circuitry 50, row control circuitry 60 and image readout/column control circuitry 70 shown in FIG. 1 have been omitted. Instead, the following will focus on the embodiment of the imaging pixels 2 included in the pixel array 40. One of the imaging pixels 2 is shown in FIG. 4 as an example for all other imaging pixels of the pixel array 40 in an enlarged view.

[0050] The imaging pixel 2 comprises a voltage supply node VN to receive a supply voltage VDD, and an output node ON to provide a pixel output signal. The imaging pixel 2 further comprises a photosensitive element 10 which may be configured as a photodiode. The photosensitive element 10 is embodied to provide a photosensitive signal VPIX. The level of the photosensitive signal VPIX is generated by the photosensitive element 10 in dependence on the brightness of light incident on photosensitive element 10.

[0051] The imaging pixel 2 further comprises a source follower transistor 31 having a control node coupled to the photosensitive element 10 to receive a photosensitive signal VPIX as control/gate signal. The source follower transistor 31 is interposed between the voltage supply node VN and the output node ON. The imaging pixel 2 further comprises a selection transistor 32 to select the imaging pixel 2 for reading out the pixel output signal of the imaging pixel. The selection transistor 32 is interposed between the source follower transistor 31 and the output node ON.

[0052] Referring to the embodiment of the imaging pixel 2 shown in FIG. 4, the source follower transistor 31 has a drain node coupled to the voltage supply node VN, a source node coupled to a drain node of selection transistor 32 and a control/gate node to receive photosensitive signal VPIX from photosensitive element 10. Selection transistor 32 has a control/gate node to receive a selection/row control signal SEL to select imaging pixel 2 for reading out the pixel output signal.

[0053] The imaging pixel 2 comprises a clamping circuit 20 to set the minimum voltage on the column line/bus 41. Referring to the embodiment of the imaging pixel 2 shown in FIG. 4, the clamping circuit 20 is arranged in parallel to a series connection of source follower transistor 31 and selection transistor 32.

[0054] The clamping circuit 20 is formed by a second source follower transistor 21 and a second selection transistor 22. Source follower transistor 21 has a drain node coupled to voltage supply node VN, a clamp control/gate node to receive a clamping control signal VC to control an operation state of the second source follower transistor 21, and a source node connected to a drain node of the second selection transistor 22. The second selection transistor 22 has a control/gate node to receive selection signal SEL to select/activate clamping circuit 20. A source node of second selection transistor 22 of clamping circuit 20 is coupled to the output node ON of imaging pixel 2.

[0055] According to a possible embodiment of the imaging pixel 2 shown in FIG. 4, selection transistor 32 and second selection transistor 22 of clamping circuit 20 are arranged to be controlled by the same control signal SEL.

[0056] According to a possible embodiment of the imaging pixel 2, source follower transistor 31 and second source follower transistor 21 of clamping circuit 20 are configured to be matched to each other. That means that pixel source follower 31 and clamp source follower 21 should have, for example, same size, close proximity, and common centroided, if possible, in order to mitigate mismatch effects.

[0057] FIG. 5 shows another embodiment of the imaging pixel 2, wherein a second selection transistor 22 of clamping circuit 20 is omitted. According to the illustrated configuration of imaging pixel 2, clamping circuit 20 is only formed by second source follower transistor 21 being interposed between voltage supply node VN and an internal node IN of imaging pixel 2. Internal node IN is located between source follower transistor 31 and selection transistor 32.

[0058] In this configuration of the imaging pixel 2 shown in FIG. 5, clamping circuit 20 is interposed between voltage supply node VN and internal node IN. In particular, as illustrated in FIG. 5, drain node of second source follower transistor 21 is coupled to voltage supply node VN, and source node of a second source follower transistor 21 of clamping circuit 20 is coupled to internal node IN of imaging pixel 2.

[0059] Referring to the concept of the imaging pixel 2 shown in FIGS. 4 and 5, instead of placing clamping circuit 20 on an edge of pixel array 40, clamping circuit 20 is moved into the imaging pixel 2. That means that clamping circuit 20 is incorporated in each imaging pixel 2 of pixel array 40, and is thus embodied as an in-pixel clamping circuit.

[0060] By having a respective clamping circuit 20 in each imaging pixel 2, the current on the power supply, and thus the voltage drop on the supply, will be constant and independent of the level of the photosensitive signal VPIX of an aggressor pixel. Aggressor pixels are those pixels that are arranged within a row of pixels on either side of victim pixels located in a central area of the pixel row. By moving the clamping circuit 20 into each imaging pixel 2, there is a constant current flow through the pixel that is independent of a signal level of photosensitive signal VPIX, leading to a constant voltage drop on the pixel array VDD supply. In conclusion, the configuration of the in-pixel clamping circuit 20 allows aggressor-dependent signal change in victim pixels (cross-talk) to be reduced in a row of the pixel array.

[0061] Benefits could be more substantial for larger pixel area sizes, where there is a larger number of columns and thus a larger possible change in voltage drop based on signal levels (in the current technology). The proposed concept of in-pixel clamping circuits could alleviate such concerns.

[0062] A similar effect could be seen if larger bias currents were to be used for the source follower transistor. In this case a clamping circuit 20 arranged on the edge of a pixel array would be diverting more current away from the pixel array. In conclusion, the in-pixel clamping circuit is even more effective if the column load current is increased, resulting in increased voltage drop change in the pixel array, or if the supply resistance in the imaging pixel is increased, for example if the source follower transistor is powered on a supply that has thin traces, or, in the case of increased array size, specifically if there are more columns in a row of the pixel array.

[0063] FIG. 6 illustrates the effect of achieving a constant voltage drop on supply lines to provide supply voltage VDD to each of the imaging pixels coupled to various row lines of the pixel array. The constant voltage drop on the various supply lines results from incorporating a respective clamping circuit 20 into each imaging pixel 2.

[0064] In particular, FIG. 6 shows, in the top three diagrams of pixel array 40, a voltage drop on supply lines to provide supply voltage VDD for imaging pixels arranged in row R1 being the row that is located furthest from bias circuitry 80, imaging pixels located in middle row R2 and imaging pixels located in row R3 being nearest to bias circuitry 80, if there are small levels of photosensitive signals in the imaging pixels. In this case bias signal/bias current provided by bias circuitry 80 is diverted to respective source follower transistor 31 of the imaging pixels. FIG. 6 shows, in the bottom three diagrams, the influence of large levels of photosensitive signals in imaging pixels on voltage drop on supply lines to provide supply voltage VDD for imaging pixels arranged in row R1, R2 and R3.

[0065] As illustrated in FIG. 6, voltage drop gradient on different supply lines in the pixel array does not change based on the level of photosensitive signal VPIX of imaging pixels arranged in a row or row position anymore, if clamping circuit 20 is embodied as an in-pixel clamping circuit of each imaging pixel of the pixel array.

[0066] The clamping control signal VC that is applied to a respective clamp control/gate node of second source follower transistor 21 of imaging pixels 2 can be driven on a per row or per column basis, or could be distributed in a 2D routing manner.

[0067] According to a possible embodiment, the imaging sensor 1 comprises a clamp control circuit 90 being configured to provide the respective clamping control signal VC1, . . . , VCn for each row 42 of pixel array 40, as illustrated in FIG. 7A. In this case the clamping control signals can be calibrated on a per row basis. According to a possible implementation, clamping control signal VC1 can be routed horizontally and different clamping control signals VC2, . . . , VCn can be applied for each horizontal route. In this case, clamp control circuit 90 may be realized as a DAC (Digital Analog Converter) with multiple taps driving multiple rows.

[0068] According to another possible embodiment to realize a calibration of the clamping control signals on a per row basis, the clamping control signals VC1, . . . , VCn could be routed both horizontally and vertically, and the global clamping control signal/clamping voltage could be changed when the next row is selected. This implementation may be realized by a fast settling DAC or buffer.

[0069] According to another possible embodiment, imaging sensor 1 may comprise a clamp control circuit 90 being configured to provide the respective clamping control signal VC1, . . . , VCn for each column 41 of imaging pixels 2, as illustrated in FIG. 7B. This configuration allows a calibration of the clamping control signals on a per column basis to be realized. In this case, the clamping control signal VC1 can be routed vertically, and different clamping control signals VC2, . . . , VCn can be applied for each vertical route. The calibration on a per column basis can be realized by a DAC with multiple taps driving multiple columns.

[0070] According to another possible embodiment of the imaging sensor 1, the clamping control signals can be calibrated on a per pixel basis. In this case, imaging sensor 1 comprises may a clamp control circuit 90 being configured to provide a respective clamping control signal VC1, . . . , VCn for each imaging pixel 2 of the pixel array 40 individually, as illustrated in FIG. 7C. In particular, clamp control circuit 90 may be configured to route clamping control signals VC1, . . . , VCn vertically with a respective different voltage level per vertical route. When a next row is selected, the new level of the clamping control signal may be selected from row control circuitry 60 which may be realized by a DAC to drive the selected row.

[0071] The proposed concept of an in-pixel clamping circuit could basically be used in any type of pixel utilizing a source follower transistor where a white clamp is also used on a per column basis. FIG. 8 shows an embodiment of an electronic device 3 comprising an imaging sensor 2. The electronic device 3 can be embodied, for example, as a camera or a smartphone or a tablet computer or a video surveillance system or an automotive imaging system. The imaging sensor 2 comprises a pixel array 40 with imaging pixels having an in-pixel clamping circuit 20 as shown in FIGS. 4 and 5. The imaging sensor 2 may be embodied as a photosensitive component of the electronic device.

[0072] The embodiments of the imaging pixel, the imaging sensor and the electronic device disclosed herein have been discussed for the purpose of familiarizing the reader with novel aspects of the design of the imaging pixel, the imaging sensor and the electronic device. Although preferred embodiments have been shown and described, many changes, modifications, equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without unnecessarily departing from the scope of the claims.

[0073] In particular, the design of the imaging pixel, the imaging sensor and the electronic device is not limited to the disclosed embodiments, and gives examples of many alternatives as possible for the features included in the embodiments discussed. However, it is intended that any modifications, equivalents and substitutions of the disclosed concepts be included within the scope of the claims which are appended hereto.

[0074] Features recited in separate dependent claims may be advantageously combined. Moreover, reference signs used in the claims are not limited to be construed as limiting the scope of the claims.

[0075] Furthermore, as used herein, the term “comprising” does not exclude other elements. In addition, as used herein, the article “a” is intended to include one or more than one component or element, and is not limited to be construed as meaning only one.

REFERENCES

[0076] 1 imaging sensor

[0077] 2 imaging pixel

[0078] 3 electronic device

[0079] 10 photosensitive element

[0080] 20 clamping circuit

[0081] 21 second source follower transistor

[0082] 22 second selection transistor

[0083] 31 source follower transistor

[0084] 32 selection transistor

[0085] 40 pixel array

[0086] 41 column line

[0087] 42 row line

[0088] 50 control circuitry

[0089] 60 row control circuitry

[0090] 70 column control circuitry

[0091] 80 bias circuitry

[0092] 90 clamping control circuit