BIOMETRIC AUTHENTICATION BASED ON LEARNING PARITY WITH NOISE

Abstract

A logic circuit for biometric authentication based on learning parity with noise. The logic circuit includes a sensor. The sensor is configured to acquire a biometric signal. The logic circuit is configured to generate a response signal from the biometric signal by implementing a finite state machine (FSM).

Claims

1. A logic circuit for biometric authentication based on learning parity with noise, the logic circuit comprising a sensor configured to acquire a biometric signal e′ comprising m bits, the logic circuit configured to generate a response signal from the biometric signal e′ by implementing a finite state machine (FSM), the FSM comprising: a first state comprising generation of an idle output; a second state comprising generation of a reliable index vector I° comprising m bits from the biometric signal e′, each bit of the reliable index vector I° comprising a respective confidence of a respective bit of the biometric signal e′; a third state comprising extraction of a subset index vector I″ from the reliable index vector I°, the subset index vector I″ comprising n non-zero bits where n≤m; a fourth state comprising generation of a modulo 2 addition vector (b′⊕e′).sub.I″ comprising n bits by performing an XOR operation on each of a plurality of selected bit pairs, each of the plurality of selected bit pairs comprising a first selected bit extracted from a respective bit of a helper data b′ according to a respective non-zero bit of the subset index vector I″ and a second selected bit extracted from the biometric signal e′ according to the respective non-zero bit; a fifth state comprising generation of a primary hash vector from a transposed inverse public key (A.sub.I″.sup.−1).sup.T comprising a primary square matrix by sequentially applying a hashing function on each row of the primary square matrix, the primary square matrix comprising a transpose of an inverse of a truncated square matrix extracted from a public key A according to the subset index vector I″, the public key A comprising an m×n matrix; a sixth state comprising verification of the public key A; a seventh state comprising verification of the transposed inverse public key (A.sub.I″.sup.−1).sup.T based on the primary hash vector simultaneously with the verification of the public key A; an eighth state comprising generation of a secret key s′ by multiplying the inverse of the truncated square matrix by the modulo 2 addition vector (b′⊕e′).sub.I″ a ninth state comprising verification of the secret key s′; and a tenth state comprising generation of the response signal by applying the hashing function to a public vector b.sub.I″′ according to the secret key s′, each respective bit of the public vector b.sub.I″′ extracted from the helper data b′ according to a respective non-zero bit of the subset index vector I″.

2. The logic circuit of claim 1, wherein the verification of the public key A comprises: obtaining a digestion of the public key A by sequentially applying the hashing function to each row of the m×n matrix; and comparing the digestion with a pre-stored digestion obtained by applying the hashing function on an original public key.

3. The logic circuit of claim 2, wherein the verification of the transposed inverse public key (A.sub.I″.sup.−1).sup.T comprises: generation of a secondary hash vector from a reloaded inverse public key comprising a secondary square matrix by sequentially applying the hashing function to each row of the secondary square matrix responsive to: applying the hashing function on a k.sup.th row of the m×n matrix where 1≤k≤m; and a k.sup.th element of the subset index vector I″ being non-zero; comparing the secondary hash vector with the primary hash vector; and comparing a multiplication result of the secondary square matrix and the k.sup.th row of the m×n matrix with a j.sup.th row of an n×n identity matrix where 1≤j≤n responsive to the secondary hash vector being equal to the primary hash vector, the k.sup.th row and the j.sup.th row associated with a j.sup.th non-zero element of the subset index vector I″.

4. The logic circuit of claim 3, wherein the verification of the secret key s′ comprises: generation of a hashed secret key h.sub.1″ by applying the hashing function on the public vector b.sub.I″′, according to the secret key s′; and comparing the hashed secret key h.sub.1″ with a pre-stored hashed key h.sub.1′.

5. The logic circuit of claim 4, further comprising a control unit configured to: transition the FSM from the first state to the second state responsive to the biometric signal e′ being acquired by the sensor; transition the FSM from the second state to the third state responsive to the reliable index vector I° being generated; transition the FSM from the third state to the fourth state responsive to the subset index vector I″ being extracted; transition the FSM from the fourth state to the fifth state responsive to the modulo 2 addition vector (b′⊕e′).sub.I″ being generated; transition the FSM from the fifth state to the sixth state responsive to the primary hash vector being generated; transition the FSM from the sixth state to the seventh state responsive to: applying the hashing function to the k.sup.th row of the m×n matrix; and the k.sup.th element of the subset index vector I″ being non-zero; transition the FSM from the sixth state to the first state responsive to a failure of the verification of the public key A; transition the FSM from the seventh state to the sixth state responsive to a success of the verification of the transposed inverse public key (A.sub.I″.sup.−1).sup.T; transition the FSM from the seventh state to the first state responsive to a failure of the verification of the transposed inverse public key (A.sub.I″.sup.−1); transition the FSM from the sixth state to the eighth state responsive to a success of the verification of the public key A; transition the FSM from the eighth state to the ninth state responsive to the secret key s′ being generated; transition the FSM from the ninth state to the eighth state responsive to an i.sup.th successive failure of the verification of the secret key s′ where i<n+1; transition the FSM from the ninth state to the first state responsive to an (n+1).sup.th successive failure of the verification of the secret key s′; transition the FSM from the ninth state to the tenth state responsive to a success of the verification of the secret key s′; and transition the FSM from the tenth state to the first state responsive to the response signal being generated.

6. The logic circuit of claim 5, further comprising: a first shift register configured to: store the helper data b′; and generate a first shifted bit by shifting the helper data b′ one bit per clock cycle; a second shift register coupled to the sensor and configured to: receive the biometric signal e′ from the sensor; and generate a second shifted bit by shifting the biometric signal e′ one bit per clock cycle; an XOR gate configured to perform an XOR operation on the first shifted bit and the second shifted bit; a third shift register configured to: store the subset index vector I″; and generate a third shifted bit by shifting the subset index vector I″ one bit per clock cycle; and a first n-bit register comprising an enable input configured to: receive the third shifted bit; and generate each respective bit of the modulo 2 addition vector (b′⊕e′).sub.I″ by loading an output of the XOR gate to a respective location in the first n-bit register once per clock cycle responsive to the third shifted bit being non-zero.

7. The logic circuit of claim 6, further comprising: a first hash unit configured to: sequentially receive each row of the primary square matrix responsive to the FSM being transitioned to the fifth state; generate the primary hash vector by sequentially applying the hashing function on the each row of the primary square matrix; generate the digestion of the public key A by sequentially applying the hashing function on each row of the m×n matrix responsive to the FSM being transitioned to the sixth state; sequentially receive each row of the secondary square matrix responsive to the FSM being transitioned to the seventh state; and generate the secondary hash vector by sequentially applying the hashing function on the each row of the secondary square matrix; and a second n-bit register coupled to the first hash unit and configured to store the primary hash vector.

8. The logic circuit of claim 7, further comprising: a third n-bit register configured to store the pre-stored digestion; and a first comparator circuit configured to: compare the secondary hash vector with the primary hash vector responsive to the secondary hash vector being generated by the first hash unit; and compare the digestion of the public key A with the pre-stored digestion responsive to the digestion of the public key A being generated by the first hash unit.

9. The logic circuit of claim 8, further comprising: a fourth n-bit register configured to receive the k.sup.th row of the m×n matrix responsive to the secondary hash vector being equal to the primary hash vector; a fifth n-bit register configured to sequentially receive each row of the secondary square matrix responsive to the secondary hash vector being equal to the primary hash vector; a first plurality of AND gates configured to generate a first n-bit vector associated with a respective row of the secondary square matrix by performing a respective bitwise AND operation on each respective bit in the fourth n-bit register and a respective bit in the fifth n-bit register; a multi-level XOR tree configured to generate a respective bit of the multiplication result by performing a modulo 2 addition on bits of the first n-bit vector; a fourth shift register coupled to the multi-level XOR tree and configured to: sequentially receive each respective bit of the multiplication result from the XOR tree at each clock cycle; and generate a fourth shifted bit by shifting the multiplication result one pit per clock cycle; a fifth shift register configured to: store the j.sup.th row of the n×n identity matrix; and generate a fifth shifted bit by circularly shifting the j.sup.th row one bit per clock cycle; and a second comparator circuit configured to compare the multiplication result with the j.sup.th row by comparing the fourth shifted bit with the fifth shifted bit.

10. The logic circuit of claim 9, further comprising: a sixth n-bit register configured to store the secret key s′; a sixth shift register coupled to the first n-bit register and configured to generate a sixth shifted bit by shifting the modulo 2 addition vector (b′⊕e′).sub.I″ one bit per clock cycle; a second plurality of AND gates configured to generate a second n-bit vector by performing bitwise AND operations on the sixth shifted bit and each bit of a respective row of the transposed inverse public key (A.sub.I″.sup.−1).sup.T at each clock cycle responsive to the FSM being transitioned to the eighth state; and a plurality of two-input XOR gates configured to: generate each bit of the secret key s′ by performing a respective bitwise XOR operation once per clock cycle on each bit of the second n-bit vector and a respective bit in the sixth n-bit register; and load each bit of the secret key s′ to a respective location in the sixth n-bit register.

11. The logic circuit of claim 10, further comprising: a second hash unit configured to generate the hashed secret key h.sub.1″ by applying the hashing function to the public vector b.sub.I″′ according to the secret key s′ responsive to the FSM being transitioned to the ninth state; and a third comparator circuit configured to compare the hashed secret key h.sub.1″ with the pre-stored hashed key h.sub.1′.

12. The logic circuit of claim 11, further comprising a third hash unit configured to generate the response signal by applying the hashing function to the public vector b′n according to the secret key s′ responsive to the FSM being transitioned to the tenth state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitation. In the figures, like reference numerals refer to the same or similar elements.

[0031] FIG. 1A shows a schematic of a logic circuit for biometric authentication based on learning parity with noise, consistent with one or more exemplary embodiments of the present disclosure.

[0032] FIG. 1B shows a block diagram of a logic circuit coupled with a processor, consistent with one or more exemplary embodiments of the present disclosure.

[0033] FIG. 1C shows a schematic of a multi-level XOR tree, consistent with one or more exemplary embodiments of the present disclosure.

[0034] FIG. 1D shows a schematic of a calculation unit, consistent with one or more exemplary embodiments of the present disclosure.

[0035] FIG. 1E shows a schematic of a hash-and-compare unit, consistent with one or more exemplary embodiments of the present disclosure.

[0036] FIG. 2 shows a schematic of a finite state machine (FSM), consistent with one or more exemplary embodiments of the present disclosure.

[0037] FIG. 3 shows a flowchart of a verification process, consistent with one or more exemplary embodiments of the present disclosure.

[0038] FIG. 4 shows a high-level functional block diagram of a computer system, consistent with one or more exemplary embodiments of the present disclosure.

DETAILED DESCRIPTION

[0039] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0040] The following detailed description is presented to enable a person skilled in the art to make and use the methods and devices disclosed in exemplary embodiments of the present disclosure. For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required to practice the disclosed exemplary embodiments. Descriptions of specific exemplary embodiments are provided only as representative examples. Various modifications to the exemplary implementations will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the scope of the present disclosure. The present disclosure is not intended to be limited to the implementations shown, but is to be accorded the widest possible scope consistent with the principles and features disclosed herein.

[0041] Herein is disclosed an exemplary logic circuit for biometric authentication based on learning parity with noise. An exemplary logic circuit may implement a finite state machine (FSM). An exemplary FSM may start by loading a biometric signal from a biometric source (such as a fingerprint of a user) and may process the biometric signal through different states to verify and generate appropriate response based on a verification result of the biometric signal. An exemplary FSM may perform only necessary calculations at each state to increase the speed of verification and reduce storage requirements. As a result, an exemplary FSM may perform biometric authentication at a higher speed and may require a less complex hardware compared to traditional biometric authentication schemes. An exemplary logic circuit may implement each state of the FSM utilizing different logic units. By a hardware implementation of biometric authentication, security of an exemplary authentication system may be improved, whereas resource requirement of the authentication process may be decreased.

[0042] FIG. 1A shows a schematic of a logic circuit for biometric authentication based on learning parity with noise, consistent with one or more exemplary embodiments of the present disclosure. An exemplary logic circuit 100 may include a sensor 102. In an exemplary embodiment, sensor 102 may be a biometric sensor, such as a fingerprint sensor which uses a grid of tiny capacitors that store electricity which is discharged only at points where fingerprint ridges touch. In an exemplary embodiment, sensor 102 may be configured to acquire a biometric signal e′. In an exemplary embodiment, biometric signal e′ may include unique data of a user (such as fingerprints) that may be converted to a digital signal with m bits.

[0043] In an exemplary embodiment, logic circuit 100 may be configured to generate a response signal h.sub.0″ from biometric signal e′ by implementing a finite state machine (FSM). In an exemplary embodiment, an FSM may refer to a mathematical model that has a number of states and performs a different action at each state. An exemplary FSM may be transitioned from one state to another based on a specific condition. As a result, an exemplary FSM may accomplish a given task after being transitioned from an initial state to a final state through different middle states.

[0044] FIG. 2 shows a schematic of an FSM, consistent with one or more exemplary embodiments of the present disclosure. An exemplary FSM 200 may include ten states. An exemplary first state 202 may include generation of an idle output. An exemplary idle output may indicate that logic circuit 100 is waiting for acquisition of biometric signal e′. In an exemplary embodiment, FSM 200 may remain at first state 202 until biometric signal e′ is acquired by sensor 102.

[0045] Referring to FIGS. 1A and 2, an exemplary logic circuit may include a control unit 104. In an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from first state 202 to a second state 204 responsive to biometric signal e′ being acquired by sensor 102. In an exemplary embodiment, control unit 104 may generate an acknowledgement signal ack when biometric signal e′ is acquired by sensor 102 to initiate second state 204. In an exemplary embodiment, a “control unit” may refer to a hardware unit that may be programmed (for example, via programmable hardware interconnects) to perform certain functions (such as functions described in the present disclosure) of a logic circuit (for example, logic circuit 100).

[0046] In an exemplary embodiment, second state 204 may include generation of a reliable index vector from biometric signal e′. An exemplary reliable index vector I° may include m bits. In an exemplary embodiment, each bit of reliable index vector I° may include a respective confidence of a respective bit of biometric signal e′. In an exemplary embodiment, confidence may refer to a value which may represent which bits of biometric signal e′ may have lower probability of error. An exemplary logic circuit may include a hardware unit 106 that may be configured to generate reliable index vector I° from biometric signal e′. In an exemplary embodiment, different methods may be utilized for generating confidence values of each bit of reliable index vector I°, such as a method disclosed by Herder et al. in “Trapdoor computational fuzzy extractors and stateless cryptographically-secure physical unclonable functions,” IEEE Transactions on Dependable and Secure Computing, vol. 14, no. 1, pp. 65-82, 2016.

[0047] In an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from second state 204 to a third state 206 responsive to reliable index vector I° being generated. As a result, in an exemplary embodiment, control unit 104 may initiate third state 206 when hardware unit 106 that obtains reliable index vector I°. In exemplary embodiment, third state 206 may include extraction of a subset index vector I″ from reliable index vector I°. In exemplary embodiment, subset index vector I″ may include n non-zero bits where n≤m. In exemplary embodiment, subset index vector I″ may be utilized to determine n most reliable rows out of a total number of m rows of an m×n matrix A that may have been randomly generated and utilized as an encryption key for encrypting biometric signal e′. In an exemplary embodiment, a reliable row may refer to a row of matrix A that may be included in an n×n truncated square matrix A.sub.I″ extracted from matrix A to obtain a highest statistical success rate of encryption of biometric signal e′ compared to other possibilities. In an exemplary embodiment, matrix A may be referred to as a public key since it may be exposed to public once it is generated.

[0048] FIG. 1B shows a block diagram of a logic circuit coupled with a processor, consistent with one or more exemplary embodiments of the present disclosure. In exemplary embodiment, reliable index vector I° may be sent to a processor 101 that may be configured to obtain subset index vector I″ from reliable index vector I°. In an exemplary embodiment, processor 101 may calculate subset index vector I″ by applying a Gaussian elimination method to matrix A based on reliable index vector I° and a given index vector I′. An exemplary index vector I′ may be a stored version of an original index vector I that may have initially generated from an original biometric signal e to indicate n most reliable bits of original biometric signal e. An exemplary original biometric signal e may have been initially obtained from a same user from whom biometric signal e′ is acquired. However, in an exemplary embodiment, due to various sources of error (such as noise), some bits original biometric signal e and biometric signal e′, and consequently, index vectors I, I°, and I′ may be different. Therefore, subset index vector I″ may be calculated to correct possible inaccuracies in given index vector I′.

[0049] Referring again to FIGS. 1A and 2, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from third state 206 to a fourth state 208 responsive to subset index vector I″ being extracted. In an exemplary embodiment, processor 101 may notify control unit 104 after generating subset index vector I″ by triggering a ready signal so that control unit 104 may initiate fourth state 208.

[0050] In an exemplary embodiment, fourth state 208 may include generation of a modulo 2 addition vector (b′⊕e′).sub.I″ by performing an XOR operation on each of a plurality of selected bit pairs. In an exemplary embodiment, each of the plurality of selected bit pairs may include a first selected bit and a second selected bit. An exemplary first selected bit may be extracted from a respective bit of a helper data b′ according to a respective non-zero bit of subset index vector I″. An exemplary second selected bit may be extracted from biometric signal e′ according to the respective non-zero bit.

[0051] In further detail regarding fourth state 208, in an exemplary embodiment, modulo 2 addition vector (b′⊕e′).sub.I″ may be obtained by performing a modulo 2 addition on helper data b′ and biometric signal e′ according to non-zero bits of subset index vector I″. In an exemplary embodiment, modulo 2 addition may include bitwise addition (i.e., an XOR operation on each pair of bits) of helper data b′ and biometric signal e′. In an exemplary embodiment, helper data b′ may have a same size as biometric signal e′, i.e., m bits. In an exemplary embodiment, helper data b′ may be a stored version of an original helper data b that may have been calculated from an original secret key s and original biometric signal e according to an operation defined by the following:

b.sub.I=A.sub.I.Math.s⊕e.sub.I  Equation (1)

where b.sub.I is an n-bit subset of original helper data b that includes n most reliable bits of original helper data b according to original index vector I, A.sub.I is an n×n square matrix that includes n most reliable rows of public key A according to original index vector I, e.sub.I is an n-bit subset of original biometric signal e that includes n most reliable bits of origin original biometric signal e according to original index vector I, A.sub.I.Math.s is a bitwise multiplication of A.sub.I and s, and ⊕ is a modulo 2 addition operator. In an exemplary embodiment, Equation (1) may be used to hide original secret key s (which is randomly generated) by employing public key A and original biometric signal e. In an exemplary embodiment, original helper data b may be obtained by expanding b.sub.I to m bits by inserting zeros based on original index vector I. In an exemplary embodiment, original helper data b may be cryptographically random and therefore, may leak no information about original secret key s and original biometric signal e.

[0052] To obtain each exemplary selected bit pair (for example, an i.sup.th selected bit pair), a corresponding bit (for example, an i.sup.th bit) of subset index vector I″ may be checked. If an exemplary i.sup.th bit of subset index vector i.sup.th is non-zero, an XOR operation may be performed on the first selected bit (for example, an i.sup.th bit of helper data b′) and the second selected bit (for example, an i.sup.th bit of biometric signal e′) to obtain a corresponding bit of modulo 2 addition vector (b′⊕e′).sub.I″. Since, in an exemplary embodiment, subset index vector I″ may have n non-zero bits, modulo 2 addition vector (b′⊕e′).sub.I″ may have a size of n bits. In other words, in an exemplary embodiment, a j.sup.th bit of modulo 2 addition vector (b′⊕e′).sub.I″ may correspond to a j.sup.th non-zero bit of subset index vector I″. As a result, in an exemplary embodiment, modulo 2 addition vector (b′⊕e′).sub.I″ may be generated from n most reliable bits of helper data b′ and biometric signal e′, according to subset index vector I″.

[0053] To implement fourth state 208, an exemplary logic circuit may further include a first shift register 108, a second shift register 110, an XOR gate 112, a third shift register 114, and a first n-bit register 116. In an exemplary embodiment, a “register” in the present disclosure refers to a hardware unit that stores digital data (i.e., data bits) and a “shift register” may refer to a register that may shift stored bits to a right or left direction at every clock cycle (typically, one bit per clock cycle). In an exemplary embodiment, first shift register 108 may be configured to store helper data b′ and generate a first shifted bit 118 by shifting helper data b′ one bit per clock cycle. In an exemplary embodiment, second shift register 110 may be coupled to sensor 102 and may be configured to receive biometric signal e′ from sensor 102 and generate a second shifted bit 120 by shifting biometric signal e′ one bit per clock cycle. In an exemplary embodiment, XOR gate 112 may be configured to perform an XOR operation on first shifted bit 118 and second shifted bit 120. In an exemplary embodiment, third shift register 114 may be configured to store subset index vector I″ and generate a third shifted bit 122 by shifting subset index vector I″ one bit per clock cycle. In an exemplary embodiment, first n-bit register 116 may include an enable input en. In an exemplary embodiment, enable input en may be configured to receive third shifted bit 122 and generate each respective bit of modulo 2 addition vector (b′⊕e′).sub.I″ by loading an output of XOR gate 112 to a respective location in first n-bit register 116 once per clock cycle responsive to third shifted bit 122 being non-zero 122. In an exemplary embodiment, when third shift register 114 loads the j.sup.th non-zero bit of subset index vector I″ to third shifted bit 122, enable input en may be activated. As a result, first n-bit register 116 may receive a result of an XOR operation on first shifted bit 118 and second shifted bit 120. Therefore, in an exemplary embodiment, first shifted bit 118 may be equal to the first selected bit when enable input en is active. In addition, in an exemplary embodiment, second shifted bit 120 may be equal to the second selected bit when enable input en is active. As a result, XOR gate 112 may output the j.sup.th bit of modulo 2 addition vector (b′⊕e′).sub.I″ (corresponding to the j.sup.th non-zero bit of subset index vector I″) to a j.sup.th bit location in first n-bit register 116. In an exemplary embodiment, it may last m clock cycles to shift all bits of subset index vector I″. Therefore, all bits of modulo 2 addition vector (b′⊕e′).sub.I″ may be generated and loaded into first n-bit register 116 after m clock cycles.

[0054] In an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from fourth state 208 to a fifth state 210 responsive to modulo 2 addition vector (b′⊕e′).sub.I″ being generated. As a result, in an exemplary embodiment, control unit 104 may initiate fifth state 210 after m clock cycles from the initiation of fourth state 208.

[0055] In an exemplary embodiment, fifth state 210 may include generation of a primary hash vector from a transposed inverse public key (A.sub.I″.sup.−1).sup.T. In an exemplary embodiment, transposed inverse public key (A.sub.I″.sup.−1).sup.T may include a primary square matrix. In an exemplary embodiment, generation of the primary hash vector may include sequentially applying a hashing function on each row of the primary square matrix. An exemplary primary square matrix may include a transpose of an inverse of a truncated square matrix. An exemplary truncated square matrix A.sub.I″ may be extracted from public key A according to subset index vector I″, as described above.

[0056] An exemplary primary square matrix may include a transpose of an inverse public key A.sub.I″.sup.−1 which is an inverse of truncated square matrix A.sub.I″ and is used for calculating a secret key s′ according to an operation defined by the following:

s′=A.sub.I″.sup.−1.Math.(b′⊕e′).sub.I″  Equation (2)

[0057] According to Equations (1) and (2), in an exemplary embodiment, secret key s′ may be equal to original secret key s if b′, e′, and I″ are equal to b, e, and I, respectively, and A.sub.I″.sup.−1 is equal to an inverse of A.sub.I. Therefore, in an exemplary embodiment, inverse public key A.sub.I″.sup.−1 may be loaded from processor 101 to an exemplary logic circuit in fifth state 210 to be verified prior to calculation of secret key s′. To lower the computational complexity of the verification of inverse public key A.sub.I″.sup.−1, an exemplary logic circuit may acquire transposed inverse public key (A.sub.I″.sup.−1).sup.T instead of inverse public key A.sub.I″.sup.−1 in fifth state 210, so that an entire column of inverse public key A.sub.I″.sup.−1 may be verified at once by loading a corresponding row of transposed inverse public key (A.sub.I″.sup.−1).sup.T to a hardware register in a single clock cycle.

[0058] FIG. 3 shows a flowchart of a verification process, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 2 and 3, in an exemplary embodiment, the verification of inverse public key A.sub.I″.sup.−1 in fifth state 210 may be performed according to a verification process 300. In an exemplary embodiment, verification process 300 may include loading the primary square matrix row by row and generating a primary hash vector σ by sequentially applying a hashing function on each row of the primary square matrix (step 302). An exemplary hashing function may digest inverse public key A.sub.I″.sup.−1 column-by-column to a fixed size code. Therefore, in an exemplary embodiment, primary hash vector σ may have a fixed size of n bits, i.e., equal to the size of each row of the primary square matrix. As a result, primary hash vector σ may be saved instead of storing inverse public key A.sub.I″.sup.−1 for the verification process, thereby reducing required storage space and computational cost. An exemplary hashing function may apply different hashing algorithms to the primary square matrix, such as secure hash algorithm (SHA)-256.

[0059] Referring again to FIG. 1A, an exemplary logic circuit may further include a first hash unit 124 and a second n-bit register 126. In an exemplary embodiment, a “hash unit” may refer to a hardware unit that applies hash function (such as SHA-256) to an input data with an arbitrary size to generate a fixed-size output data. In an exemplary embodiment, first hash unit 124 may be configured to sequentially receive each row of the primary square matrix responsive to FSM 200 being transitioned to fifth state 210. As a result, transposed inverse public key (A.sub.I″.sup.−1).sup.T may be loaded to first hash unit 124 row by row when FSM 200 is transitioned to fifth state 210. In an exemplary embodiment, first hash unit 124 may be further configured to generate primary hash vector σ by sequentially applying the hashing function on each row of the primary square matrix. In an exemplary embodiment, second n-bit register 126 may be coupled to hash unit 124 and may be configured to store primary hash vector σ. An exemplary hashing result of each row of transposed inverse public key (A.sub.I″.sup.−1).sup.T may be digested into a temporary register 127 at each clock cycle. In an exemplary embodiment, a complete digestion of inverse public key A.sub.I″.sup.−1 may be provided after n clock cycles to be loaded and stored into second n-bit register 126 from temporary register 127.

[0060] Referring again to FIGS. 1A and 2, in an exemplary embodiment, control unit 104 may be further configured to transition FSM 200 from fifth state 210 to a sixth state 212 responsive to primary hash vector σ being generated. As a result, in an exemplary embodiment, control unit 104 may initiate sixth state 212 after n clock cycles from the initiation of fifth state 210.

[0061] In an exemplary embodiment, sixth state 212 may include verification of public key A. An exemplary verification of public key A in sixth state 212 may include obtaining a digestion of public key A by sequentially applying the hashing function on each row of the m×n matrix and comparing the digestion with a pre-stored digestion that may be obtained by applying the hashing function on an original public key. In an exemplary embodiment, the original public key may refer to an m×n matrix that may have been initially generated when original biometric signal e was acquired. An exemplary original public key may be equal to public key A if public key A is accurately generated and received by logic circuit 100.

[0062] Referring again to FIGS. 2 and 3, in an exemplary embodiment, the verification of public key A in sixth state 212 may be performed according to verification process 300. In an exemplary embodiment, verification process 300 may further include loading matrix A row by row (step 304). To implement an exemplary verification of public key A in sixth state 212, verification process 300 may further include obtaining a digestion of each row of matrix A (step 306) after the row is loaded in step 304. Similar to generating primary hash vector σ, each newly received row of public key A may be hashed to a digestion of a previous row of public key A. An exemplary hashing function (such as SHA-256) may be applied to each row of public key A at each clock cycle. In an exemplary embodiment, a complete digestion of public key A may be provided after m clock cycles. In an exemplary embodiment, if a last row of public key A is hashed (step 308, yes), the digestion may be compared with the pre-stored digestion (step 310). Otherwise, verification process 300 may load a next row of matrix A to continue digesting public key A (step 308, no). In an exemplary embodiment, if the digestion of matrix A is equal to the pre-stored digestion (step 310, yes), verification of matrix A may be successful. Otherwise, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from sixth state 212 to first state 202 responsive to a failure of the verification of public key A (step 310, no). As a result, FSM 200 may restart if verification of public key A fails.

[0063] Referring again to FIG. 1A, in an exemplary embodiment, first hash unit 124 may be configured to generate the digestion of public key A by sequentially applying the hashing function on each row of the m×n matrix responsive to FSM 200 being transitioned to sixth state 212. An exemplary hashing result of each row of public key A may be digested into a temporary register 127 at each clock cycle. As a result, in an exemplary embodiment, first hash unit 124 may generate a complete digestion of public key A after m clock cycles from the beginning of sixth state 212.

[0064] An exemplary logic circuit may further include a third n-bit register 128 and a first comparator circuit 130. In an exemplary embodiment, third n-bit register 128 may be configured to store the pre-stored digestion. In an exemplary embodiment, first comparator circuit 130 may be configured to compare the digestion of public key A with the pre-stored digestion responsive to the digestion of the public key A being generated by first hash unit 124. In an exemplary embodiment, when the digestion of the public key A is generated and stored in temporary register 127 in sixth state 212, control unit 104 may configure a multiplexer 132 through a select line sel.sub.1 of multiplexer 132 to load the pre-stored digestion from third n-bit register 128 to a first input 134 of first comparator circuit 130. In an exemplary embodiment, first comparator circuit 130 may then compare the pre-stored digestion with the digestion of the public key A that is loaded from temporary register 127 to a second input 136 of first comparator circuit 130. If the digestion of the public key A is equal to the pre-stored digestion, comparator circuit 130 may output an exemplary valid signal to control unit 104, indicating that verification of public key A is successful.

[0065] Referring again to FIGS. 2 and 3, an exemplary seventh state 214 may include verification of transposed inverse public key (A.sub.I″.sup.−1).sup.T based on primary hash vector σ simultaneously with verification of public key A to ensure the integrity of a given (A.sub.I″.sup.−1) that may be generated and sent to logic circuit 100 by processor 101. In an exemplary embodiment, since transposed inverse public key (A.sub.I″.sup.−1).sup.T is utilized by FSM 200 to obtain secret key s′ for computational efficiency (instead of directly using inverse public key A.sub.I″.sup.−1 in Equation (2)), (A.sub.I″.sup.−1).sup.T may be verified in seventh state 214 instead of A.sub.I″.sup.−1. To verify transposed inverse public key (A.sub.I″.sup.−1).sup.T, in an exemplary embodiment, verification process 300 may include generation of a secondary hash vector from a reloaded inverse public key (step 312) responsive to applying the hashing function to a k.sup.th row (i.e., row.sub.k) of the m×n matrix and a k.sup.th element of subset index vector I″ being non-zero (step 314, yes) where 1≤k≤m. As a result, an exemplary secondary hash vector may be generated each time the hashing function is applied to a row of public key A that is included in truncated square matrix A.sub.I″. An exemplary reloaded inverse public key may include a secondary square matrix. In an exemplary embodiment, if the reloaded inverse public key is correctly generated by processor 101 and accurately loaded to logic circuit 100, the secondary square matrix may be equal to the primary square matrix. Therefore, in an exemplary embodiment, the secondary square matrix may be compared with the primary square matrix by comparing their corresponding hash vectors to verify the reloaded inverse public key, as described below.

[0066] In an exemplary embodiment, rows of matrix A that are included in truncated square matrix A.sub.I″ may be detected in step 314 according to subset index vector I″. In an exemplary embodiment, each non-zero element (for example, the k.sup.th element) of subset index vector I″ may indicate the inclusion of a corresponding row (for example, the k.sup.th row) of matrix A in truncated square matrix A.sub.I″. In an exemplary embodiment, if the k.sup.th row of the m×n matrix is included in n×n truncated square matrix A.sub.I″, transposed inverse public key (A.sub.I″.sup.−1).sup.T may be reloaded from processor 101 to logic circuit 100 to verify that an inverse of A.sub.I″ is correctly generated by processor 101. In an exemplary embodiment, transposed inverse public key (A.sub.I″.sup.−1).sup.T may be reloaded row by row to obtain the secondary square matrix. Afterward, in an exemplary embodiment, the secondary hash vector may be generated by sequentially applying the hashing function on each row of the secondary square matrix upon reloading each row of transposed inverse public key (A.sub.I″.sup.−1).sup.T in step 312.

[0067] In an exemplary embodiment, verification of a reloaded version of transposed inverse public key (A.sub.I″.sup.−1).sup.T in step 312 may further include comparing the secondary hash vector with primary hash vector σ. If, in an exemplary embodiment, the secondary hash vector is different from primary hash vector σ, verification of transposed inverse public key (A.sub.I″.sup.−1).sup.T may fail and FSM 200 may restart from first state 202. Otherwise, verification process 300 may proceed to step 316 to verify a j.sup.th row of A.sub.I″ by comparing a multiplication result (i.e., (A.sub.I″.sup.−1).sup.T×row.sub.k) of the secondary square matrix and the k.sup.th row of the m×n matrix with a j.sup.th row (IU) of an n×n identity matrix where 1≤j≤n responsive to the secondary hash vector being equal to primary hash vector σ. In an exemplary embodiment, the k.sup.th row of the m×n matrix and the j.sup.th row of the n×n identity matrix may be associated with a j.sup.th non-zero element of the subset index vector I″. In an exemplary embodiment, at each iteration of step 314 in which the k.sup.th element of subset index vector I″ is non-zero, the multiplication result may be compared with the j.sup.th row of the identity matrix, starting with j=1. If an exemplary multiplication result is equal to the j.sup.th row of the identity matrix, j may be incremented by one to examine a next row of A.sub.I″ in a next iteration of step 316. Therefore, an exemplary j.sup.th non-zero element of subset index vector I″ may be the same as the k.sup.th element of subset index vector I″ if the k.sup.th element of subset index vector I″ is non-zero. In an exemplary embodiment, verification of rows of A.sub.I″ may be repeated until a last row of public key A is loaded (step 318, yes). If an exemplary multiplication result is different from the j.sup.th row of the identity matrix in step 316, verification of A.sub.I″ (or reloaded matrix (A.sub.I″.sup.−1).sup.T) may fail, because A.sub.I″×A.sub.I″.sup.−1 may be different from the identity matrix and therefore, an exemplary reloaded matrix A.sub.I″.sup.−1 may not be considered a correct inverse of matrix A.sub.I″. As a result, in an exemplary embodiment, FSM 200 may restart from first state 202. Otherwise, an exemplary verification of transposed inverse public key (A.sub.I″.sup.−1).sup.T may be successful if all rows of A.sub.I″ are successfully verified in step 316.

[0068] Referring again to FIGS. 1A, 2, and 3, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from sixth state 212 to seventh state 214 responsive to applying the hashing function to the k.sup.th row (step 306) of the m×n matrix and the k.sup.th element of the subset index vector I″ being non-zero (step 314, yes). As a result, in an exemplary embodiment, FSM 200 may be transitioned from sixth state 212 to seventh state 214 each time the hashing function is applied to a row of public key A that is included in truncated square matrix A.sub.I″.

[0069] In an exemplary embodiment, first hash unit 124 may be further configured to sequentially receive each row of the secondary square matrix from processor 101 responsive to FSM 200 being transitioned to seventh state 214 and generate the secondary hash vector by sequentially applying the hashing function on each row of the secondary square matrix. As a result, in an exemplary embodiment, it may take n clock cycles for seventh state 214 to receive and digest all rows of the secondary square matrix after applying the hashing function to each row of public key A that is included in truncated square matrix A.sub.I″ in sixth state 212.

[0070] In an exemplary embodiment, first comparator circuit 130 may be further configured to implement step 312 of verification process 300 by comparing the secondary hash vector with primary hash vector σ responsive to the secondary hash vector being generated by first hash unit 124. In an exemplary embodiment, when the secondary hash vector is generated and stored in temporary register 127 in seventh state 214, control unit 104 may configure multiplexer 132 through select line sel.sub.1 of multiplexer 132 to load primary hash vector σ from second n-bit register 126 to first input 134 of first comparator circuit 130. In an exemplary embodiment, first comparator circuit 130 may then compare primary hash vector σ with the secondary hash vector that is loaded from temporary register 127 to second input 136 of first comparator circuit 130. If the secondary hash vector is equal to primary hash vector σ, comparator circuit 130 may output an exemplary valid signal to control unit 104, indicating that verification of the reloaded inverse public key is successful.

[0071] An exemplary logic circuit may further include a fourth n-bit register 138, a fifth n-bit register 140, a first plurality of AND gates 142, a multi-level XOR tree 144, a fourth shift register 146, a fifth shift register 148, and a second comparator circuit 150. To implement step 316 of verification process 300, in an exemplary embodiment, fourth n-bit register 138 may be configured to receive the k.sup.th row of m×n matrix A from processor 101 responsive to the secondary hash vector being equal to primary hash vector σ. An exemplary valid signal may configure fourth n-bit register 138 to receive the k.sup.th row of matrix A if the secondary hash vector is equal to primary hash vector σ. In an exemplary embodiment, fifth n-bit register 140 may be configured to sequentially receive each row of the secondary square matrix responsive to the secondary hash vector being equal to primary hash vector σ. An exemplary valid signal may configure fifth n-bit register 140 to receive each row of the secondary square matrix if the secondary hash vector is equal to primary hash vector σ.

[0072] To implement the multiplication (A.sub.I″.sup.−1).sup.T×row.sub.k in step 316 of verification process 300, in an exemplary embodiment, first plurality of AND gates 142 may be configured to generate a first n-bit vector X.sub.t by performing a respective bitwise AND operation on each respective bit (for example, a j.sup.th bit) in fourth n-bit register 138 and a respective bit (for example, a j.sup.th bit) in fifth n-bit register 140. In an exemplary embodiment, first n-bit vector X.sub.t may be associated with a respective row of the secondary square matrix. Each exemplary bit of first n-bit vector X.sub.t may be equal to a bitwise multiplication of a corresponding bit of the k.sup.th row of matrix A and a corresponding bit an exemplary row of the secondary square matrix. As a result, in an exemplary embodiment, each row of (A.sub.I″.sup.−1).sup.T may be convolved with row.sub.k in one clock cycle.

[0073] FIG. 1C shows a schematic of a multi-level XOR tree, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, multi-level XOR tree 144 may have ln (n) layers (for example, 7 layers for n=128) and may be configured to generate a respective bit of the multiplication result at each clock cycle by performing a modulo 2 addition on bits of first n-bit vector 142. In an exemplary embodiment, a j.sup.th bit of the multiplication result may correspond to a j.sup.th non-zero bit of subset index vector I″, as described above. In an exemplary embodiment, it may take n clock cycles to completely generate the multiplication result in step 316.

[0074] In an exemplary embodiment, fourth shift register 146 may be coupled to multi-level XOR tree 144 and may be configured to sequentially receive each respective bit of the multiplication result from the XOR tree at each clock cycle and generate a fourth shifted bit 152 by shifting the multiplication result one pit per clock cycle. In an exemplary embodiment, fifth shift register 148 may be configured to store the j.sup.th row of the n×n identity matrix and generate a fifth shifted bit 154 by circularly shifting the j.sup.th row one bit per clock cycle. In an exemplary embodiment, second comparator circuit 150 may be configured to compare the multiplication result with the j.sup.th row by comparing fourth shifted bit 152 with fifth shifted bit 154. If, in an exemplary embodiment, the multiplication result is different from the j.sup.th row of the n×n identity matrix, verification of the transposed inverse public key (A.sub.I″.sup.−1).sup.T in step 316 may fail, and consequently, control unit 104 may transition FSM 200 from seventh state 214 to first state 202, so that FSM 200 may restart from its initial state. Otherwise, control unit 104 may transition FSM 200 from seventh state 214 to sixth state 212, so that verification process 300 may proceed to verifying a next row of matrix A.

[0075] Referring again to FIGS. 1A and 2, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from sixth state 212 to an eighth state 216 responsive to a success of the verification of public key A. Therefore, in an exemplary embodiment, control unit 104 may initiate eighth state 216 if matrix A is successfully verified in step 310 of verification process 300. In an exemplary embodiment, eighth state 216 may include generation of secret key s′ by multiplying inverse of the truncated square matrix A.sub.I″.sup.−1 by modulo 2 addition vector (b′⊕e′).sub.I″ according to Equation (2).

[0076] To implement eighth state 216, an exemplary logic circuit may further include a sixth n-bit register 156, a sixth shift register 158, and a calculation unit 160. In an exemplary embodiment, sixth n-bit register 156 may be configured to store secret key s′. In an exemplary embodiment, sixth shift register 158 may be coupled to first n-bit register 116 and may be configured to generate a sixth shifted bit b′e′[i] by shifting modulo 2 addition vector (b′⊕e′).sub.I″ one bit per clock cycle.

[0077] FIG. 1D shows a schematic of a calculation unit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, calculation unit 160 may include a second plurality of AND gates 162 and a plurality of two-input XOR gates 164. In an exemplary embodiment, second plurality of AND gates 162 may include n AND gates. As a result, second plurality of AND gates 162 may be configured to generate a second n-bit vector Yt by performing bitwise AND operations on sixth shifted bit b′e′[i] and each bit of a respective row of transposed inverse public key (A.sub.I″.sup.−1).sup.T at each clock cycle responsive to FSM 200 being transitioned to eighth state 216. Therefore, for each exemplary row of transposed inverse public key (A.sub.I″.sup.−1).sup.T, second n-bit vector Yt may be generated once after initiation of eighth state 216 in a single clock cycle. In an exemplary embodiment, plurality of two-input XOR gates 164 may be configured to generate each bit of secret s′ key by performing a respective bitwise XOR operation once per clock cycle on each bit of second n-bit vector Yt and a respective bit in sixth n-bit register 156. In an exemplary embodiment, plurality of two-input XOR gates 164 may be further configured to load each bit of secret key s′ to a respective location in sixth n-bit register 156. For example, an i.sup.th bit of secret key s′ may be loaded to an i.sup.th location in sixth n-bit register 156 where 0≤i<n. Therefore, at each exemplary clock, the i.sup.th bit of secret key s′ may be XORed with a value of the i.sup.th bit that may have been generated in a previous clock cycle. In an exemplary embodiment, plurality of two-input XOR gates 164 may include n XOR gates. As a result, all bits of secret key s′ may be XORed with their previous values in a single clock cycle. As a result, an entire calculation of Equation (2) may last n clock cycles (one clock cycle for each row of transposed inverse public key (A.sub.I″.sup.−1).sup.T).

[0078] Referring again to FIGS. 1A and 2, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from eighth state 216 to a ninth state 218 responsive to secret key s′ being generated. As a result, FSM 200 may be transitioned to ninth state 218 after n clock cycles from the initiation of eighth state 216. In an exemplary embodiment, ninth state 218 may include verification of secret key s′. In an exemplary embodiment, verification of secret key s′ may include generation of a hashed secret key h.sub.1″ by applying the hashing function to a public vector b.sub.I″′ according to secret key s′ and comparing hashed secret key h.sub.1″ with a pre-stored hashed key h.sub.1′.

[0079] In an exemplary embodiment, each respective bit of public vector b.sub.I″′ may be extracted from helper data b′ according to a respective non-zero bit of subset index vector I″. As a result, in an exemplary embodiment, public vector b.sub.I″′ may include n most reliable bits of helper data b′ according to subset index vector I″. In an exemplary embodiment, pre-stored hashed key h.sub.1′ may have been previously generated by processor 101 by applying the hashing function to b.sub.I (defined in Equation (1)) according to original secret key s. Therefore, pre-stored hashed key h.sub.1′ may be used for verification of secret key s′ in ninth state 218. If, in an exemplary embodiment, hashed secret key h.sub.1″ is equal to pre-stored hashed key h.sub.1′, secret key s′ may be considered valid. Otherwise, in an exemplary embodiment, verification of secret key s′ may be considered unsuccessful.

[0080] To implement ninth state 218, an exemplary logic circuit may further include a hash-and-compare unit 166. FIG. 1E shows a schematic of a hash-and-compare unit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, hash-and-compare unit 166 may include a second hash unit 168 and a third comparator circuit 170. In an exemplary embodiment, second hash unit 168 may be configured to generate hashed secret key h.sub.1″ by applying the hashing function to public vector b.sub.I″′ according to secret key s′ when FSM 200 is transitioned to ninth state 218.

[0081] In an exemplary embodiment, third comparator circuit 170 may be configured to compare hashed secret key h.sub.1″ with pre-stored hashed key h.sub.1′. If, in an exemplary embodiment, hashed secret key h.sub.1″ is different from pre-stored hashed key h.sub.1′, FSM 200 may be transitioned back to eighth state 216 to recalculate secret key s′ with one bit-flip in modulo 2 addition vector (b′⊕e′).sub.I″. Therefore, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from ninth state 218 to eighth state 216 responsive to an i.sup.th successive failure of the verification of secret key s′ where i<n+1. Since, in an exemplary embodiment, there may be n possible bit-flips in modulo 2 addition vector (b′⊕e′).sub.I″, FSM 200 may be successively transitioned from ninth state 218 to eighth state 216 until a number of successive failures of verification of secret key s′ reaches n+1. If none of exemplary bit-flips of (b′⊕e′).sub.I″ leads to a successful verification of secret key s′, secret key s′ may be considered invalid and logic circuit 100 may generate an error signal. As a result, in an exemplary embodiment, control unit 104 may be configured to transition FSM 200 from ninth state 218 to first state 202 responsive to an (n+1).sup.th successive failure of the verification of the secret key s′, so that FSM 200 may restart from an idle state.

[0082] Referring again to FIGS. 1A, 1E, and 3, in an exemplary embodiment, control unit 104 may be further configured to transition FSM 200 from ninth state 218 to a tenth state 220 if secret key s′ is successfully verified in ninth state 218. In an exemplary embodiment, tenth state 220 may include generation of response signal h.sub.0″ by applying the hashing function to public vector b.sub.I″′ according to secret key s′.

[0083] To implement tenth state 220, in an exemplary embodiment, hash-and-compare unit 166 may further include a third hash unit 172. In an exemplary embodiment, third hash unit 170 may be configured to generate response signal h.sub.0″ by applying the hashing function to public vector b.sub.I″′ according to secret key s′ responsive to FSM 200 being transitioned to tenth state 220. In an exemplary embodiment, if hashed secret key h.sub.1″ is equal to pre-stored hashed key h.sub.1′ (i.e., secret key s′ is verified successfully), third comparator circuit 170 may trigger a buffer circuit 174 that is coupled to third hash unit 172 to pass response signal h.sub.0″ as a final output of logic circuit 100. Afterwards, in an exemplary embodiment, control unit 104 may transition FSM 200 from tenth 220 state to first state 202 responsive to response signal h.sub.0″ being generated.

[0084] In order to differentiate response signal h.sub.0″ from hashed secret key h.sub.1″ (since they are both generated from public vector b.sub.I″′ according to secret key s′), different extra bits may be concatenated to inputs of second hash unit 168 and third hash unit 172. For example, a “1” bit may be concatenated to the input data of second hash unit 168 and a “0” bit may be concatenated to the input data of third hash unit 172. An exemplary concatenation may have to be previously applied to b.sub.I for generation of pre-stored hashed key h.sub.1′, so that digestion of secret key s′ may be consistent with that of original secret key s.

[0085] FIG. 4 shows an example computer system 400 in which an embodiment of the present invention, or portions thereof, may be implemented as computer-readable code, consistent with exemplary embodiments of the present disclosure. For example, processor 101 may be implemented in computer system 400 using hardware, software, firmware, tangible computer readable media having instructions stored thereon, or a combination thereof and may be implemented in one or more computer systems or other processing systems. Hardware, software, or any combination of such may embody any of the units and components in FIGS. 1A-3.

[0086] If programmable logic is used, such logic may execute on a commercially available processing platform or a special purpose device. One ordinary skill in the art may appreciate that an embodiment of the disclosed subject matter can be practiced with various computer system configurations, including multi-core multiprocessor systems, minicomputers, mainframe computers, computers linked or clustered with distributed functions, as well as pervasive or miniature computers that may be embedded into virtually any device.

[0087] For instance, a computing device having at least one processor device and a memory may be used to implement the above-described embodiments. A processor device may be a single processor, a plurality of processors, or combinations thereof. Processor devices may have one or more processor “cores.”

[0088] An embodiment of the invention is described in terms of this example computer system 400. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures. Although operations may be described as a sequential process, some of the operations may in fact be performed in parallel, concurrently, and/or in a distributed environment, and with program code stored locally or remotely for access by single or multiprocessor machines. In addition, in some embodiments the order of operations may be rearranged without departing from the spirit of the disclosed subject matter.

[0089] Processor device 404 may be a special purpose (e.g., a graphical processing unit) or a general-purpose processor device. As will be appreciated by persons skilled in the relevant art, processor device 404 may also be a single processor in a multi-core/multiprocessor system, such system operating alone, or in a cluster of computing devices operating in a cluster or server farm. Processor device 404 may be connected to a communication infrastructure 406, for example, a bus, message queue, network, or multi-core message-passing scheme.

[0090] In an exemplary embodiment, computer system 400 may include a display interface 402, for example a video connector, to transfer data to a display unit 430, for example, a monitor. Computer system 400 may also include a main memory 408, for example, random access memory (RAM), and may also include a secondary memory 410. Secondary memory 410 may include, for example, a hard disk drive 412, and a removable storage drive 414. Removable storage drive 414 may include a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. Removable storage drive 414 may read from and/or write to a removable storage unit 418 in a well-known manner. Removable storage unit 418 may include a floppy disk, a magnetic tape, an optical disk, etc., which may be read by and written to by removable storage drive 414. As will be appreciated by persons skilled in the relevant art, removable storage unit 418 may include a computer usable storage medium having stored therein computer software and/or data.

[0091] In alternative implementations, secondary memory 410 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 400. Such means may include, for example, a removable storage unit 422 and an interface 420. Examples of such means may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 422 and interfaces 420 which allow software and data to be transferred from removable storage unit 422 to computer system 400.

[0092] Computer system 400 may also include a communications interface 424. Communications interface 424 allows software and data to be transferred between computer system 400 and external devices. Communications interface 424 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface 424 may be in the form of signals, which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 424. These signals may be provided to communications interface 424 via a communications path 426. Communications path 426 carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link or other communications channels.

[0093] In this document, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage unit 418, removable storage unit 422, and a hard disk installed in hard disk drive 412. Computer program medium and computer usable medium may also refer to memories, such as main memory 408 and secondary memory 410, which may be memory semiconductors (e.g. DRAMs, etc.).

[0094] Computer programs (also called computer control logic) are stored in main memory 408 and/or secondary memory 410. Computer programs may also be received via communications interface 424. Such computer programs, when executed, enable computer system 400 to implement different embodiments of the present disclosure as discussed herein. In particular, the computer programs, when executed, enable processor device 404 to implement the processes of the present disclosure, such as the operations in verification process 300 illustrated by flowchart of FIG. 3 discussed above. Accordingly, such computer programs represent controllers of computer system 400. Where an exemplary embodiment of logic circuit 100 is implemented using software, the software may be stored in a computer program product and loaded into computer system 400 using removable storage drive 414, interface 420, and hard disk drive 412, or communications interface 424.

[0095] Embodiments of the present disclosure also may be directed to computer program products including software stored on any computer useable medium. Such software, when executed in one or more data processing device, causes a data processing device to operate as described herein. An embodiment of the present disclosure may employ any computer useable or readable medium. Examples of computer useable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, and optical storage devices, MEMS, nanotechnological storage device, etc.).

[0096] The embodiments have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0097] While the foregoing has described what may be considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0098] Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.

[0099] The scope of protection is limited solely by the claims that now follow. That scope is intended and should be interpreted to be as broad as is consistent with the ordinary meaning of the language that is used in the claims when interpreted in light of this specification and the prosecution history that follows and to encompass all structural and functional equivalents. Notwithstanding, none of the claims are intended to embrace subject matter that fails to satisfy the requirement of Sections 101, 102, or 103 of the Patent Act, nor should they be interpreted in such a way. Any unintended embracement of such subject matter is hereby disclaimed.

[0100] Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.

[0101] It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0102] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various implementations. This is for purposes of streamlining the disclosure, and is not to be interpreted as reflecting an intention that the claimed implementations require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed implementation. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[0103] While various implementations have been described, the description is intended to be exemplary, rather than limiting and it will be apparent to those of ordinary skill in the art that many more implementations and implementations are possible that are within the scope of the implementations. Although many possible combinations of features are shown in the accompanying figures and discussed in this detailed description, many other combinations of the disclosed features are possible. Any feature of any implementation may be used in combination with or substituted for any other feature or element in any other implementation unless specifically restricted. Therefore, it will be understood that any of the features shown and/or discussed in the present disclosure may be implemented together in any suitable combination. Accordingly, the implementations are not to be restricted except in light of the attached claims and their equivalents. Also, various modifications and changes may be made within the scope of the attached claims.