STORAGE CIRCUIT PROVIDED WITH VARIABLE RESISTANCE TYPE ELEMENTS

Abstract

A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RT.sub.j to convert a resistance value of a memory cell MC.sub.ij to be read to a data voltage, a reference circuit and RT.sub.R to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RT.sub.j and a first input terminal of the sense amplifier or between the reference circuit and RT.sub.R and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Claims

1. A storage circuit comprising: a memory cell array including a matrix of memory cells each of which includes a variable resistance type element, the variable resistance type element having a resistance value changing in at least two steps; a resistance-voltage conversion circuit to convert a resistance value of a memory cell to be read in the memory cell array to a data voltage; a reference circuit to generate a reference voltage used for comparison with the data voltage; a sense amplifier to determine data stored in the memory cell to be read by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other; and an analog buffer circuit arranged at least one of between the resistance-voltage conversion circuit and a first input terminal of the sense amplifier or between the reference circuit and a second input terminal of the sense amplifier.

2. The storage circuit according to claim 1, wherein the resistance-voltage conversion circuit is arranged for each column of the memory cell array, and each of the resistance-voltage conversion circuits converts a resistance value of a memory cell to be read in a corresponding column to a data voltage, the analog buffer circuit is arranged in at least one column in the memory cell array and buffers a data voltage generated by a resistance-voltage conversion circuit of the column and transmits the buffered data voltage to a first input terminal of the sense amplifier, and current driving capability of the analog buffer circuit is higher than current driving capability of a resistance-voltage conversion circuit of the column.

3. The storage circuit according to claim 2, wherein the analog buffer circuit is arranged in two or more columns in the memory cell array, and each of the analog buffer circuits has a different current driving capability according to distance between the resistance-voltage conversion circuit of the column and a first input terminal of the sense amplifier.

4. The storage circuit according to claim 1, wherein the resistance-voltage conversion circuit and the sense amplifier are arranged in each of a plurality of columns in the memory cell array, the analog buffer circuit buffers a reference voltage output by the reference circuit and transmits the buffered reference voltage to second input terminals of the plurality of sense amplifiers, and current driving capability of the analog buffer circuit is higher than current driving capability of the reference circuit.

5. The storage circuit according to claim 4, wherein the analog buffer circuit is capable of adjusting current driving capability according to distance to the sense amplifier of a column to be accessed.

6. The storage circuit according to claim 1, wherein the analog buffer circuit includes a transistor circuit, and current driving capability of the analog buffer circuit is adjusted by size of a transistor included in a transistor circuit.

7. The storage circuit according to claim 1, wherein current driving capability of the analog buffer circuit is adjusted by power-supply voltage of the analog buffer circuit.

8. The storage circuit according to claim 1, wherein the analog buffer circuit has an amplification factor of one-fold and converts impedance.

9. The storage circuit according to claim 1, wherein the analog buffer circuit includes source follower circuits arranged both between the resistance-voltage conversion circuit and a first input terminal of the sense amplifier and between the reference circuit and a second input terminal of the sense amplifier.

10. A storage circuit comprising: a memory cell array including a matrix of memory cells each of which includes a variable resistance type element, the variable resistance type element having a resistance value changing in at least two steps; a resistance-voltage conversion circuit disposed for each column of the memory cell array and configured to convert a resistance value of a memory cell to be read in a same column to a data voltage; at least one reference circuit to generate a reference voltage used for comparison with the data voltage; and a sense amplifier disposed for each column of the memory cell array and configured to determine data stored in the memory cell to be read by receiving the data voltage generated by a resistance-voltage conversion circuit in a same column and a reference voltage generated by the reference circuit via first and second input terminals, respectively, and comparing both voltages with each other, wherein the reference circuit has a higher current driving capability than each of the resistance-voltage conversion circuits.

11. The storage circuit according to claim 10, wherein the reference circuit includes a reference cell including a variable resistance type element having a resistance value changing and a reference voltage conversion circuit to convert a resistance value of the reference cell to a reference voltage, and current driving capability of the reference voltage conversion circuit is higher than current driving capability of the resistance-voltage conversion circuits.

12. The storage circuit according to claim 10, wherein the reference circuit is capable of adjusting current driving capability according to distance to the sense amplifier of a column to be accessed.

13. The storage circuit according to claim 11, wherein each of the reference voltage conversion circuit and the resistance-voltage conversion circuits includes a transistor circuit, and current driving capability is adjusted by size of a transistor included in a transistor circuit.

14. The storage circuit according to claim 11, wherein current driving capability of the reference voltage conversion circuit is adjusted by power-supply voltage of the reference voltage conversion circuit.

15. The storage circuit according to claim 10, wherein at least one reference voltage conversion circuit is arranged in a plurality in parallel with one another.

16. The storage circuit according to claim 15 comprising means for controlling a number of the reference voltage conversion circuits to be activated.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] A more complete understanding of this application can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

[0039] FIG. 1 is a block diagram of a storage circuit according to Embodiment 1 of the present disclosure;

[0040] FIGS. 2A and 2B are circuit diagrams illustrating configurations of an analog buffer circuit and a reference buffer circuit illustrated in FIG. 1, respectively;

[0041] FIGS. 3A to 31 are timing charts for a description of read operation of the storage circuit illustrated in FIG. 1;

[0042] FIGS. 4A to 4F are timing charts for a description of operation of writing data “0” into a memory cell in the storage circuit illustrated in FIG. 1;

[0043] FIGS. 5A to 5F are timing charts for a description of operation of writing data “1” into a memory cell in the storage circuit illustrated in FIG. 1;

[0044] FIGS. 6A and 6B are respectively circuit diagrams illustrating circuit examples of the analog buffer circuit and the reference buffer circuit illustrated in FIG. 1;

[0045] FIGS. 7A and 7B are respectively circuit diagrams illustrating other circuit examples of the analog buffer circuit and the reference buffer circuit illustrated in FIG. 1;

[0046] FIGS. 8A and 8B are diagrams illustrating variations of a reference circuit in the storage circuit;

[0047] FIG. 9 is a block diagram of a main part of a storage circuit according to Embodiment 2;

[0048] FIG. 10 is a block diagram of a main part of a storage circuit according to another example of Embodiment 2;

[0049] FIG. 11 is a block diagram of a main part of a storage circuit according to Embodiment 3;

[0050] FIGS. 12A and 12B are respectively block diagrams of a main part of an analog buffer circuit in a storage circuit according to Embodiment 4;

[0051] FIG. 13 is a block diagram of a main part of a storage circuit according to Embodiment 5;

[0052] FIG. 14 is a block diagram of a main part of another storage circuit according to Embodiment 5;

[0053] FIG. 15 is a diagram illustrating simulation results indicating a relationship between wiring driving time and storage capacity in storage circuits according to a prior art and the respective embodiments; and

[0054] FIG. 16 is a block diagram for a description of a problem in a storage circuit disclosed in International Publication No. WO 2016/186086.

DETAILED DESCRIPTION

[0055] Storage circuits according to embodiments of the present disclosure are described below with reference to the drawings.

Embodiment 1

[0056] In FIG. 1, a configuration of an m×n bit portion of a storage circuit 11 according to Embodiment 1 is illustrated.

[0057] As illustrated in FIG. 1, the storage circuit 11 includes a memory cell array 21 and a reference cell array 22.

[0058] The memory cell array 21 includes memory cells MC.sub.ij (i=1 to m and j=1 to n) arranged in a matrix of m rows and n columns. Each of m and n is a natural number.

[0059] In contrast, the reference cell array 22 includes reference cells RC.sub.i (i=1 to m) arranged in m rows and one column.

[0060] To one end of each memory cell MC.sub.ij, one end of a current path of a selection transistor ST.sub.ij is connected. To one end of each reference cell RC.sub.i, one end of a current path of a reference selection transistor AT.sub.i is connected.

[0061] Each of the selection transistors ST.sub.ij and each of the reference selection transistors AT.sub.i include N-channel MOS transistors, the drains of which are connected to the corresponding memory cell MC.sub.ij and the corresponding reference cell RC.sub.i, respectively.

[0062] The other ends of memory cells MC.sub.ij in the j-th column are connected in common to a bit line BL.sub.j of the j-th column.

[0063] The other ends of the reference cells RC.sub.i are connected in common to a reference bit line BL.sub.R.

[0064] The other ends of the current paths of selection transistors ST.sub.ij in the j-th column, which are respectively connected to the memory cells MC.sub.ij in the j-th column, are connected in common to a source line SL.sub.j arranged in the j-th column.

[0065] The other ends of the current paths of the reference selection transistors AT.sub.i, which are respectively connected to the reference cell RC.sub.i, are connected in common to a reference source line SL.sub.R.

[0066] On the other hand, the gates of selection transistors ST.sub.ij and a reference selection transistor AT.sub.i in the i-th row are connected in common to a word line WL.sub.i in the i-th row.

[0067] The bit lines BL.sub.1 to BL.sub.n include metal layers, such as aluminum layers or copper layers, that have substantially the same material, width, and thickness as one another. The bit lines BL.sub.j are connected in common to a vertical bit line VBL via analog buffer circuits (hereinafter, simply referred to as buffer circuits) BU.sub.j and current paths of column selection transistors CT.sub.j.

[0068] The vertical bit line VBL extends in the column direction and is connected to a positive input terminal (+) of a sense amplifier SA. The vertical bit line VBL has a larger cross section than the bit lines BL.sub.1 to BL.sub.n and a smaller resistance value per unit length than the bit lines BL.sub.j. The positive input terminal (+) is an example of a first input terminal of the sense amplifier SA.

[0069] The reference cells RC.sub.1 to RC.sub.m include MTJ elements and provide a reference resistance value at the time of read operation and are connected in common to the reference bit line BL.sub.R. The reference bit line BL.sub.R includes a metal layer having substantially the same material, width, and thickness as those in the bit lines BL.sub.1 to BL.sub.n and exhibits substantially the same electrical characteristics as the bit lines BL.sub.1 to BL.sub.n. The reference bit line BL.sub.R is connected to a negative input terminal (−) of the sense amplifier SA via a reference buffer circuit BU.sub.R and a current path of a reference column selection transistor CT.sub.R. The negative input terminal (−) is an example of a second input terminal of the sense amplifier SA.

[0070] The column selection transistors CT.sub.1 to CT.sub.n and the reference column selection transistor CT.sub.R have the same size and characteristics as one another.

[0071] In the following description, an input side portion and an output side portion of the buffer circuit BU.sub.j of each of the bit lines BL.sub.j are sometimes distinguished from each other as a first bit line BL.sub.j1 and a second bit line BL.sub.j2, respectively. In addition, an input side portion and an output side portion of the reference buffer circuit BU.sub.R of the reference bit lines BL.sub.R are sometimes distinguished from each other by referring to the input side portion and the output side portion as a first reference bit line BL.sub.R1 and a second reference bit line BL.sub.R2, respectively.

[0072] To the first bit line BL.sub.j1 in the j-th column, one end of a current path of a read load transistor RT.sub.j is connected. To the other end of the current path of the read load transistor RT.sub.j, read voltage V.sub.R is applied. The read load transistor RT.sub.j is a load transistor that functions as a load at the time of data read.

[0073] To the first bit line BL.sub.j1 in the j-th column, one end of a current path of a write transistor WTP.sub.j and one end of a current path of a write transistor WTN.sub.j are further connected. To the other end of the current path of the write transistor WTP.sub.j, write voltage V.sub.W is applied. In contrast, the other end of the current path of the write transistor WTN.sub.j is grounded. The write transistor WTP.sub.j includes a P-channel MOS transistor, and the write transistor WTN.sub.j includes an N-channel MOS transistor.

[0074] To the first reference bit line BL.sub.R1 connected to the reference cells RC.sub.i, one end of a current path of a reference read load transistor RT.sub.R is connected. To the other end of the current path of the reference read load transistor RT.sub.R, the read voltage V.sub.R is applied. The reference read load transistor RT.sub.R is a load transistor that functions as a load at the time of data read and has the same size and characteristics as the read load transistors RT.sub.1 to RT.sub.n.

[0075] The first reference bit line BL.sub.R1 and the reference read load transistor RT.sub.R function as a reference voltage conversion circuit to convert a resistance value of a reference cell RC.sub.i to a reference in cooperation with each other.

[0076] To each of the source lines SL.sub.j, one end of a current path of a write transistor WQ.sub.j and one end of a current path of a read/write transistor RWQ.sub.j are connected. To the other end of the current path of the write transistor WQ.sub.j, the write voltage V.sub.W is applied. In contrast, the other end of the current path of the read/write transistor RWQ.sub.j is grounded. The write transistor WQ.sub.j includes a P-channel MOS transistor and has the same size and characteristics as the write transistors WTP.sub.1 to WTP.sub.n. The read/write transistors RWQ.sub.j include N-channel MOS transistors and have the same size and characteristics as one another.

[0077] The reference source line SL.sub.R is grounded via a current path of a reference read transistor RWQ.sub.R. The reference read transistor RWQ.sub.R includes an N-channel MOS transistor and has the same size and characteristics as the read/write transistors RWQ.sub.1 to RWQ.sub.n. The gate of the reference read transistor RWQ.sub.R is pulled up.

[0078] The word lines WL.sub.1 to WL.sub.m are connected to a row decoder 31.

[0079] One ends of column lines CL.sub.1 to CL.sub.n are connected to a column decoder 32.

[0080] The other end of each of the column lines CL.sub.j is connected to one input terminal of a NAND gate RG.sub.j in the same column. To the other input terminal of the NAND gate RG.sub.j, a read enable signal RE is supplied. An output signal from the NAND gate RG.sub.j is output to the gate of the corresponding read load transistor RT.sub.j and an enable terminal of the corresponding buffer circuit BU.sub.j. As a result, when reading is instructed by the read enable signal RE and a memory cells MC.sub.ij in the j-th column are selected by a column selection signal, the read load transistor RT.sub.j turns on and the buffer circuit BU.sub.j is brought to an enabled state, amplifies voltage of the first bit line BL.sub.j1 one-fold, and outputs the amplified voltage to the second bit line BL.sub.j2.

[0081] Each of the column lines CL.sub.j is connected to one input terminal of a NAND gate NG.sub.j in the same column. To the other input terminal of the NAND gate NG.sub.j, a write control signal WBLH is supplied. The NAND gate NG.sub.j outputs a low-level output signal to the gate of the corresponding write transistor WTP.sub.j when both voltage of the column line CL.sub.j and the write control signal WBLH are at a high level.

[0082] Each of the column lines CL.sub.j is connected to one input terminal of an AND gate AG.sub.j in the same column. To the other input terminal of the AND gate AG.sub.j, a write control signal WBLL is supplied. The AND gate AG.sub.j outputs a high-level output signal to the gate of the write transistor WTN.sub.j in the same column when both the voltage of the column line CL.sub.j and the write control signal WBLL are at the high level.

[0083] Each of the column lines CL.sub.j is further connected to the gate of the column selection transistor CT.sub.j in the same column. The column selection transistor CT.sub.j turns on when the j-th column is selected.

[0084] One end of a reference column line CL.sub.R is connected to a reference column decoder 33, and the other end of the reference column line CL.sub.R is connected to one input terminal of a reference NAND gate RG.sub.R. To the other input terminal of the reference NAND gate RG.sub.R, the read enable signal RE is supplied. The reference NAND gate RG.sub.R outputs an output signal to the gate of the reference read load transistor RT.sub.R and an enable terminal of the reference buffer circuit BU.sub.R. As a result, the reference read load transistor RT.sub.R turns on and functions as a load when data read is instructed. In addition, the reference buffer circuit BU.sub.R is brought to an enabled state when data read is instructed.

[0085] The reference column line CL.sub.R is connected to one input terminal of a reference NAND gate NG.sub.R. To the other input terminal of the reference NAND gate NG.sub.R, the write control signal WBLH is supplied. The reference NAND gate NG.sub.R outputs a low-level output signal to the gate of a reference write transistor WTP.sub.R when both voltage of the reference column line CL.sub.R and the write control signal WBLH are at the high level.

[0086] The reference column line CL.sub.R is connected to the gate of the reference column selection transistor CT.sub.R. Therefore, the reference column selection transistor CT.sub.R turns on when the reference column line CL.sub.R is at the high level.

[0087] To the gate of each of the write transistors WQ.sub.j, which is connected to the source line SL.sub.j of the j-th column, a write control signal WSLH is applied via an inverter IN. Therefore, when the write control signal WSLH is at the high level, in other words, when “1” is to be written into a memory cell MC.sub.ij, the write transistor WQ.sub.j turns on.

[0088] To the gate of each of the read/write transistors RWQ.sub.j, which is connected to the source line SL.sub.j of the j-th column, an output terminal of an OR gate OR is connected. To one input terminal and the other input terminal of the OR gate OR, the read enable signal RE and a write control signal WSLL are supplied, respectively. When at least one of the read enable signal RE or the write control signal WSLL is at the high level, that is, at the time of reading or when “0” is to be written into a memory cell, the OR gate OR outputs a high-level signal and causes the read/write transistors RWQ.sub.1 to RWQ.sub.n to turn on.

[0089] A read/write controller 34, in accordance with an instruction from a not-illustrated higher-level device, sets the read enable signal RE to the high level at the time of data read, sets the write control signals WBLH and WSLL to the high level at the time of writing data “0”, and sets the write control signals WBLL and WSLH to the high level at the time of writing data “1”.

[0090] The sense amplifier SA compares voltage at the positive input terminal with voltage of the reference bit line BL.sub.R, and outputs a low-level DATA signal when the voltage at the positive input terminal is lower than voltage at the negative input terminal and outputs a high-level DATA signal when the voltage at the positive input terminal is higher than the voltage at the negative input terminal.

[0091] Each of the memory cells MC.sub.ij includes a magnetic tunneling junction (MTJ) element. The MTJ element includes three layers, namely a pinned (fixed) layer, an insulating layer, and a free layer. Magnetization direction of the pinned layer is fixed, and, even when current flows in the layer, the magnetization direction of the pinned layer does not change. In contrast, magnetization direction of the free layer can be changed, and, when current flows in the layer, the magnetization direction of the free layer changes. The insulation layer is a thin film disposed between the pinned layer and the free layer.

[0092] The MTJ element exhibits a low resistance value R.sub.p while the MTJ element is in a state where the magnetization directions of the pinned layer and the free layer point in the same direction as each other (parallel state) and exhibits a high resistance value R.sub.ap (>R.sub.p) while the MTJ element is in a state where the magnetization directions of the pinned layer and the free layer point in the opposite directions to each other (antiparallel state).

[0093] In the present embodiment, the low resistance value and the high resistance value of the MTJ element are associated with data “0” and data “1”, respectively.

[0094] Next, the reference cells RC.sub.i are described. Each of the reference cells RC.sub.i includes a series circuit of an MTJ element M and a fixed resistor FR. The MTJ element has the same structure (material, size, impurity concentration, and the like) as an MTJ element included in a memory cell MC.sub.ij and is set in a low resistance state (parallel state) where the magnetization directions of the pinned layer and the free layer point in the same direction as each other.

[0095] A resistance value R.sub.offset of the fixed resistor FR is set to a value that is greater than 0 and less than R.sub.ap−R.sub.p (=R.sub.p×MR ratio).

[0096] In addition, the MTJ element in each reference cell RC.sub.i is connected in such a way that, when read current flows, the low resistance state thereof is maintained. For example, at the time of reading, the voltage of the reference bit line BL.sub.R is set to be higher than that of the reference source line SL.sub.R. In the configuration of the present embodiment, the free layer and the pinned layer are connected to the reference bit line BL.sub.R1 and the reference source line SL.sub.R side, respectively.

[0097] Note that a read load transistor RT.sub.j, a bit line BL.sub.j, a selection transistor ST.sub.ij, a source line SL.sub.j, and a read/write transistor RWQ.sub.j function as a resistance-voltage conversion circuit that converts resistance of a memory cell MC.sub.ij to be accessed to voltage.

[0098] The buffer circuit BU.sub.j of the j-th column is an analog buffer circuit to buffer and output an input signal. More specifically, as illustrated in FIG. 2A, the buffer circuit BU.sub.j of the j-th column includes an amplifier circuit OP.sub.j to the positive input terminal (+) of which the first bit line BL.sub.j1 of the j-th column is connected and the output terminal of which is connected to the second bit line BL.sub.j2 and the negative input terminal (−), and amplifies input voltage one-fold and outputs the amplified voltage. The buffer circuit BU.sub.j of the j-th column has a higher current driving capability than current driving capability of the read load transistor RT.sub.j. Note that the current driving capability, that is, driving capability, is capacity of how much current a circuit can pass to an output. The amplifier circuit OP.sub.j ideally has infinite input impedance and zero output impedance and also has an impedance conversion function. The amplifier circuit OP.sub.j is brought to an enabled state when an enable signal supplied to an enable terminal EN is at a low level, that is, when the storage circuit 11 is in a read mode and the corresponding j-th column is selected.

[0099] As illustrated in FIG. 1, the buffer circuit BU.sub.j of the j-th column has the input terminal thereof arranged at a position that is located on the sense amplifier SA side of a connection point between the first bit line BL.sub.j1 and the read load transistor RT.sub.j of the j-th column and a connection point among the first bit line BL.sub.j and the write transistors WTP.sub.j and WTN.sub.j of the j-th column and that is in vicinities of the connection points. In addition, the output terminal of the buffer circuit BU.sub.j of the j-th column is connected to the positive input terminal of the sense amplifier SA via the second bit line BL.sub.j2 and the vertical bit line VBL. In other words, the buffer circuit BU.sub.j of the j-th column is arranged between the load transistor RT.sub.j, which is an example of the resistance-voltage conversion circuit, and the positive input terminal of the sense amplifier SA, which is an example of the first input terminal of the sense amplifier SA.

[0100] The reference buffer circuit BU.sub.R is an analog buffer circuit to buffer and output an input signal. More specifically, as illustrated in FIG. 2B, the reference buffer circuit BU.sub.R also includes an amplifier circuit OP.sub.R to the positive input terminal (+) of which the first reference bit line BL.sub.R1 is connected, the output terminal of which is connected to the second reference bit line BL.sub.R2 and the negative input terminal (−), and the amplification factor of which is set to one-fold. The reference buffer circuit BU.sub.R has a higher current driving capability than current driving capability of the reference read load transistor RT.sub.R. The amplifier circuit OP.sub.R ideally has infinite input impedance and zero output impedance and also has an impedance conversion function. The amplifier circuit OP.sub.R is brought to an enabled state when an enable signal supplied to an enable terminal EN is at the low level, that is, when the storage circuit 11 is in the read mode and a reference cell RC is selected.

[0101] As illustrated in FIG. 1, the reference buffer circuit BU.sub.R has the input terminal thereof arranged at a position that is located on the sense amplifier SA side of a connection point between the first reference bit line BL.sub.R1 and the reference read load transistor RT.sub.R and a connection point between the first reference bit line BL.sub.R1 and the reference write transistor WTP.sub.R and that is in vicinities of the connection points. In addition, the output terminal of the reference buffer circuit BU.sub.R is connected to the negative input terminal of the sense amplifier SA via the reference bit line BL.sub.R. In other words, the reference buffer circuit BU.sub.R is arranged between a reference circuit and the negative input terminal of the sense amplifier SA, which is an example of the second input terminal of the sense amplifier SA.

[0102] Next, operation of the storage circuit 11 having the configuration described above is described.

(Read Operation)

[0103] Read operation is described with reference to timing charts in FIGS. 3A to 31.

[0104] A case where data is read from the memory cell MC.sub.ij in the i-th row and the j-th column is used as an example.

[0105] The column decoder 32 decodes a column address and, as illustrated in FIG. 3B, sets the column line CL.sub.j of the j-th column to the high level and maintains the other column lines CL at the low level at timing t1. In addition, as illustrated in FIG. 3B, the reference column decoder 33 sets the reference column line CL.sub.R to the high level.

[0106] Further, as illustrated in FIG. 3C, the read/write controller 34 sets the read enable signal RE to the high level at timing t1. As a result, both inputs of the NAND gate RG.sub.j of the j-th column are set to the high level, and, as illustrated in FIG. 3D, the output of the NAND gate RG.sub.j is set to the low level. As a result, the read load transistor RT.sub.R turns on. As a result, as illustrated in FIG. 3E, the bit line BL.sub.j1 of the j-th column is charged with the read voltage V.sub.R.

[0107] Likewise, both the voltage of the reference column line CL.sub.R and the read enable signal RE, which are two inputs to the reference NAND gate RG.sub.R, are set to the high level at timing t1. Thus, as illustrated in FIG. 3D, the output of the reference NAND gate RG.sub.R is set to the low level, and the reference read load transistor RT.sub.R turns on. As a result, as illustrated in FIG. 3G, the reference bit line BL.sub.j1 is once charged with the read voltage V.sub.R.

[0108] In addition, the read enable signal RE being set to the high level causes the output of the OR gate OR to be set to the high level, which causes the read/write transistors RWQ.sub.1 to RWQ.sub.n to turn on. As a result, the source line SL.sub.j of the j-th column is connected to a ground. Note that the reference read transistor RWQ.sub.R has the gate pulled up and is always in an on-state. As a result, the reference source line SL.sub.R is connected to the ground.

[0109] Succeedingly, the row decoder 31 decodes a row address and, as illustrated in FIG. 3A, sets the word line WL.sub.i of the i-th row to the high level and maintains the other word lines WL at the low level at timing t2. As a result, the selection transistor ST.sub.ij and the reference selection transistor AT.sub.i turn on.

[0110] The selection transistor ST.sub.ij turning on causes current to flow from the read load transistor RT.sub.j to the first bit line BL.sub.j1, to the memory cell MC.sub.ij, to the source line SL.sub.j, to the read/write transistor RWQ.sub.j, and to the ground, and, as illustrated in FIG. 3E, voltage (data voltage) V.sub.b1 of the first bit line BL.sub.j1 of the j-th column changes to a voltage corresponding to a resistance value of the memory cell MC.sub.ij. Specifically, when the resistance value of the MTJ element included in the memory cell MC.sub.ij, is a high resistance (stored data are “1”), the voltage V.sub.b1 changes to a comparatively high voltage, and, when the resistance value of the MTJ element is a low resistance (stored data are “0”), the voltage V.sub.b1 changes to a comparatively low voltage.

[0111] The first bit line BL.sub.ij of the j-th column is connected to the input terminal of the buffer circuit BU.sub.j, which has a large input impedance. Thus, a portion of the first bit line BL.sub.j1 that is charged by the read load transistor RT.sub.j is short and has a sufficiently small wiring capacitance compared with a conventional case where the entire bit line BL.sub.j including the vertical bit line VBL is charged. Thus, speed of change in the voltage of the first bit line BL.sub.j1 of the j-th column is higher than in the conventional case.

[0112] As illustrated in FIG. 3D, when the output of the NAND gate RG.sub.j is set to the low level at timing t1, the buffer circuit BU.sub.j is brought to the enabled state and outputs a data voltage V.sub.b2, which is the same as a data voltage V.sub.b1 of the first bit line BL.sub.j1, to the second bit line BL.sub.j2. The current driving capability of the buffer circuit BU.sub.j is higher than the current driving capability of the read load transistor RT.sub.j. Therefore, although wiring capacitance of the second bit line BL.sub.j2 and the vertical bit line VBL is comparatively large, the buffer circuit BU.sub.j is capable of charging the second bit line BL.sub.j2 and the vertical bit line VBL at high speed and, as illustrated in FIGS. 3E and 3F, causing the voltage V.sub.b2 of the vertical bit line VBL to follow the data voltage V.sub.b1 of the first bit line BL.sub.j1. The voltage V.sub.b2 of the vertical bit line VBL is supplied to the positive input terminal of the sense amplifier SA.

[0113] When the word line WL.sub.i of the i-th row is set to the high level and the reference selection transistor AT.sub.i turns on at timing t2, current flows from the reference read load transistor RT.sub.R to the first reference bit line BL.sub.R1, to the reference cell RC.sub.i, to the reference selection transistor AT.sub.i, to the reference source line SL.sub.R, to the reference read transistor RWQ.sub.R, and to the ground. Therefore, voltage of the first reference bit line BL.sub.R1 changes to a reference voltage V.sub.ref1, as illustrated in FIG. 3G.

[0114] The reference buffer circuit BU.sub.R was brought to the enabled state at timing t1, and the reference buffer circuit BU.sub.R thus outputs a reference voltage V.sub.ref2, which is the same as the reference voltage V.sub.ref1 of the first reference bit line BL.sub.R1. Since the reference buffer circuit BU.sub.R has a large current driving capability, the reference buffer circuit BU.sub.R is capable of charging the second reference bit line BL.sub.R2 and a vertical bit line VBL.sub.R at high speed and causing the reference voltage V.sub.ref2 to follow change in the reference voltage V.sub.ref1 of the first reference bit line BL.sub.R1, as illustrated in FIG. 3H.

[0115] The sense amplifier SA outputs a high-level output signal DATA when the data voltage V.sub.b2 of the vertical bit line VBL, which is applied to the positive input terminal, is higher than the reference voltage V.sub.ref2, which is applied to the negative input terminal, and outputs a low-level output signal DATA when the data voltage V.sub.b2 of the vertical bit line VBL is lower than the reference voltage V.sub.ref2, as illustrated in FIG. 3I. Performing signal processing with “1” and “0” representing the high level and the low level, respectively, causes stored data in the memory cell MC.sub.ij in the i-th row and the j-th column to be read.

[0116] Subsequently, the word line WL.sub.i, the read enable signal RE, and the column lines CL.sub.j and CL.sub.R are successively set to the low level, and one read cycle is terminated.

[0117] Note that, in the read operation, the write control signals WBLH, WBLL, WSLH, and WSLL are maintained at the low level.

[0118] (Write Operation)

[0119] When data are written into the memory cell MC.sub.ij in the i-th row and the j-th column, the column decoder 32 decodes the column address and, as illustrated in FIGS. 4B and 5B, sets the column line CL.sub.j of the j-th column to the high level and maintains the other column lines CL at the low level.

[0120] On the other hand, the read/write controller 34 controls the write control signals WBLH, WBLL, WSLH, and WSLL according to the write data.

[0121] Since, in a write mode, the read enable signal RE is at the low level, the NAND gates RG.sub.j and RG.sub.R output high-level signals. Thus, the read load transistors RT.sub.j and RT.sub.R turn off, and the buffer circuits BU.sub.j and BU.sub.R are brought to a disabled state and do not operate. Therefore, there is no chance that write current flows into the second bit lines BL.sub.j2 and the vertical bit line VBL.

[0122] First, operation in the case of writing “0” is described.

[0123] The read/write controller 34 sets the write control signals WBLH and WSLL to the high level, as illustrated in FIG. 4C, and maintains the write control signals WBLL and WSLH at the low level, as illustrated in FIG. 4D. As a result, the output of the write NAND gate NG.sub.j of the j-th column is set to the low level, and the write transistor WTP.sub.j turns on. As a result, as illustrated in FIG. 4E, the first bit line BL.sub.ij of the j-th column is brought to the write voltage. Since the first bit line BL.sub.j1 is comparatively short, the time required for charging is a short period of time.

[0124] On the other hand, the write control signal WSLL being set to the high level causes the output of the OR gate OR to be set to the high level, which causes the read/write transistor RWQ.sub.j to turn on, as a result of which, as illustrated in FIG. 4F, the source line SL.sub.j is grounded.

[0125] Succeedingly, the row decoder 31 decodes the row address and, as illustrated in FIG. 4A, sets the word line WL.sub.i of the i-th row to the high level and causes the selection transistor ST.sub.ij to turn on. Then, the selection transistor ST.sub.ij turning on causes current to flow from the write transistor WTP.sub.j to the first bit line BL.sub.j1 of the j-th column, to the memory cell MC.sub.ij, to the source line SL.sub.j, to the read/write transistor RWQ.sub.j, and to the ground. As a result, the MTJ element included in the memory cell MC.sub.ij is set to the parallel state, and the resistance value of the MTJ element changes to a low resistance. In other words, data “0” are written.

[0126] Next, operation in the case of writing data “1” is described.

[0127] In this case, the read/write controller 34 sets the write control signals WBLL and

[0128] WSLH to the high level, as illustrated in FIG. 5D, and maintains the write control signals WBLH and WSLL at the low level, as illustrated in FIG. 5C. As a result, the output of the AND gate AG.sub.j of the j-th column is set to the high level, and the write transistor WTN.sub.j turns on.

[0129] On the other hand, the write control signal WSLH being set to the high level causes the output of the inverter IN to be set to the low level, which causes the write transistor WQ.sub.j to turn on, as a result of which, as illustrated in FIG. 5F, the write voltage V.sub.W is applied to the source line SL.sub.j.

[0130] Succeedingly, the row decoder 31 decodes the row address and, as illustrated in FIG. 5A, sets the word line WL.sub.i of the i-th row to the high level and causes the selection transistor ST.sub.ij to turn on. As a result, current flows from the write transistor WQ.sub.j to the source line SL.sub.j, to the memory cell MC.sub.ij, to the first bit line BL.sub.j1 of the j-th column, to the write transistor WTN.sub.j, and to the ground. The current flows through the MTJ element included in the memory cell MC.sub.ij, the MTJ element is set to the anti-parallel state, and the resistance value of the MTJ element changes to a high resistance. In other words, data “1” are written.

[0131] Subsequently, the word line WL.sub.i, the column line CL.sub.j, the write control signal WBLL, and the write control signal WSLH are successively set to the low level, and one cycle of write processing is terminated.

[0132] (Data Writing into Reference Cell RC.sub.i)

[0133] Into the reference cells, only data “0” are written.

[0134] Writing methods include a method of applying a magnetic field from the outside and a method using write current.

[0135] A method for setting the reference cells RC to the low resistance state (parallel state) by passing write current through the reference cells RC is described below.

[0136] First, the reference column decoder 33 sets the reference column line CL.sub.R to the high level. On the other hand, the read/write controller 34 sets the write control signal WBLH to the high level. As a result, the reference NAND gate NG.sub.R outputs a low-level signal. As a result, the reference write transistor WTP.sub.R turns on.

[0137] On the other hand, the row decoder 31 sets the word line WL.sub.1 to the high level and sets the other word lines WL to a ground level. As a result, the reference selection transistor AT.sub.1 turns on.

[0138] Then, current flows from the reference write transistor WTP.sub.R to the reference bit line BL.sub.R1, to the reference cell RC.sub.1, to the reference selection transistor AT.sub.1, to the reference source line SL.sub.R, to the reference read transistor RWQ.sub.R, and to the ground. As a result, current flows through the MTJ element included in the reference cell RC.sub.1, a free layer MF of the MTJ element is magnetized in the same direction as a pinned layer MP of the MTJ element, and resistance across the MTJ element changes to the low resistance R.sub.p.

[0139] The row decoder 31 sets the word line WL.sub.1 to the low level and the word line WL.sub.2 to the high level when the writing of data “0” into the reference cell RC.sub.1 is completed. Subsequently, by selecting the reference selection transistors AT.sub.3 to AT.sub.m in a sequential manner, current is passed through the reference cells RC.sub.2 to RC.sub.m in a sequential manner and data “0” are written into the MTJ elements.

[0140] In this manner, data “0” can be written into all the reference cells RC.sub.1 to RC.sub.m.

[0141] As described in the foregoing, in the storage circuit 11 according to the present embodiment, a buffer circuit is arranged in each bit line BL. Thus, a portion that the read load transistor RT.sub.j is required to charge at the time of data read is only a first bit line BL.sub.j1 portion, which is relatively short. Therefore, the read load transistor RT.sub.j can charge the wiring capacitance of the first bit line BL.sub.j1 at high speed and thereby establish the data voltage V.sub.b1.

[0142] The buffer circuit BU.sub.j has a larger current driving capability than the read load transistor RT.sub.j. Thus, the buffer circuit BU.sub.j is capable of charging the second bit line BL.sub.j2 and the vertical bit line VBL at higher speed than in the case of charging the second bit line BL.sub.j2 and the vertical bit line VBL with current that has passed the read load transistor RT.sub.j. Therefore, the buffer circuit BU.sub.j can establish the voltage V.sub.b2 at the positive input terminal of the sense amplifier SA in a shorter period of time than in the conventional case. Therefore, it is possible to read data at high speed.

[0143] The reference voltage V.sub.ref2, which is applied to the negative input terminal of the sense amplifier SA, can also be established in a short period of time.

[0144] In addition, it is possible to prevent write current from sneaking into the vertical bit line VBL, improve write speed, and further suppress leakage current and thereby suppress power consumption.

[0145] Specifically, the buffer circuits BU.sub.j and BU.sub.R includes, for example, an amplifier circuit including a known transistor circuit illustrated in FIGS. 6A and 6B.

[0146] Each transistor included in the amplifier illustrated in FIG. 6A includes a MOS transistor that has a larger current driving capability than a read load transistor RT, such as a transistor having a large channel width, and the entire circuit also has a large current driving capability. The positive input terminal is connected to the gate of a MOS transistor, and the input impedance is thus extremely high.

[0147] The amplifier illustrated in FIG. 6B includes the amplifier illustrated in FIG. 6A and an output stage (driving stage) DR. In the case of this configuration, the output stage DR includes a MOS transistor that has a larger current driving capability than a read load transistor RT, such as a transistor having a large channel width, and the entire circuit also has a larger current driving capability than a read load transistor RT.

[0148] Power-supply voltage VDD to be supplied to the buffer circuits BU.sub.j may be a voltage different from the read voltage V.sub.R. In FIG. 6B, the power-supply voltages VDD and VCC may be different from each other.

[0149] Although, in FIGS. 6A and 6B, buffer circuits having characteristics that an amplification factor is one-fold, that is, input voltage Vin is equal to output voltage Vout, were illustrated as examples, the buffer circuits are not limited thereto. Any buffer circuit with whatever input/output characteristics may be used as long as such a buffer circuit does not have adverse effects on comparison between the data voltage V.sub.b1 and the reference voltage V.sub.ref1 in the sense amplifier SA.

[0150] For example, as a buffer circuit BU, an NMOSFET source follower circuit exemplified in FIG. 7A or a PMOSFET source follower circuit exemplified in FIG. 7B can be used. A source follower circuit has characteristics that Vout=Vin−Vgs. In the above equation, Vgs denotes voltage at the gate with respect to the source.

[0151] A case is assumed where, in the circuit configuration illustrated in FIG. 1, a source follower circuit illustrated in FIG. 7A or 7B is used as the buffer circuits BU.sub.j and the reference buffer circuit BU.sub.R. In this case, a difference ΔV.sub.read between voltage applied to the positive input terminal of the sense amplifier SA and voltage applied to the negative input terminal of the sense amplifier SA is expressed by the equation (1):

[00001]$\begin{array}{cc}\begin{array}{c}{\Delta V}_{read}=V_{b2}-V_{\mathrm{ref}2}\\ =\left(V_{b1}-V\mathrm{gs}\right)-\left(V_{\mathrm{ref}1}-V\mathrm{gs}\right)\\ =V_{b1}-V_{\mathrm{ref}1}\end{array}.& \left(1\right)\end{array}$

[0152] As described above, influence of the gate-source voltage Vgs is canceled out between two buffer circuits, namely a buffer circuit BU.sub.j and the buffer circuit BU.sub.R, and the sense amplifier SA is able to output an appropriate signal DATA.

[0153] Although, in the configuration in FIG. 1, the buffer circuit BU.sub.R is arranged in the reference bit line BL.sub.R, no buffer circuit has to be arranged in the reference bit line BL.sub.R when the wiring capacitance of the reference bit line BL.sub.R is small and signal delay is negligible. Likewise, no buffer circuit has to be disposed in a bit line BL located in a vicinity of the sense amplifier SA. From which column onward a buffer circuit BU is disposed can be arbitrarily set.

[0154] Although, in the configuration in FIG. 1, each reference cell RC.sub.i includes a fixed resistor FR and an MTJ element, a fixed resistor FR can be arranged in such a manner as to be shared by a plurality of reference cells RC.sub.i, as illustrated in FIGS. 8A and 8B.

[0155] Although, in the embodiments described above, data “0” and data “1” are assigned to the low and high resistances of an MTJ element, respectively, data “1” and data “0” may be assigned to the low and high resistances of an MTJ element, respectively.

[0156] In the above description, each of the memory cells MC.sub.ij including an MTJ element is connected to a first signal line that is connected to the read load transistor RT.sub.j and the input terminal of the buffer circuit BU.sub.j, and each of the selection transistors ST.sub.ij is connected to a second signal line that is connected to the write transistor WQ.sub.j and the read/write transistor WRQ.sub.j. Thus, the first signal line and the second signal line are referred to as a bit line BL.sub.ij and a source line SL.sub.ij, respectively. However, the selection transistor ST.sub.ij and the memory cell MC.sub.ij may be connected to the first signal line and the second signal line, respectively. In this case, the first signal line and the second signal line serve as a source line and a bit line, respectively. In this case, read current flows from the read load transistor RT.sub.j to the source line SL.sub.j, to the selection transistor ST.sub.ij, to the memory cell MC.sub.ij, to the bit line BL.sub.ij, to the read/write transistor WRQ.sub.j, and to the ground. Likewise, each of the reference cells RC.sub.i is connected to a first reference signal line that is connected to the reference read load transistor RT.sub.R, and each of the reference selection transistors AT.sub.i is connected to a second reference signal line that is connected to the reference read transistor RWQ.sub.R. Thus, the first reference signal line and the second reference signal line are referred to as the reference bit line BL.sub.R and the reference source line SL.sub.R, respectively. However, the reference selection transistor AT.sub.i and the reference cell RC.sub.i may be connected to the first reference signal line and the second reference signal line, respectively. In this case, the first reference signal line and the second reference signal line serve as the reference source line and the reference bit line, respectively. In addition, the name of a signal line, the name of a transistor, and the like can be arbitrarily defined. This applies to the following description.

[0157] The current driving capability of a buffer circuit BU.sub.j is determined, for example, in the following manner.

[0158] The read current passed through a memory cell MC.sub.ij is set to ½ or less of a minimum value of the write current in order not to induce a read disturb malfunction. The above “write current” means current that allows stored data in a memory cell MC.sub.ij to be rewritten by keeping passing the current through the memory cell MC.sub.ij during a preset write time TW. Although, theoretically, if a condition that the minimum value of the write current is greater than the read current is satisfied, no read disturb can occur, the read current is set in a manner as described above in order to maintain margin for fluctuation of various factors, such as variation in voltage, temperature, and a production process. The current driving capability of a buffer circuit BU.sub.j is selected in such a way that, by passing current, the current being larger than current that flows through the vertical bit line VBL without the buffer circuit BU.sub.j disposed, while maintaining a condition that the read current passed through a memory cell MC.sub.ij is less than or equal to ½ of the minimum value of the write current, the vertical bit line VBL can be charged at high speed.

Embodiment 2

[0159] In Embodiment 1, all the buffer circuits BU.sub.j and BU.sub.R were assumed to have the same size. In Embodiment 1, the second bit lines BL.sub.j2 of the respective columns have the same length and substantially the same wiring capacitance. In addition, the vertical bit line VBL is used by all the columns in a shared manner. Therefore, wiring capacitances to be charged by the respective buffer circuits BU.sub.j are the same as one another. However, effective wiring capacitances to be charged in order to establish input voltage at the positive input terminal of the sense amplifier SA are different from one another for each column. For example, in FIG. 1, wiring capacitance that the buffer circuit BU.sub.n of the n-th column is required to charge in order to establish the voltage at the positive input terminal of the sense amplifier SA is larger than wiring capacitance that the buffer circuit BU.sub.1 of the first column is required to charge in order to establish the voltage at the positive input terminal of the sense amplifier SA.

[0160] Focusing on this point, it may be configured such that, as schematically illustrated in FIG. 9, current driving capability of a buffer circuit BU.sub.j is differentiated from the others for each column.

[0161] In a storage circuit 12 in FIG. 9, the current driving capability of the buffer circuits BU.sub.j diminishes in the order of the n-th column, the (n−1)-th column, . . . , and the first column. Note that, in FIG. 9, the current driving capability is indicated by size of a triangle representing a buffer circuit BU. In addition, no buffer circuit is arranged in a reference bit line BL.sub.R.

[0162] Further, it may be configured such that, as illustrated in FIG. 10, one or a plurality of successive columns is grouped into a group and the current driving capability of the buffer circuits BU is differentiated for each group. The numbers of columns belonging to individual groups may be the same or different from one another.

[0163] In the example in FIG. 10, two columns belong to a first group, three columns belong to a second group, . . . , and two columns belong to a k-th group, and, as the group number increases, the current driving capability of a buffer circuit BU.sub.j increases. Note that, in the same group, the current driving capabilities of buffer circuits BU.sub.j are the same. Note also that the configuration in FIG. 9 is equivalent to a configuration in which all the groups include one column.

[0164] The configuration as described above enables read operation to be speeded up, power consumption to be suppressed, and increase in a footprint to be suppressed.

[0165] An arbitrary method for adjusting or differentiating the current driving capability of the buffer circuits BU may be used.

[0166] For example, 1) a method of using buffer circuits BU having the same configuration and differentiating power-supply voltage VDD, 2) a method of, although using buffer circuits BU having the same circuit configuration, differentiating size (in particular, channel width) of transistors included in the buffer circuits BU, 3) a method of differentiating a circuit configuration for each buffer circuit, 4) a method of differentiating the number of buffer circuits connected in parallel, 5) a combination of these methods, or the like can be employed.

Embodiment 3

[0167] Although, in Embodiments 1 and 2, one sense amplifier SA was arranged for the entire memory cell array, a configuration in which a sense amplifier is arranged for each column in a memory cell array as disclosed in International Publication No. WO 2019/112068 can also be employed. In FIG. 11, a main part of a storage circuit 13 having such a configuration is illustrated.

[0168] As illustrated in FIG. 11, in the present embodiment, a sense amplifier SA is arranged for each column of a memory cell array 21.

[0169] A bit line BL.sub.j of the j-th column is connected to a positive input terminal of a sense amplifier SA of the j-th column via a current path of a column selection transistor CT.sub.j.

[0170] In contrast, in a reference bit line BL.sub.R, a buffer circuit BU.sub.R is arranged. In the following description, as with Embodiment 1, reference bit lines connected to an input terminal and an output terminal of the buffer circuit BU.sub.R are referred to as a first reference bit line BL.sub.R1 and a second reference bit line BL.sub.R2, respectively. The second reference bit line BL.sub.R2 is connected to a vertical reference bit line VRBL, which is arranged for sense amplifiers SA1 to SAn in common.

[0171] The buffer circuit BU.sub.R has a larger current driving capability than any one of read load transistors RT.sub.1 to RT.sub.n.

[0172] The vertical reference bit line VRBL extends in the column direction and is connected to negative input terminals of the sense amplifiers SA1 to SAn.

[0173] Read operation of the storage circuit 13 is described. Note that basic operation is the same as the read operation in the storage circuit 11 of Embodiment 1 and the following description is made mainly on differences.

[0174] An example in which data is read from a memory cell MC.sub.ij in the i-th row and the j-th column is described.

[0175] First, when the j-th column is selected and the read load transistor RT.sub.j turns on, the bit line BL.sub.j of the j-th column is charged with read voltage V.sub.R. At the same time, a reference read load transistor RT.sub.R turns on. As a result, the first reference bit line BL.sub.R1 is charged with the read voltage V.sub.R.

[0176] Succeedingly, not-illustrated read/write transistors RWQ.sub.1 to RWQ.sub.n turn on.

[0177] Succeedingly, a word line WL.sub.i of the i-th row is set to a high level and a selection transistor ST.sub.ij and a reference selection transistor AT.sub.i turn on.

[0178] Then, read current flows from the read load transistor RT.sub.j to the bit line BL.sub.j, to the memory cell MC.sub.ij, to a source line SL.sub.j, to the read/write transistor RWQ.sub.j, and to a ground. As a result, voltage (data voltage) V.sub.b of the bit line BL.sub.j of the j-th column changes to a voltage V.sub.b corresponding to a resistance value of the memory cell MC.sub.ij. In the configuration in FIG. 11, no vertical bit line is arranged and the bit lines BL.sub.j are comparatively short. Therefore, the data voltage V.sub.b propagates to the positive input terminal of a sense amplifier SA in a short period of time.

[0179] At the same time, the selection transistor AT.sub.i turning on causes reference current to flow from the reference read load transistor RT.sub.R to the bit line BL.sub.R1, to the reference cell RC.sub.i, to a source line SL.sub.R, to a reference read transistor RWQ.sub.R, and to the ground. The first reference bit line BL.sub.R1 is relatively short and is charged in a short period of time, and voltage of the first reference bit line BL.sub.R1 changes to a reference voltage V.sub.ref1 in a short period of time.

[0180] At the same time as the reference read load transistor RT.sub.R turns on, the reference buffer circuit BU.sub.R is brought to an enabled state. Since the reference buffer circuit BU.sub.R has a high current driving capability, the reference buffer circuit BU.sub.R is capable of rapidly charging the second reference bit line BL.sub.R2 and the vertical reference bit line VRBL and supplying the negative input terminal of the sense amplifier SAj of the j-th column with a reference voltage V.sub.ref2 in a short period of time. Therefore, it is possible to prevent a situation in which it takes time to transmit the reference voltage V.sub.ref2 to the sense amplifier that is located away from the reference circuit and read speed is thereby limited.

Embodiment 4

[0181] Although, in Embodiment 3, an example in which the entire vertical reference bit line VRBL is rapidly charged was described, effective length of a vertical reference bit line VRBL that is required to be charged is different between when the first column is accessed and when the n-th column is accessed. For example, while, when a memory cell MC.sub.j1 in the first column is accessed, only wiring capacitance in a distance to a negative input terminal of a sense amplifier SA1 within the vertical reference bit line VRBL is required to be charged, when a memory cell MC.sub.in in the n-th column is accessed, wiring capacitance of substantially the whole of the vertical reference bit line VRBL is required to be charged. Thus, as with Embodiment 2, driving capability of a buffer circuit BU.sub.R may be adjusted according to a column to be accessed in order to suppress power consumption.

[0182] FIG. 12A exemplifies a configuration in which current driving capability of one buffer circuit BU.sub.R is changed according to a column to be accessed. In FIG. 12A, power-supply voltages VD1 to VDk are prepared as power-supply voltage of the buffer circuit BU.sub.R. VDk> . . . >VD2>VD1 holds.

[0183] A selector 41 decodes a column address, and selects the voltage VD1 by use of a switch SW when a column belonging to a first group that is closest to a reference circuit is to be accessed, selects the voltage VD2 by use of the switch SW when a column belonging to a second group that is second closest to the reference circuit is to be accessed, . . . , and selects the voltage VDk by use of the switch SW when a column belonging to a k-th group that is k-th closest to (farthest from) the reference cell column is to be accessed.

[0184] The buffer circuit BU.sub.R operates with voltage that is applied via the switch SW. Therefore, as the column to be accessed is located farther away from the reference circuit, the power-supply voltage rises in a stepwise manner and the driving capability increases in a stepwise manner.

[0185] FIG. 12B exemplifies a configuration in which a plurality of buffer circuits BU.sub.R1 to BU.sub.Rk having different current driving capabilities is switched according to a column to be accessed. In FIG. 12B, k buffer circuits BU.sub.R1 to BU.sub.Rk are prepared. In terms of current driving capability, the buffer circuits BU.sub.R1 to BU.sub.Rk are ordered as BU.sub.k≥ . . . ≥BU.sub.2≥BU.sub.1.

[0186] A first reference bit line BL.sub.R1 is connected to positive input terminals of the k buffer circuits BU.sub.R1 to BU.sub.Rk in common. Output terminals of the k buffer circuits BU.sub.R1 to BU.sub.Rk are connected to a reference column selection transistor CT.sub.R via transfer gates TG.sub.1 to TG.sub.k, respectively.

[0187] A selector 42 decodes a column address, and supplies an enable signal to the buffer circuit BU.sub.1 and also supplies an on-signal to the transfer gate TG.sub.1 when a column belonging to the first group, which is closest to the reference circuit, is to be accessed, supplies the enable signal to the buffer circuit BU.sub.2 and also supplies the on-signal to the transfer gate TG.sub.2 when a column belonging to the second group, which is second closest to the reference circuit, is to be accessed, . . . , and supplies the enable signal to the buffer circuit BU.sub.k and also supplies the on-signal to the transfer gate TG.sub.k when a column belonging to the k-th group, which is k-th closest to (farthest from) the reference circuit, is to be accessed.

[0188] A buffer circuit BU.sub.R that is set to an enabled state by the selector 42 amplifies input voltage one-fold and applies a reference voltage V.sub.ref2 to the vertical reference bit line VRBL via a transfer gate TG that is in an on-state. Therefore, as the column to be accessed is located farther away from the reference circuit, a buffer circuit BU that has a higher current driving capability is selected and the driving capability increases in a stepwise manner.

[0189] Note that, in the configuration in FIG. 12B, the buffer circuits having different current driving capabilities are achieved by, for example, i) differentiating power-supply voltages supplied to the buffer circuits, ii) differentiating sizes (in particular, channel widths) of transistors included in the buffer circuits from one another, iii) differentiating circuit configurations of the buffer circuits from one another, or iv) a combination of these methods. Alternatively, it may be configured such that, by changing a combination of buffer circuits that are brought to the enabled states at the same time, the current driving capability is changed. The above-described methods are examples, and the achievement method is not limited thereto.

Embodiment 5

[0190] Although, in Embodiment 3, the current driving capability of the reference circuit is increased by arranging the buffer circuit BU.sub.R, the configuration is not limited thereto, and current driving capability itself of a reference circuit may be increased.

[0191] For example, in a storage circuit 14 illustrated in FIG. 13, current driving capability of the reference circuit may be set relatively large by setting size of a reference read load transistor RT.sub.R larger than sizes of read load transistors RT.sub.1 to RT.sub.n.

[0192] For example, i) voltages VE and V.sub.R are set as VE=V.sub.R, ii) the size (in particular, channel width) of the reference read load transistor RT.sub.R is set to be p (p>1) times the sizes (in particular, channel widths) of the read load transistors RT.sub.1 to RT.sub.n, iii) cross-sectional area of a resistor RF included in each reference cell RC.sub.i is increased p-fold and a resistance value thereof is decreased to lip, and iv) cross-sectional area of an MTJ included in each reference cell RC.sub.i is increased p-fold and a resistance value thereof in a parallel state is decreased to R.sub.p/p.

[0193] With such a configuration, it is possible to increase the current driving capability p-fold while maintaining reference voltage V.sub.ref and charge wiring capacitance of a vertical reference bit line VRBL with large current rapidly.

[0194] Alternatively, the voltages VE and V.sub.R are set as VE>V.sub.R, and on-resistance of the reference read load transistor RT.sub.R and resistance (combined resistance of a fixed resistor FR and an MTJ element) of each reference cell RC.sub.i are adjusted in such a way that the reference voltage V.sub.ref expressed by the equation (2) has an appropriate value.

V.sub.ref=VE(R.sub.RF+R.sub.p)/[(R.sub.RF+R.sub.p)+R.sub.on)]  (2)

where R.sub.FR denotes a resistance value of a fixed resistor FR, R.sub.p denotes a resistance value of an MTJ element in the parallel state, and R.sub.on denotes a value of the on-resistance of the reference read load transistor RT.sub.R.

[0195] Further, as illustrated in a storage circuit 15 in FIG. 14, a plurality of reference circuits, for example, p reference circuits, may be arranged in parallel with one another.

[0196] The p reference circuits may have the same current driving capability as one another or have current driving capabilities different from one another.

[0197] A reference column decoder 43 selects one or a plurality of reference circuits and applies an on-signal to the gates of reference read load transistors RT.sub.R of the selected reference circuits in such a way that optimum current driving capability can be obtained according to a column to be accessed.

[0198] The disclosure of the present application may produce an effect when the number m of rows and the number n of columns are large. In contrast, when the number m of rows and the number n of columns are small, an advantage of speed-up is small against a disadvantage of increase in a circuit size by an amount equivalent to a space for arranging buffer circuits BU.sub.j. Thus, a relationship between circuit size and the effect of the present disclosure is verified below.

[0199] FIG. 15 illustrates simulation results of a relationship between length of the vertical bit line VBL (FIG. 1) or the vertical reference bit line VRBL (FIG. 11) and time (wiring driving time) t.sub.read required to drive the vertical bit line VBL or the vertical reference bit line VRBL, which is equivalent to delay time.

[0200] First, in a storage circuit in which neither a buffer circuit BU.sub.j nor a reference buffer circuit BU.sub.R is disposed (FIG. 15), wiring driving time t.sub.read of the vertical bit line VBL is defined by the equation below:

t.sub.read=CL/I.sub.cell.

[0201] In this equation, C denotes capacitance (wiring capacitance or parasitic capacitance) per unit length of the vertical bit line VBL or the vertical reference bit line VRBL. Herein, as a value of C, 208 aF/μm (208×10.sup.−18 F/μm) is set as specified in International Roadmap for Devices and Systems (IRDS) 2018. Note that IRDS forecasts that the above numerical value does not change from the 20-nm generation onward. In addition, L denotes length of the vertical bit line VBL (or the vertical reference bit line VRBL, the same applies hereinafter) and corresponds to the number n of columns. I.sub.cell is current that flows from a read load transistor RT.sub.j to a memory cell MC.sub.ij and a bit line BL.sub.j and the vertical bit line VBL at the time of read operation.

[0202] Sizes in the column direction and the row direction of a combination of a memory cell MC.sub.ij and a selection transistor ST.sub.ij (or a combination of a reference memory cell RC.sub.j and a reference selection transistor AT.sub.i) are 4 F when represented using a minimum processing dimension F because two wirings are required to be laid in each of the column direction and the row direction per combination. In area, the size is 16 F.sup.2.

[0203] Herein, it is assumed that F=20 nm. It is also assumed that voltage of a bit line BL.sub.j is 0.8 V and the size of each transistor is a size determined using a design rule of the 55-nm channel length generation.

[0204] In addition, it is assumed that the read current I.sub.cell, which is passed through each memory cell MC.sub.ij at the time of data read, is 40 μA that is a standard read current in the case of a storage capacity of 128 Mbits and 2.5 μA that the applicants forecast as a standard read current in the case of a storage capacity of 2 Gbits.

[0205] Results of simulation of a relationship between the number of bit lines BL connected to the vertical bit line VBL and the wiring driving time t.sub.read in the case where no buffer circuit BU.sub.j is disposed, which was performed based on the assumptions described above, are illustrated in graphs 1 and 2 in FIG. 15.

[0206] From the graph 2, it is evident that, at a standard read current I.sub.cell=40 μA in the case of a storage capacity of 128 Mbits, which is a comparatively low capacity, the wiring driving time t.sub.read is sufficiently small because there is margin in the read current. In contrast, it is evident that, at a standard read current I.sub.cell=2.5 μA in the case where increase in the storage capacity has advanced and the storage capacity has reached a capacity of 2 Gbits (graph 1), the wiring driving time becomes extremely large as the storage capacity increases. These observations reveal that it is desirable to take a countermeasure against future increase in the storage capacity.

[0207] Next, effects of the embodiments on the wiring driving time are examined.

[0208] As a prerequisite, the configurations of memory cells are the same. It is assumed that voltage of a bit line BL.sub.j is 0.8 V and the read current I.sub.cell=2.5 μA.

[0209] i) Simulation 1:

[0210] A simulation result in the case where a voltage follower circuit illustrated in FIG. 6A or 6B is employed as a buffer circuit BU.sub.j in the storage circuit 11 illustrated in FIG. 1 is illustrated in a graph 3.

[0211] ii) Simulation 2:

[0212] A simulation result in the case where a voltage follower circuit illustrated in FIG. 6A or 6B is employed as a buffer circuit BU.sub.j in the storage circuit 13 illustrated in FIG. 11 is the same as the graph 3 due to similarity in the configurations.

[0213] iii) Simulation 3:

[0214] A simulation result in the case where a source follower circuit illustrated in FIG. 7A or 7B is employed as a buffer circuit BU.sub.j in the storage circuit 11 illustrated in FIG. 1 is illustrated in a graph 4.

[0215] iv) Simulation 4:

[0216] A simulation result in the case where a source follower circuit illustrated in FIG. 7A or 7B is employed as a buffer circuit BU.sub.j in the storage circuit 13 illustrated in FIG. 11 is the same as the graph 4 due to similarity in the configurations.

[0217] v) Simulation 5:

[0218] A simulation result in the case where the number p of reference circuits is set to 2 in the storage circuit illustrated in FIG. 14 is illustrated in a graph 5.

[0219] vi) Simulation 6:

[0220] A simulation result in the case where the number p of reference circuits is set to 4 in the storage circuit illustrated in FIG. 14 is illustrated in a graph 6.

[0221] Comparison between the graph 2 and the graphs 3 to 6 reveals that, although depending on the number of memory cells, the embodiments enables the wiring driving time t.sub.read to be reduced to ½ or less and the read speed to be increased under the common condition that the read current I.sub.cell is set to 2.5 μA.

[0222] The larger the number of memory cells connected to the vertical bit line VBL or the vertical reference bit line VRBL becomes, the larger effect of reduction in the wiring driving time t.sub.read is. This result has a significant effect for future increase in the storage capacity of the memory cells.

[0223] Further analysis reveals that, when, in a configuration in which buffer circuits are arranged, such as the configurations in FIGS. 1 and 11, voltage follower circuits as exemplified in FIG. 6 are employed as buffer circuits BU.sub.j, the wiring driving time t.sub.read of the entire circuit is restricted by a delay time (approximately 1.5 ns) of the voltage follower circuits themselves and the wiring driving time t.sub.read does not depend much on the number of memory cells per wiring. In contrast, when source follower circuits as exemplified in FIG. 7 are employed, delay increases in proportion to a load although delay in the source follower circuits themselves is comparatively small.

[0224] In the configuration in which reference circuits are arranged in parallel, the wiring driving time t.sub.read depends on the number of memories per wiring and the number of parallel reference circuits and decreases as the number of parallel reference circuits increases.

[0225] The simulation results illustrated in FIG. 15 reveals that, even when the respective embodiments cause the storage circuit to be highly integrated and read current to become small, the respective embodiments described above enable the wiring driving time to be suppressed and the read speed to be increased.

[0226] In addition, as illustrated in the simulation results in FIG. 15, when the number of bit lines connected to the vertical bit line VBL or the vertical reference bit line VRBL is less than 256, there is no large difference in the wiring driving time t.sub.read. In contrast, when the number of bit lines connected to the vertical bit line VBL or the vertical reference bit line VRBL becomes greater than or equal to 256, effect of reduction in the wiring driving time becomes larger as the number of bit lines increases. Therefore, it is considered that the respective embodiments are especially effective when the number of bit lines connected to the vertical bit line VBL or the vertical reference bit line VRBL is greater than or equal to 256.

[0227] Although the storage circuits according to a plurality of embodiments of the present disclosure were described above, the present disclosure is not limited to the above-described embodiments and can be changed appropriately.

[0228] For example, the storage element is not limited to the MTJ element, and the storage element is only required to be a variable resistance type element, such as a resistance random access memory (ReRAM). For example, the storage element is not limited to the MTJ element, and the storage element is only required to be a variable resistance type element, such as a resistance random access memory (ReRAM).

[0229] Although an example in which a resistance value can be changed in two steps was described, the resistance value may be changeable in three or more steps. In this case, a reference circuit that generates two or more reference voltages for determining in which step has the resistance is only required to be prepared.

[0230] The present disclosure is not limited to the description of the above-described embodiments and the drawings, and the above-described embodiments and the drawings can be modified as appropriate.

[0231] The foregoing describes some example embodiments for explanatory purposes. Although the foregoing discussion has presented specific embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. This detailed description, therefore, is not to be taken in a limiting sense, and the scope of the invention is defined only by the included claims, along with the full range of equivalents to which such claims are entitled.