STRESS AND/OR STRAIN MEASUREMENT CELL FOR A STRESS AND/OR STRAIN MEASUREMENT SYSTEM

Abstract

A stress and/or strain measurement cell for a stress and/or strain measurement system. The cell includes a reference contact, a sensor contact and a first current mirror circuit which is integrated into a semiconductor material and has a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact. The first conduction path includes a first transistor and the second conduction path includes a second transistor. A first crystal direction of the semiconductor material oriented perpendicular to a first inversion channel of the first transistor is definable for the first inversion channel and a second crystal direction of the semiconductor material oriented perpendicular to a second inversion channel of the second transistor is definable for the second inversion channel. The first crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material.

Claims

1. A stress and/or strain measurement cell for a stress and/or strain measurement system, comprising: a reference contact at which a reference current signal of the stress and/or strain measurement cell is provided; a sensor contact at which a sensor current signal of the stress and/or strain measurement cell is provided; and a first current mirror circuit integrated into a semiconductor material and having a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact, wherein the first conduction path of the first current mirror circuit includes at least one first transistor, and the second conduction path of the first current mirror circuit includes at least one second transistor, a first gate terminal of the first transistor, a first drain terminal of the first transistor and a second gate terminal of the second transistor are at an identical potential; wherein a first crystal direction of the semiconductor material oriented perpendicular to a first inversion channel of the first transistor is definable for the first inversion channel, and a second crystal direction of the semiconductor material oriented perpendicular to a second inversion channel of the second transistor is definable for the second inversion channel, wherein the first crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material.

2. The stress and/or strain measurement cell as recited in claim 1, wherein the first conduction path of the first current mirror circuit further includes a third transistor connected to the first drain terminal of the first transistor, and the second conduction path of the first current mirror circuit further includes a fourth transistor connected to a second drain terminal of the second transistor, and wherein a third gate terminal of the third transistor, a third drain terminal of the third transistor and a fourth gate terminal of the fourth transistor are at an identical potential.

3. The stress and/or strain measurement cell as recited in claim 2, wherein a third crystal direction of the semiconductor material oriented perpendicular to a third inversion channel of the third transistor, which is also oriented perpendicular to a fourth inversion channel of the fourth transistor, is definable for the third inversion channel.

4. The stress and/or strain measurement cell as recited in claim 1, further comprising: a second current mirror circuit integrated into the semiconductor material with a third conduction path connectable or connected to the reference contact or to a further reference contact and with a fourth conduction path connectable or connected to the sensor contact or to a further sensor contact, the third conduction path of the second current mirror circuit including at least one fifth transistor, and the fourth conduction path of the second current mirror circuit including at least one sixth transistor; wherein a fifth gate terminal of the fifth transistor, a fifth drain terminal of the fifth transistor and a sixth gate terminal of the sixth transistor are at an identical potential; wherein a fifth crystal direction of the semiconductor material oriented perpendicular to a fifth inversion channel of the fifth transistor is definable for the fifth inversion channel, and a sixth crystal direction of the semiconductor material oriented perpendicular to a sixth inversion channel of the sixth transistor is definable for the sixth inversion channel, the fifth crystal direction of the semiconductor material being inclined relative to the sixth crystal direction of the semiconductor material, and wherein the fifth crystal direction of the semiconductor material is inclined relative to the first crystal direction of the semiconductor material and/or the sixth crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material.

5. The stress and/or strain measurement cell as recited in claim 4, wherein the third conduction path of the second current mirror circuit further includes a seventh transistor connected to the fifth drain terminal of the fifth transistor and the fourth conduction path of the second current mirror circuit further includes an eighth transistor connected to a sixth drain terminal of the sixth transistor, and wherein a seventh gate terminal of the seventh transistor, a seventh drain terminal of the seventh transistor, and an eighth gate terminal of the eighth transistor are at an identical potential.

6. The stress and/or strain measurement cell as recited in claim 5, wherein a seventh crystal direction of the semiconductor material oriented perpendicular to a seventh inversion channel of the seventh transistor, which is also oriented perpendicular to an eighth inversion channel of the eighth transistor, is definable for the seventh inversion channel.

7. The stress and/or strain measurement cell as recited in claim 4, further comprising: a switch device configured such that, when the switch device is in a first switching state, the first conduction path of the first current mirror circuit is connected to the reference contact and the second conduction path of the first current mirror circuit is connected to the sensor contact and, when the switch device is in a second switching state, the third conduction path of the second current mirror circuit is connected to the reference contact and the fourth conduction path of the second current mirror circuit is connected to the sensor contact.

8. The stress and/or strain measurement cell as recited in claim 1, wherein each of the first transistor and/or the second transistor is a MOSFET.

9. The stress and/or strain measurement cell as recited in claim 2, wherein each of the first transistor and/or the second transistor, and/or the third transistor and/or the fourth transistor is a MOSFET.

10. The stress and/or strain measurement cell as recited in claim 5, wherein each of the fifth transistor and/or the sixth transistor and/or the seventh transistor and/or the eighth transistor, is a MOSFET.

11. A stress and/or strain measurement system for a semiconductor device, comprising: at least one stress and/or strain measurement cell, each including: a reference contact at which a reference current signal of the stress and/or strain measurement cell is provided, a sensor contact at which a sensor current signal of the stress and/or strain measurement cell is provided, and a first current mirror circuit integrated into a semiconductor material and having a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact, wherein the first conduction path of the first current mirror circuit includes at least one first transistor, and the second conduction path of the first current mirror circuit includes at least one second transistor, a first gate terminal of the first transistor, a first drain terminal of the first transistor and a second gate terminal of the second transistor are at an identical potential, wherein a first crystal direction of the semiconductor material oriented perpendicular to a first inversion channel of the first transistor is definable for the first inversion channel, and a second crystal direction of the semiconductor material oriented perpendicular to a second inversion channel of the second transistor is definable for the second inversion channel, wherein the first crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material; wherein the semiconductor material of the stress and/or strain measurement cell is arrangeable or arranged on and/or in the semiconductor device at a respective sensor position of the stress and/or strain measurement cell; and an electronic device configured and/or programed to determine, at least based on the reference current signal provided at the reference contact of the stress and/or strain measurement cell and of the sensor current signal provided at the sensor contact of the stress and/or strain measurement cell, a direction-dependent item of stress and/or strain information for at least the sensor position of the stress and/or strain measurement cell.

12. The stress and/or strain measurement system as recited in claim 11, wherein the stress and/or strain measurement system includes a plurality of stress and/or strain measurement cells as the at least one stress and/or strain measurement cell, wherein the respective semiconductor material of the stress and/or strain measurement cells is arranged on and/or in at least one part of the semiconductor device at a plurality of sensor positions, and wherein the electronic device is configured and/or programed to determine, based on the reference current signals provided at the reference contacts and of the sensor current signals provided at the sensor contacts, an item of information relating to a stress and/or strain distribution on and/or in the at least one part of the semiconductor device as a direction-dependent item of stress and/or strain information.

13. A method for determining a direction-dependent item of stress and/or strain information for at least one sensor position of a semiconductor device, the method comprising the following steps: arranging at least one stress and/or strain measurement cell including a reference contact, a sensor contact, and a first current mirror circuit integrated into a semiconductor material and having a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact, the first conduction path of the first current mirror circuit including at least one first transistor and the second conduction path of the first current mirror circuit including at least one second transistor, wherein a first gate terminal of the first transistor, a first drain terminal of the first transistor, and a second gate terminal of the second transistor, are at an identical potential, and wherein a first crystal direction of the semiconductor material oriented perpendicular to a first inversion channel of the first transistor is definable for the first inversion channel, and a second crystal direction of the semiconductor material oriented perpendicular to a second inversion channel of the second transistor is definable for the second inversion channel and the first crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material, in such a manner that, at least at the sensor position, the semiconductor material of the stress and/or strain measurement cell is located on and/or in the semiconductor device at the sensor position; and determining the direction-dependent item of stress and/or strain information for at least the sensor position of the stress and/or strain measurement cell at least based on a reference current signal provided at the reference contact of the stress and/or strain measurement cell and a sensor current signal provided at the sensor contact of the stress and/or strain measurement cell.

14. The method as recited in claim 13, wherein a plurality of stress and/or strain measurement cells is arranged as the at least one stress and/or strain measurement cell in such a manner that the respective semiconductor material of the stress and/or strain measurement cells is located on and/or in at least one part of semiconductor device at a plurality of sensor positions, and wherein an item of information relating to a stress and/or strain distribution on and/or in the at least one part of the semiconductor device is determined based on the reference current signals provided at the reference contacts and the sensor current signals provided at the sensor contacts as a direction-dependent item of stress and/or strain information.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Further features and advantages of the present invention are explained below with reference to the Figures.

[0017] FIG. 1 is a schematic representation of a first example embodiment of the stress and/or strain measurement cell of the present invention.

[0018] FIG. 2 is a schematic representation of a second example embodiment of the stress and/or strain measurement cell of the present invention.

[0019] FIG. 3 is a schematic representation of one example embodiment of the stress and/or strain measurement system of the present invention.

[0020] FIGS. 4Aa to 4Cc are schematic representations explaining an embodiment of the method for determining a direction-dependent item of stress and/or strain measurement information for at least one sensor position of a semiconductor device, with FIGS. 4Aa and 4Ca showing schematic representations of a stress and/or strain measurement system, FIGS. 4Ab and 4Cb showing a time profile of a stress exerted on the semiconductor device and FIGS. 4Ac and 4Cc showing a time profile of output signals of the stress and/or strain measurement system.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0021] FIG. 1 shows a schematic representation of a first embodiment of the stress and/or strain measurement cell.

[0022] The stress and/or strain measurement cell 10 shown schematically in FIG. 1 has an input contact 12, a reference contact 14 and a sensor contact 16. While the stress and/or strain measurement cell 10 can be supplied with an input current at its input contact 12, a reference current signal i.sub.1 from the stress and/or strain measurement cell 10 is provided at its reference contact 14 and a sensor current signal i.sub.2 from the stress and/or strain measurement cell 10 is provided at its sensor contact 16. The sensor current signal i.sub.2 can also be denoted a “derived current signal” derived from the reference current signal i.sub.1. The stress and/or strain measurement cell 10 also has a first current mirror circuit 18 which is integrated/embedded in a semiconductor material (not shown). The semiconductor material may be silicon, for example. Silicon is, however, not the only semiconductor material from which the stress and/or strain measurement cell 10 can be produced. Instead, the semiconductor material can alternatively or additionally to silicon also include at least one further (semiconductor) material. The first current mirror circuit 18 may also be taken to be a first current mirror 18.

[0023] The first current mirror circuit 18 moreover has a first conduction path 18a electrically connectable or connected to the reference contact 14 and a second conduction path 18b electrically connectable or connected to the sensor contact 16. The first conduction path 18a and the second conduction path 18b can also in each case be denoted a “leg” of the first current mirror circuit 18. In the embodiment of FIG. 1, the first conduction path 18a is electrically (non-decouplably) connected to the reference contact 14 and the second conduction path 18b to the sensor contact 16. The first conduction path 18a of the first current mirror circuit 18 comprises at least one first transistor T.sub.1. The second conduction path 18b of the first current mirror circuit 18 is correspondingly provided with at least one second transistor T.sub.2. A first gate terminal of the first transistor T.sub.1, a first drain terminal of the first transistor T.sub.1 and a second gate terminal of the second transistor T.sub.2 are at an identical potential. This is preferably ensured by the first gate terminal of the first transistor T.sub.1, the first drain terminal of the first transistor T.sub.1 and the second gate terminal of the second transistor T.sub.2 being connected together electrically.

[0024] A first crystal direction of the semiconductor material which is oriented perpendicular to a first inversion channel of the first transistor T.sub.1 is defined/definable for the first inversion channel of the first transistor T.sub.1. A second inversion channel of the second transistor T.sub.2 is also configured such that a second crystal direction of the semiconductor material is oriented perpendicular to the second inversion channel of the second transistor T.sub.2. It is expressly stated here that the first crystal direction of the semiconductor material oriented perpendicular to the first inversion channel of the first transistor T.sub.1 extends inclined relative to the second crystal direction of the semiconductor material oriented perpendicular to the second inversion channel of the second transistor T.sub.2. A first angle of inclination between the first crystal direction of the semiconductor material and the second crystal direction of the semiconductor material is greater than 0° and less than or equal to 90°. The first angle of inclination between the first crystal direction of the semiconductor material and the second crystal direction of the semiconductor material is preferably greater than 20° and less than or equal to 90°, more preferably greater than 40° and less than or equal to 90°. In particular, the first crystal direction of the semiconductor material can be oriented perpendicular to the second crystal direction of the semiconductor material. For example, the first crystal direction oriented perpendicular to the first inversion channel of the first transistor T.sub.1 may be the [110] crystal direction of the silicon used as the semiconductor material and the second crystal direction oriented perpendicular to the second inversion channel of the second transistor T.sub.2 may be the [1-10] crystal direction of the silicon. The crystal directions stated here should, however, only be interpreted as being stated by way of example. The mutually differing orientations of the inversion channels of the first transistor T.sub.1 and of the second transistor T.sub.2 can also be paraphrased as the first transistor T.sub.1 and the second transistor T.sub.2 of the first current mirror circuit 18 having a “twisted” orientation to one another.

[0025] If mechanical stresses arise in the semiconductor material with the first current mirror circuit 18 embedded therein, such as for example in the event of stress and/or strain, the mechanical stresses bring about a change in charge carrier mobility in the inversion channels of transistors T.sub.1 and T.sub.2. However, due to the different orientation of the inversion channels of transistors T.sub.1 and T.sub.2 (in relation to the crystal structure of the semiconductor material), the mechanical stresses bring about non-identical changes in charge carrier mobility in the inversion channels of transistors T.sub.1 and T.sub.2. A difference between a change in charge carrier mobility in the first inversion channel of the first transistor T.sub.1 and a change in charge carrier mobility in the second inversion channel of the second transistor T.sub.2 is for, example, dependent on the direction of orientation of the inversion channels of transistors T.sub.1 and T.sub.2 (in relation to the crystal structure of the semiconductor material), a direction of the mechanical stresses, an applied source voltage at each of transistors T.sub.1 and T.sub.2, an applied gate voltage at each of transistors T.sub.1 and T.sub.2, an applied drain voltage at each of transistors T.sub.1 and T.sub.2, and on minority carrier mobility of transistors T.sub.1 and T.sub.2. The non-identical changes in charge carrier mobility in the inversion channels of transistors T.sub.1 and T.sub.2 moreover result in non-identical changes to the reference current signal i.sub.1 of the stress and/or strain measurement cell 10 and to the sensor current signal i.sub.2 of the stress and/or strain measurement cell 10, or in a variation of a difference Δ of the reference current signal i.sub.1 minus the sensor current signal i.sub.2. Since the difference Δ of the reference current signal i.sub.1 minus the sensor current signal i.sub.2 is dependent on the different orientations of the inversion channels of transistors T.sub.1 and T.sub.2, it is hereafter denoted angle-dependent stress difference Δ.

[0026] The first inversion channel of the first transistor T.sub.1 and the second inversion channel of the second transistor T.sub.2 can thus be utilized as stress-sensitive layers for detecting mechanical stresses. The first current mirror circuit 18 thus has stress and strain sensitivity which is dependent on the different orientations of the inversion channels of transistors T.sub.1 and T.sub.2 (in relation to the crystal structure of the semiconductor material), which can be utilized not only for detecting mechanical stresses, but also for determining the direction of the mechanical stresses. Alternatively, either the change in reference current signal i.sub.1 of the stress and/or strain measurement cell 10 triggered by the mechanical stresses together with the change in sensor current signal i.sub.2 of the stress and/or strain measurement cell 10 likewise triggered by the mechanical stresses or only the change in angle-dependent stress difference Δ can be evaluated for this purpose. The first current mirror circuit 18 can therefore also be denoted first piezoresistive current mirror circuit 18. It is expressly stated here that the different orientations of the inversion channels of transistors T.sub.1 and T.sub.2 can be freely selected and therefore the stress and strain sensitivity of the first current mirror circuit 18 which is dependent thereon can advantageously be “optimized” for any desired stress directions.

[0027] In the stress and/or strain measurement cell of FIG. 1, the first conduction path 18a of the first current mirror circuit 18 is advantageously further additionally provided with a third transistor T.sub.3 connected to the first drain terminal of the first transistor T.sub.1. Correspondingly, the second conduction path 18b of the first current mirror circuit 18 also additionally further comprises a fourth transistor T.sub.4 connected to a second drain terminal of the second transistor T.sub.2. As FIG. 1 shows diagrammatically, a third gate terminal of the third transistor T.sub.3, a third drain terminal of the third transistor T.sub.3 and a fourth gate terminal of the fourth transistor T.sub.4 are at an identical potential. This is achieved by the third gate terminal of the third transistor T.sub.3, the third drain terminal of the third transistor T.sub.3 and the fourth gate terminal of the fourth transistor T.sub.4 being connected together electrically.

[0028] The further development of the first current mirror circuit 18 with the third transistor T.sub.3 and the fourth transistor T.sub.4 creates a cascoded power supply of first current mirror circuit 18 which advantageously assists in stabilizing the current signals i.sub.1 and i.sub.2 provided at the first current mirror circuit 18. This ensures reliable stability of the power supply of the first current mirror circuit 18 despite its stress and strain sensitivity. Although it is frequently the case for an integrated circuit, into which class the first current mirror circuit 18 falls, that a stable operating point for performing undistorted measurements is not ensured, this frequent deficiency of integrated circuits in the first current mirror circuit 18 is remedied by its cascoded power supply. The first current mirror circuit 18 can therefore also be denoted a cascoded current mirror circuit 18.

[0029] A third/fourth crystal direction of the semiconductor material oriented perpendicular to a third inversion channel of the third transistor T.sub.3, which is also oriented perpendicular to a fourth inversion channel of the fourth transistor T.sub.4, is preferably determinable for the third inversion channel of the third transistor T.sub.3. Non-identical orientations of the third inversion channel of the third transistor T.sub.3 and of the fourth inversion channel of the fourth transistor T.sub.4 (in relation to the crystal structure of the semiconductor material) are thus not necessary.

[0030] The first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3 and/or the fourth transistor T.sub.4 are preferably each a MOSFET. For example, the first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3 and/or the fourth transistor T.sub.4 are each a p-MOSFET. Alternatively, the first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3 and/or the fourth transistor T.sub.4 can each be an n-MOSFET. By using just one type of transistor, manufacturing costs and effort for the stress and/or strain measurement cell 10 of FIG. 1 can be minimized. Using just one type of transistor likewise ensures uniform temperature effects of the stress and/or strain measurement cell 10 of FIG. 1.

[0031] FIG. 2 shows a schematic representation of a second embodiment of the stress and/or strain measurement cell.

[0032] The stress and/or strain measurement cell 10 of FIG. 2 additionally further has, as a complement to the previously described embodiment, a second current mirror circuit 20 integrated into the semiconductor material with a third conduction path 20a connectable or connected to the reference contact 14 or to a further reference contact and with a fourth conduction path 20b connectable or connected to the sensor contact 16 or to a further sensor contact. The third conduction path 20a of the second current mirror circuit 20 has at least one fifth transistor T.sub.5. The fourth conduction path 20b of the second current mirror circuit 20 correspondingly comprises at least one sixth transistor T.sub.6. As is apparent from FIG. 2, a fifth gate terminal of the fifth transistor T.sub.5, a fifth drain terminal of the fifth transistor T.sub.5 and a sixth gate terminal of the sixth transistor T.sub.6 are at an identical potential, which is specifically achieved by means of an electrical connection of the fifth gate terminal of the fifth transistor T.sub.5, of the fifth drain terminal of the fifth transistor T.sub.5 and of the sixth gate terminal of the sixth transistor T.sub.6.

[0033] A fifth crystal direction of the semiconductor material which is oriented perpendicular to a fifth inversion channel of the fifth transistor T.sub.5 is defined/definable for the fifth inversion channel of the fifth transistor T.sub.5. A sixth crystal direction of the semiconductor material oriented perpendicular to a sixth inversion channel of the sixth transistor T.sub.6 is correspondingly also determinable for the sixth inversion channel, wherein the sixth crystal direction of the semiconductor material extends inclined relative to the fifth crystal direction of the semiconductor material. A second angle of inclination between the fifth crystal direction of the semiconductor material and the sixth crystal direction of the semiconductor material is preferably greater than 20° and less than or equal to 90°, more preferably greater than 40° and less than or equal to 90°. In particular, the fifth crystal direction of the semiconductor material can be oriented perpendicular to the sixth crystal direction of the semiconductor material. Moreover, the fifth crystal direction of the semiconductor material is inclined relative to the first crystal direction of the semiconductor material and/or the sixth crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material. More preferably, a third angle of inclination between the fifth crystal direction of the semiconductor material and the first crystal direction of the semiconductor material and/or a fourth angle of inclination between the sixth crystal direction of the semiconductor material and the second crystal direction of the semiconductor material are greater than 20° and less than or equal to 90°, specifically greater than 40° and less than or equal to 90°. Moreover it is sometimes advantageous for the second crystal direction of the semiconductor material to be rotated about a first axis of rotation in relation to the first crystal direction of the semiconductor material, while the fifth crystal direction of the semiconductor material in relation to the first crystal direction of the semiconductor material and/or the sixth crystal direction of the semiconductor material in relation to the second crystal direction are rotated about a second axis of rotation which is oriented inclined relative to the first axis of rotation. The second axis of rotation can in particular be oriented perpendicular to the first axis of rotation.

[0034] The two current mirror circuits 18 and 20 can be used as piezoresistive current mirror circuits 18 and 20. Providing the stress and/or strain measurement cell 10 of FIG. 2 with the two current mirror circuits 18 and 20 means that its stress and strain sensitivity is increased for further stress directions in comparison with the stress and strain sensitivity of the first current mirror circuit 18 alone. The stress and/or strain measurement cell 10 shown in FIG. 2 can, as a further development, further have at least one third current mirror circuit which in each case has at least some of the above-described features of the second current mirror circuit 20. The stress and strain sensitivity of the stress and/or strain measurement cell 10 can be additionally optimized by concatenating at least three current mirror circuits of different orientations.

[0035] As an advantageous further development of the stress and/or strain measurement cell 10 of FIG. 2, the third conduction path 20a of the second current mirror circuit 20 also comprises a seventh transistor T.sub.7 connected to the fifth drain terminal of the fifth transistor T.sub.5 and the fourth conduction path 20b of the second current mirror circuit 20 also comprises an eighth transistor T.sub.8 connected to a sixth drain terminal of the sixth transistor T.sub.6, wherein a seventh gate terminal of the seventh transistor T.sub.7, a seventh drain terminal of the seventh transistor T.sub.7 and an eighth gate terminal of the eighth transistor T.sub.8 are at an identical potential. The two current mirror circuits 18 and 20 thus have the advantages already described above of a cascoded power supply and can therefore be denoted cascoded current mirror circuits 18 and 20. Moreover, a seventh/eighth crystal direction of the semiconductor material oriented perpendicular to a seventh inversion channel of the seventh transistor T.sub.7, which is also oriented perpendicular to an eighth inversion channel of the eighth transistor T.sub.8, can be determinable for the seventh inversion channel of the seventh transistor T.sub.7. Non-identical orientations of the seventh inversion channel of the seventh transistor T.sub.7 and of the eighth inversion channel of the eighth transistor T.sub.8 (in relation to the crystal structure of the semiconductor material) are thus not necessary.

[0036] The stress and/or strain measurement cell 10 of FIG. 2 additionally also has a switch device 22 which is configured such that, when the switch device 22 is in a first switching state, the first conduction path 18a of the first current mirror circuit 18 is connected to the reference contact 14 and the second conduction path 18b of the first current mirror circuit 18 is connected to the sensor contact 16 and, when the switch device 22 is in a second switching state, the third conduction path 20a of the second current mirror circuit 20 is connected to the reference contact 14 and the fourth conduction path 20b of the second current mirror circuit 20 is connected to the sensor contact 16. By using the switch device 22, it is possible to “select” between the stress and strain sensitivity of the first current mirror circuit 18 and the stress and strain sensitivity of the second current mirror circuit 20 for the stress and/or strain measurement cell 10. This can also provide additional information for determining the direction of the mechanical stresses. The reference current signal i.sub.1 provided at reference contact 14 and the sensor current signal i.sub.2 provided at sensor contact 16 can be individually evaluated for each switching state of the switch device 22 for evaluation of the stress and/or strain measurement cell of FIG. 2. Preferably, however, the angle-dependent stress difference Δ already defined above is evaluated for each switching state of the switch device 22, which assists with reducing component scatter effects.

[0037] The first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3, the fourth transistor T.sub.4, the fifth transistor T.sub.5, the sixth transistor T.sub.6, the seventh transistor T.sub.7 and/or the eighth transistor T.sub.8 are preferably each a MOSFET in the stress and/or strain measurement cell 10 of FIG. 2 as well. The first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3, the fourth transistor T.sub.4, the fifth transistor T.sub.5, the sixth transistor T.sub.6, the seventh transistor T.sub.7 and/or the eighth transistor T.sub.8 can each be a p-MOSFET. Alternatively, the first transistor T.sub.1, the second transistor T.sub.2, the third transistor T.sub.3, the fourth transistor T.sub.4, the fifth transistor T.sub.5, the sixth transistor T.sub.6, the seventh transistor T.sub.7 and/or the eighth transistor T.sub.8 can each be an n-MOSFET. As a result of using just one type of transistor, manufacturing costs are reduced, manufacturing effort lowered and temperature effects minimized for the stress and/or strain measurement cell 10 of FIG. 2 as well.

[0038] FIG. 3 is a schematic representation of one embodiment of the stress and/or strain measurement system.

[0039] The stress and/or strain measurement system shown schematically in FIG. 3 can be used for a semiconductor device 24 in order to detect the occurrence of stress and/or strain at at least one sensor position Pa and Pb of the semiconductor device 24. For this purpose, the stress and/or strain measurement system has at least one stress and/or strain measurement cell 10a and 10b, wherein the semiconductor material of the stress and/or strain measurement cell 10a and 10b is arrangeable/arranged on and/or in the semiconductor device 24 at a respective sensor position Pa and Pb of the stress and/or strain measurement cell 10a or 10b. The semiconductor device 24 may be, for example, a micromechanical component, a control device and/or a sensor device, such as in particular an inertial sensor. It is, however, expressly stated that usability of the stress and/or strain measurement system is not limited to the examples of semiconductor device 24 stated here.

[0040] The stress and/or strain measurement system also has an electronic device 26 which is designed and/or programed to determine, at least on the basis of the reference current signal i.sub.1a and i.sub.1b provided at the reference contact of the stress and/or strain measurement cell 10a or 10b and of the sensor current signal i.sub.2a and i.sub.2b provided at the sensor contact of the stress and/or strain measurement cell 10a or 10b, a direction-dependent item of stress and/or strain information 28 for at least the sensor position Pa and Pb of the stress and/or strain measurement cell 10a or 10b. In an advantageous further development, the stress and/or strain measurement system may comprise a plurality of stress and/or strain measurement cells 10a or 10b, wherein the respective semiconductor material of the stress and/or strain measurement cells 10a or 10b is arranged on and/or in at least one part of the semiconductor device 24 at a plurality of sensor positions Pa and Pb. The electronic device 26 may in this case be designed and/or programed to determine, on the basis of the reference current signals i.sub.1a and i.sub.1b provided at the reference contacts and of the sensor current signals i.sub.2a and i.sub.2b provided at the sensor contacts, an item of information relating to a stress and/or strain distribution on and/or in the at least one part of the semiconductor device 24 as a direction-dependent item of stress and/or strain information 28. In particular, the stress and/or strain measurement system may be designed and/or programed to carry out at least some of the method steps described below.

[0041] FIGS. 4Aa to 4Cc are schematic representations explaining an embodiment of the method for determining a direction-dependent item of stress and/or strain measurement information for at least one sensor position of a semiconductor device, with FIGS. 4Aa and 4Ca showing schematic representations of a stress and/or strain measurement system, FIGS. 4Ab and 4Cb showing a time profile of a stress exerted on the semiconductor device and FIGS. 4Ac and 4Cc showing a time profile of output signals of the stress and/or strain measurement system.

[0042] At the beginning of the method, at least one stress and/or strain measurement cell 10a and 10b with a reference contact, a sensor contact and a first current mirror circuit, which is integrated into a semiconductor material and has a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact, wherein the first conduction path of the first current mirror circuit comprises at least one first transistor and the second conduction path of the first current mirror circuit comprises at least one second transistor, and wherein a first gate terminal of the first transistor, a first drain terminal of the first transistor and a second gate terminal of the second transistor are at an identical potential, is arranged in such a manner at the sensor position Pa and Pb that the semiconductor material of the stress and/or strain measurement cell 10a and 10b is located on and/or in the semiconductor device 24 at sensor position Pa and Pb. As FIGS. 4Aa to 4Ca show diagrammatically, it is ensured when arranging the at least one stress and/or strain measurement cell 10a and 10b at its sensor position Pa and Pb that a first crystal direction n.sub.1a and n.sub.1b of the semiconductor material oriented perpendicular to a first inversion channel of its first transistor T.sub.1 is in each case definable for the first inversion channel of its first transistor T.sub.1 and a second crystal direction n.sub.2a and n.sub.2b of the semiconductor material oriented perpendicular to a second inversion channel of its second transistor T.sub.2 is in each case definable for the second inversion channel of its second transistor T.sub.2, wherein the first crystal direction n.sub.1a and n.sub.1b of the semiconductor material for the at least one stress and/or strain measurement cell 10a and 10b extends inclined relative to the second crystal direction n.sub.2a and n.sub.2b of the semiconductor material of the same stress and/or strain measurement cell 10a and 10b. In particular, a plurality of stress and/or strain measurement cells 10a and 10b may be arranged such that the respective semiconductor material of the stress and/or strain measurement cells 10a and 10b is located on and/or in at least one part of the semiconductor device 24 at a plurality of sensor positions Pa and Pb. Not only can the definable first crystal directions n.sub.1a and n.sub.1b be oriented differently from one another but also the definable second crystal directions n.sub.2a and n.sub.2b can be oriented differently from one another for the plurality of stress and/or strain measurement cells 10a and 10b as well.

[0043] The direction-dependent item of stress and/or strain information 28 for at least the sensor position Pa and Pb of the stress and/or strain measurement cell 10a and 10b is then determined at least on the basis of a reference current signal i.sub.1a and i.sub.1b provided at the reference contact of the stress and/or strain measurement cell and of a sensor current signal i.sub.2a and i.sub.2b provided at the sensor contact of the stress and/or strain measurement cell. In the example of FIGS. 4A to 4C, angle-dependent stress differences Δa=i.sub.1a−i.sub.2a and Δb=i.sub.1b−i.sub.2b are calculated as output signals for this purpose.

[0044] Although, in the example of FIGS. 4Aa-4Ac, a first stress direction 30a of a stress σ exerted on the semiconductor device 24 is oriented perpendicular to a second stress direction 30b of the stress σ exerted in the example of FIGS. 4Ba-4Bc, while a third stress direction 30c of the stress σ of the example of FIGS. 4Ca-4Cc is located between the first stress direction 30a and the second stress direction 30b, a comparison of FIGS. 4Ac to 4Cc reveals that the stress and/or strain measurement cells 10a and 10b have elevated sensitivity for all stress directions 30a to 30c due to the different orientations of their definable first crystal directions n.sub.1a and n.sub.1b and their definable second crystal directions n.sub.2a and n.sub.2b. By configuring the current mirror circuits of the stress and/or strain measurement cells 10a and 10b as cascoded current mirror circuits, it is also possible to ensure sufficient stability of their power supply so that reliable measurements can be carried out. An item of information relating to a stress and/or strain distribution on and/or in the at least one part of the semiconductor device 24 can thus reliably be determined as a direction-dependent item of stress and/or strain information 28 on the basis of the output signals Δa and Δb.