Abstract
A gate driver circuit includes a pulse generator that receives an input signal and generates a pulse signal in response to a switch-on command included in the input signal. The pulse signal has a pulse with a pulse length that is dependent on a level of a pulse control signal. The circuit further includes a sampling circuit that samples an output voltage subsequent to the pulse and stores a respective sampled value, and a controller that receives the sampled value of the output voltage and a reference voltage and updates the level of the pulse control signal based on the sampled value and the reference voltage. A driver circuit generates the output voltage based on the pulse signal.
Claims
1. A circuit comprising: a pulse generator configured to receive an input signal and to generate a pulse signal in response to a switch-on command included in the input signal, the pulse signal having a pulse with a pulse length that is dependent on a level of a pulse control signal; a sampling circuit configured to sample an output voltage subsequent to the pulse and to store a respective sampled value; a controller configured to receive the sampled value of the output voltage and a reference voltage and to update the level of the pulse control signal based on the sampled value and the reference voltage; and a driver circuit configured to generate the output voltage based on the pulse signal.
2. The circuit of claim 1, wherein the pulse control signal has a predetermined initial level before being updated for a first time.
3. The circuit of claim 2, wherein the initial level is set to such a level, that a resulting pulse length is short enough that the generated output voltage is below a predefined maximum voltage value.
4. The circuit of claim 1, wherein the driver circuit operably receives a supply voltage that is higher than a predetermined maximum voltage value.
5. The circuit of any of claim 1, wherein the driver circuit includes an output resistor.
6. The circuit of claim 1, wherein the pulse generator uses the updated level when generating a subsequent pulse in response to a subsequent switch-on command included in the input signal.
7. The circuit of claim 1, wherein the sampling circuit is configured to store the sampled value in a first capacitor, the sampled value being represented by a respective capacitor voltage.
8. The circuit of claim 1, wherein the controller comprises a differential amplifier configured to output, as pulse control signal, a signal representing a difference between the sampled value and the reference voltage.
9. The circuit of claim 1, wherein the pulse control signal is a control current, and wherein the pulse generator is configured to generate a ramp signal with a steepness depending on the control current, the pulse length being determined by a time at which a level of the ramp signal reaches a reference value.
10. A switching converter comprising: a power transistor having a gate electrode and a load terminal coupled to an inductor, wherein the gate electrode is coupled to the circuit of claim 1 so that the output voltage of the circuit is applied to the gate electrode.
11. A method comprising: generating a pulse signal in response to a switch-on command included in an input signal, the pulse signal having a pulse with a pulse length that is dependent on a level of a pulse control signal; generating an output voltage based on the pulse signal [using a driver circuit (ii)]; sampling the output voltage subsequent to the pulse and storing a respective sampled value; and updating the level of the pulse control signal based on the sampled value and a reference voltage.
12. The method of claim 11, wherein generating the pulse signal comprises: generating a ramp signal with a steepness depending on the pulse control signal, the pulse length being determined by a time at which a level of the ramp signal reaches a reference value.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for the purpose of illustration, show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
[0008] FIG. 1 illustrates one common implementation of a gate driver circuit for driving a high-side transistor;
[0009] FIG. 2(a) illustrates an equivalent circuit of the driver circuit and a timing diagram,
[0010] FIG. 2(b) illustrates the charging process of the transistor gate;
[0011] FIG. 3 illustrates, in a schematic timing diagram, the charging process of a transistor gate when using a driver circuit according to the embodiments described herein;
[0012] FIG. 4 illustrates one approach that might be obvious but that will not work in practical applications;
[0013] FIG. 5 illustrates timing diagrams illustrating, by way of example, the operation principle of the embodiments described herein;
[0014] FIG. 6 illustrates one example implementation of a gate driver circuit in accordance with one embodiment;
[0015] FIG. 7 illustrates one exemplary implementation of the pulse generator used in the example of FIG. 6 in more detail; and
[0016] FIG. 8 illustrates one exemplary application of the gate driver circuit of FIG. 6.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0017] FIG. 1 illustrates one common implementation of a gate driver circuit for driving a high-side transistor. In the present example, the high-side transistor is a power transistor (e.g., a DMOS transistor) denoted as M.sub.D. The diode D.sub.R coupled in parallel to the transistors drain-source current path represents the transistor's intrinsic body diode, which is always present in most semiconductor fabrication technologies. The gate driver circuit 11 includes a series of CMOS inverter circuits, wherein the input signal IN, applied to the input of the driver circuit is a logic signal, which is basically forwarded to the power transistor's gate electrode. When the power transistor M.sub.D is switched on, the source voltage V.sub.S (at circuit node N.sub.S) will be close to the drain voltage V.sub.B of the transistor M.sub.D and, therefore, the supply voltage V.sub.BOOT for the gate driver 11 needs to be shifted to a voltage level higher than the drain voltage V.sub.B applied to the power transistor M.sub.D. This is usually accomplished by a so-called boot-strap circuit.
[0018] In the present example the boot-strap circuit 10 includes a series circuit composed of rectifier diode D.sub.B and capacitor C.sub.B, wherein the series circuit is coupled between a circuit node providing the supply voltage V.sub.B and circuit node N.sub.S. The capacitor C.sub.B is charged while the transistor M.sub.D is off and the circuit node N.sub.S is pulled to lower voltage levels (e.g., close to ground). The capacitor C.sub.B is charged up to a voltage V.sub.BOOT which is limited by the Zener voltage of Zener diode D.sub.Z coupled in parallel to the capacitor C.sub.B. When the transistor M.sub.D is switched on, the circuit node N.sub.S is pulled close to the supply voltage V.sub.S and the rectifier diode D.sub.B becomes reverse biased (and blocking) which the capacitor C.sub.B still can provide the supply voltage V.sub.BOOT to the gate driver 11. Various implementations of boot-strap circuits are known and are thus not further discussed herein.
[0019] FIG. 2(a) illustrates an equivalent circuit of the gate driver circuit and the transistor gate connected thereto. The transistor gate is represented by the capacitance C.sub.EQ, which is basically determined by the gate capacitance of the power transistor M.sub.D. The resistor R.sub.EQ coupled in series to the capacitor C.sub.EQ represents the effective output resistance of the gate driver circuit 11, and the voltage source represents the voltage V.sub.BOOT provided by the capacitor C.sub.B shown in FIG. 1. For further discussion, we assume the capacitor C.sub.EQ is discharged. When the switch SW is closed, the voltage V.sub.BOOT is applied to the series circuit of resistor R.sub.EQ and capacitor C.sub.EQ causing the capacitor C.sub.EQ to be charged. FIG. 2(b), illustrates a timing diagram of the voltage V.sub.G across the capacitor C.sub.EQ, which corresponds to the gate-source voltage in the circuit of FIG. 1. The equivalent circuit of FIG. 2(a) is a first-order low pass having a time constant of τ=R.sub.QEC.sub.EQ. It takes usually a time of 4τ to 5τ to charge the gate capacitance C.sub.EQ to a level V.sub.Go (approximately 3V in the current example) that is sufficiently high to drive the transistor into its low-ohmic state (on-resistance R.sub.ON of transistor M.sub.D). The level V.sub.Go basically corresponds to the bootstrap voltage V.sub.BOOT. The embodiments described herein aim at shortening the charging time to significantly shorter time spans.
[0020] The timing diagram in FIG. 3 illustrates how the charging curve if FIG. 2(b) changes if the bootstrap voltage V.sub.BOOT is increased from V.sub.Go to V.sub.G1, which is approximately 8 V in the present example. Due to the higher bootstrap voltage V.sub.BOOT, the.sub.gate voltage V.sub.G reaches the target level of V.sub.Go in significantly less time. In the depicted example, the level V.sub.Go s reached in a charging time of T.sub.CH which can be significantly lower than the time constant τ. The problem with increasing the bootstrap voltage to, e.g., 8 V is that the charging process must be reliably interrupted as soon as the target level of 3V is reached. Otherwise the gate oxide of the power transistor may be destroyed.
[0021] One straight-forward approach to limit the gate voltage to a target voltage V.sub.Go significantly lower than the bootstrap voltage V.sub.BOOT is illustrated in FIG. 4. The circuit of FIG. 4 basically corresponds to the circuit of FIG. 1 with an additional comparator 12, which is configured to compare the gate voltage V.sub.G present at the transistor's gate electrode with the desired target voltage V.sub.Go (wherein V.sub.Go<V.sub.BOOT) and detect the gate voltage V.sub.G reaching the target level V.sub.Go. If this is the case, the comparator triggers disables the gate driver 11 thus stopping the charging process of the gate capacitance. Unfortunately, in practice, the approach shown in FIG. 4 will not work for most applications because of the comparator delay and the propagation delay within the gate driver 11. During this delay time, the gate voltage will rise to levels above the target voltage which can damage the gate oxide of the power transistor M.sub.D.
[0022] The embodiments described below use an approach different from the approach illustrated in FIG. 4 to reliably limit the gate voltage V.sub.G to the desired target voltage V.sub.Go while using significantly higher bootstrap voltages (e.g., 8 V or higher). The concept is first explained using the timing diagrams of FIG. 5. The first diagram (top) of FIG. 5 illustrates the control signal IN, which can be regarded as the input signal of the gate driver circuit. The signal IN is a logic signal indicating (e.g., by a high signal level for a time interval T.sub.ON) the desired switching state of the power transistor M.sub.D. The rising edge of the signal IN triggers the process of charging the gate capacitance of the power transistor M.sub.D.
[0023] However, the gate capacitance is not charged for the whole time interval T.sub.ON but only for a short time interval T.sub.CH, which is indicated by a high level of signal IN′ (see third diagram (from the top) of FIG. 5). The time intervals T.sub.ON and T.sub.CH begin at the same time instant, wherein T.sub.CH is only a fraction of T.sub.ON. As can be seen in the second diagram of FIG. 5, the gate voltage V.sub.G rises during the time interval T.sub.CH (as the charge stored in the gate capacitor increases), whereas the gate voltage V.sub.G remains basically constant after the time interval T.sub.CH during the remaining part of the time interval T.sub.ON. At the end of the time interval T.sub.ON (on-time) the gate capacitor is discharged (e.g., by connecting the gate electrode to the source electrode of the power transistor by a low-ohmic current path and, consequently, the transistor is switched off.
[0024] The time T.sub.CH is adjustable and is initially set to a default value small enough to ensure that the gate voltage V.sub.G will not exceed the target value V.sub.Go even if the combination of the actual parameters V.sub.BOOT, R.sub.EQ and C.sub.EQ (cf. FIGS. 2(a) and 2(b)), which may vary due to tolerances, represent a worst case (bootstrap voltage at the higher end and the time constant R.sub.EQC.sub.EQ at the lower end). At the end of the charging time T.sub.CH the actual voltage level at the gate electrode is sampled, e.g., using a sample and hold circuit. The sampling time instant is determined by the rising edge of the signal SMP, which may immediately follow after the falling edge of the signal IN′ (see fourth (bottom) diagram of FIG. 5). The time T.sub.CH can then be adjusted based on the sampled gate voltage level. If the sampled value is lower than the target value V.sub.Go, then the time T.sub.CH is increased by a specific amount so that, in the next switching cycle, the gate is charged to a somewhat higher level as in the preceding cycle. Conversely, if the sampled value is higher than the target value V.sub.Go, then the time T.sub.CH is decreased. If the sampled value equals the target level V.sub.Go, then the time T.sub.CH may remain unchanged.
[0025] On exemplary implementation of the concept explained above is illustrated in FIG. 6 (gate control circuit boo). FIG. 6 shows the power MOS transistor M.sub.D whose drain-source current path is coupled between the circuit nodes ND (connected to drain) and N.sub.S (connected to source). The supply voltage V.sub.B is applied to the node ND. An impedance (load, not shown) may be connected between node N.sub.S and a reference potential (e.g., ground). Similar to FIG. 1, the gate driver 11 is supplied by the bootstrap voltage V.sub.BOOT, wherein the floating potential at node N.sub.S is the reference potential for the gate driver circuit 11. Different from the circuit of FIG. 1, the pulse signal IN′ is supplied to the input of the gate driver 11, which produces a corresponding output signal. As shown in FIG. 5, the signal IN includes, in each switching cycle, a short pulse with an adjustable pulse length T.sub.CH. According to the example of FIG. 6, a pulse generator 20 is configured to receive the input signal IN (cf., FIG. 5) and to generate the pulse signal IN′ in response to a rising edge if the input signal IN, wherein the pulse length T.sub.CH is dependent on a level of a pulse control signal S.sub.CH. It is noted that, in the present example, the rising edge of the input signal IN serves as a switch-on command, which initiates the process of switching-on the transistor M.sub.D. Other types of switch-on commands (e.g., a falling edge, a specific digital word received via a serial communication link, etc.) may be used dependent on the actual application.
[0026] The example of FIG. 6 further includes a sampling circuit 21 that is configured to sample the gate voltage V.sub.G generated by the gate driver 11 subsequent to the pulse (i.e., after the time interval T.sub.CH, see FIG. 5) and to store a respective sampled value V.sub.SMP. A controller 22 is configured to receive the sampled value V.sub.SMP and a reference voltage V.sub.REF (that represents the desired target gate voltage) and to update the level of the pulse control signal S.sub.CH based on the sampled value V.sub.SMP and the reference voltage V.sub.REF. In the depicted embodiment, the controller is basically a difference amplifier which amplifies the difference V.sub.REF-V.sub.SMP. This means basically a P-controller. However, other types of controllers may be used in other embodiments. If, in one switching cycle, the gate voltage V.sub.G—and thus the sampled value V.sub.SMP—is lower than the reference value V.sub.REF, then the pulse control signal S.sub.CH will be adjusted to increase the time T.sub.CH in the next switching cycle, which will result in a higher gate voltage V.sub.G. Similarly, if the gate voltage V.sub.G—and thus the sampled value V.sub.SMP—is higher than the reference value V.sub.REF, then the pulse control signal S.sub.CH will be adjusted to decrease the time T.sub.CH in the next switching cycle, which will result in a lower gate voltage V.sub.G. In steady state with continuously repeating switching cycles, the gate voltage V.sub.G will approximately be equal to the reference voltage value V.sub.REF.
[0027] Before being updated for the first time, the level of the pulse control signal S.sub.CH is at a predetermined initial level. The initial level may be used to generate the first pulse in response to the first switch-on command after a startup (power-on) of the circuit.
[0028] FIG. 7 illustrates one example implementation of the pulse generator circuit 20 in more detail. In the depicted example, it is assumed that the controller 22 has a current output like, for example, a transconductance amplifier. The controller 22 sinks a current i.sub.CH at its output, wherein the current i.sub.CH depends on the difference V.sub.REF−V.sub.SMP. The higher the difference V.sub.REF−V.sub.SMP, the higher the current i.sub.CH at the output of controller 22. The current i.sub.CH is “mirrored” to another current path by a first current mirror CM.sub.1. That is the current i.sub.CH passes though the input path of current mirror CAC that is coupled to the output of the controller 22, wherein the output current path of current mirror CAC provides the mirrored current, which may be equal to the current in the input path. A current sink Q.sub.1 is connected to the output of the current mirror CAC and configured to sink a constant DC current i.sub.DC. Further, the input path of a second current mirror CM.sub.2 is connected to the output of the first current mirror CM.sub.1. Following Kirchhoff s current law, the current i.sub.o passing through the input path of the second current mirror CM.sub.2 must equal i.sub.DC minus i.sub.CH (i.sub.o=i.sub.DC−i.sub.CH). The input current i.sub.o of current mirror CM.sub.2 is mirrored to the output of the current mirror CM.sub.2.
[0029] An inverter INV.sub.2 is supplied by the output current i.sub.o of the second current mirror CM.sub.2 and accordingly, the current i.sub.o=i.sub.DC−i.sub.CH is the maximum output current of the inverter INV.sub.2 when the inverter output is at a high level. Another inverter INV.sub.1 is connected ahead of the inverter INV.sub.2. Accordingly, the inverter chain INV.sub.1 and INV.sub.2 does not change the logic state of the input signal IN supplied to the inverter INV.sub.1 in a steady state, but the output current of the inverter chain is limited to the current level i.sub.o. A capacitor C.sub.CH is coupled to the output of inverter INV.sub.2. Accordingly, upon with a rising edge in input signal IN the capacitor C.sub.CH is charged with the current i.sub.o. The resulting capacitor voltage V.sub.CH will ramp up until it reaches approximately the supply voltage of the inverter INV.sub.2 (approximately V.sub.BOOT minus the voltage drop in current mirror CM.sub.2).
[0030] The capacitor voltage V.sub.CH (voltage ramp) is compared with a reference voltage V.sub.X by comparator CMP, which is configured to signal (e.g., by a low level at its output) that the capacitor voltage V.sub.CH has exceeded the reference voltage V.sub.X. The comparator output voltage is used to blank the input voltage IN using an AND gate which receives, as input signals, the input signal IN and the comparator output signal. The output signal of the AND gate is denoted as IN′ (see also FIG. 5). The signal IN′ follows the input signal IN before it is blanked by the comparator output signal a time T.sub.CH after the rising edge of the input signal. The time T.sub.CH depends in the current i.sub.o and the capacitance C.sub.CH, wherein the current i.sub.o depends on the controller output current i.sub.CH. If the controller output current i.sub.CH increases, the current i.sub.o will decrease and, consequently, the capacitor C.sub.CH is charged more slowly and the time T.sub.CH increases. The time T.sub.CH is the pulse length of the pulse in signal IN′ triggered by a (rising edge in input signal IN, see FIG. 5). The inverted comparator output signal (inverter INV.sub.3) is provided as output signal SMP that triggers the sampling circuit 21 as explained above. Accordingly, the pulse length T.sub.CH is determined by the controller output current i.sub.CH and thus by the sampled voltage value V.sub.SMP, wherein at the end of the pulse a new value is samples.
[0031] It is noted that FIG. 6 illustrates a concept for charging the gate capacitance in order to switch the power transistor M.sub.D on. The circuitry for discharging the gate capacitance in order to switch the power transistor M.sub.D off is not shown in order to keep the drawings simple. However, known concepts may be used to switch off the power transistor M.sub.D such as, for example, an electronic switch (e.g., another transistor) configured to electrically connect gate and source electrode of the power transistor M.sub.D in response to a falling edge of the input signal IN. Of course, gate and source electrode of power transistor M.sub.D need to be disconnected at or before the next rising edge of the input signal IN in order to allow another switch-on.
[0032] FIG. 8 illustrates one exemplary application of the gate control circuit 100 of FIGS. 6 and 7. In essence, FIG. 8 illustrates a buck converter circuit. The gate control circuit 100 and the high-side power transistor 100 have already explained with reference to FIG. 4. An inductor L is connected between the source terminal of power transistor M.sub.D and an output circuit node, at which the output voltage V.sub.OUT is provided. A capacitor C.sub.OUT is connected between the output node and ground GND. Further, a free-wheeling diode D.sub.F is connected between the source terminal of transistor M.sub.D and ground GND. A low side DMOS transistor may be used instead of the diode D.sub.F. Embodiments of the gate control circuit 100 described herein allow a faster switching and thus a reduction of the inductance and, consequently, a reduction of the inductor size.
[0033] Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, inverted logic levels can be used, and logic operations such as AND, NAND, OR, etc. can generally be replaced by different logic operations using commonly known concepts. In particular regard to the various functions performed by the above described components or structures (units, assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond—unless otherwise indicated—to any component or structure, which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary implementations of the invention.
