METHOD FOR ANALYZING AN ELECTRICAL CIRCUIT

Abstract

A method for analyzing an electrical circuit. The method includes procuring one or multiple netlists(s) of the circuit; supplying the one or multiple netlist(s) to a classification model; and mapping, by the classification model, one or multiple of the connection(s) included in the netlist or netlists onto one or multiple net type(s) from a predefined selection of net types.

Claims

1. A method for analyzing an electrical circuit, comprising the following steps: procuring one or multiple netlists of the circuit; supplying the one or multiple netlists to a classification model; and mapping, by the classification model, one or multiple of connections included in the one or multiple netlists onto one or multiple net types from a predefined selection of net types.

2. The method as recited in claim 1, wherein at least one net type indicates: a function and/or a configuration of a connection in the circuit, and/or an affiliation of the connection with a functional module of the circuit, and/or a provided voltage level of the connection, and/or a use of the connection for analog or digital signal transmission, and/or a speed class of a digital data transmission via the connection, and/or a frequency range of an analog signal transmitted via the connection, and/or a communication standard used on the connection, and/or a categorization of the connection with respect to safety relevance.

3. The method as recited in claim 1, wherein, in addition to at least one connection, a type of a component connected to the at least one connection, and/or a function of a pin of a component to which the connection is connected, is supplied to the classification model.

4. The method as recited in claim 3, wherein the type of the component, and/or the function of the pin, is ascertained from: at least one assembly list of the circuit, and/or at least one component grouping of the circuit, and/or at least one data sheet or one other instruction sheet of a component, and/or at least one analytical result of a further analytical model.

5. The method as recited in claim 1, wherein a layout of the circuit and/or a design of the circuit is checked for conformity using a predefined rule set, taking at least one of the mapped net types into consideration.

6. The method as recited in claim 5, wherein at least one rule of the rule set includes that connections of two predefined net types: must not have any electrical contact with one another, and/or must not cross one another, and/or must extend at a minimum distance with respect to one another, and/or must be insulated from one another by insulation.

7. The method as recited in claim 1, wherein the electrical circuit is divided into netlists in such a way that each netlist of the netlists relates to no more than a predefined number of connected components.

8. A method for troubleshooting an electrical circuit, comprising the following steps: establishing at least one hypothesis for a cause of an error; analyzing the circuit by: procuring one or multiple netlists of the circuit, supplying the one or multiple netlists to a classification model, and mapping, by the classification model, one or multiple of connections included in the one or multiple netlists onto one or multiple net types from a predefined selection of net types; based on the at least one hypothesis, ascertaining a list of net types in such a way that connections belonging to the net types, and/or components connected to the connections, may be causative for the error; ascertaining specific connections in the circuit which belong to the net types included in the list as well as components connected to the specific connections; and checking the ascertained specific connections and components for a presence of errors.

9. The method as recited in claim 8, wherein multiple hypotheses for the cause of the error, and/or the list of the net types, are organized in descending order of likelihoods: (i) with which the respective hypothesis is accurate, or (ii) with which connections of the respective net type or components connected the net type are causative for the error.

10. A non-transitory machine-readable data medium on which is stored a computer program for analyzing an electrical circuit, the computer program, when executed by a computer, causing the computer to perform the following steps: procuring one or multiple netlists of the circuit; supplying the one or multiple netlists to a classification model; and mapping, by the classification model, one or multiple of connections included in the one or multiple netlists onto one or multiple net types from a predefined selection of net types.

11. One or multiple computers configured to analyze an electrical circuit, the one or multiple computers configured to: procure one or multiple netlists of the circuit; supply the one or multiple netlists to a classification model; and map, by the classification model, one or multiple of connections included in the one or multiple netlists onto one or multiple net types from a predefined selection of net types.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG. 1 shows one exemplary embodiment of method 100 for analyzing an electrical circuit 1.

[0051] FIG. 2 shows one exemplary embodiment of method 200 for troubleshooting an electrical circuit 1.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0052] FIG. 1 is a schematic flowchart of one exemplary embodiment of method 100 for analyzing an electrical circuit 1.

[0053] In step 110, one or multiple netlists(s) 11 of circuit 1 is/are procured. In the process, according to block 111, electrical circuit 1 may be divided into netlists 11 in such a way that each netlist 11 relates to no more than a predefined number of connected components 13.

[0054] In step 120, the one or multiple netlist(s) is/are supplied to a classification model. According to block 121, in addition to at least one connection 12, a type of a component 13 connected to this connection 12, and/or a function of the pin of component 13 to which connection 12 is connected, is/are supplied to classification model 2. According to block 121a, the type of the component, and/or the function of the pin, may, in particular, be ascertained, for example, from

[0055] at least one assembly list of circuit 1, and/or

[0056] at least one component grouping of circuit 1, and/or

[0057] at least one data sheet or one other instruction sheet of a component 13, and/or

[0058] at least one analytical result of a further analytical model.

[0059] In step 130, one or multiple of connection(s) 12 included in netlist or netlists 11 is/are mapped by classification model 2 onto one or multiple net type(s) 12a through 12c from a predefined selection of net types 12a through 12c.

[0060] In step 140, the layout and/or the design of circuit 1 is checked for conformity using a predefined rule set 3, taking at least one of the ascertained net types 12a through 12c into consideration. With each rule, the circuit may either be conforming (OK) or non-conforming (NOK). According to block 141, at least one rule of rule set 3 may include that connections 12 of two predefined net types 12a through 12c

[0061] must not have any electrical contact with one another, and/or

[0062] must not cross one another, and/or

[0063] must extend at a minimum distance with respect to one another, and/or

[0064] must be insulated from one another by insulation.

[0065] FIG. 2 is a schematic flowchart of one exemplary embodiment of method 200 for troubleshooting in an electrical circuit 1 which is subject to an initially unknown error F.

[0066] In step 210, at least one hypothesis 4 for the error cause is established.

[0067] According to block 211, multiple hypotheses 4 may be established and may be organized in descending order of the likelihoods with which they accurately describe the error cause.

[0068] In step 220, circuit 1 is analyzed using the above-described method 100.

[0069] In step 230, a list 5 of net types 12a through 12c is ascertained based on the at least one hypothesis 4. These net types 12a through 12c are selected in such a way that connections 12 belonging precisely to these net types 12a through 12c, and/or components 13 connected to these connections 12, may be causative for the sought error F.

[0070] According to block 231, list 5 of net types 12a through 12c may be organized in descending order of the likelihoods with which connections 12 of the respective net type 12a through 12c, or components 13 connected thereto, are causative for the sought error F.

[0071] In step 240, the specific connections 12 in circuit 1 which belong to net types 12a through 12c included in list 5 as well as components 13 connected to these connections 12 are ascertained.

[0072] In step 250, connections 12 and components 13 thus ascertained are at least preferentially checked for the presence of errors. This means that it is also possible to check other connections and components, but the ascertained connections 12 and components 13 are preferred.