OPTOELECTRONIC DEVICE

Abstract

An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.

Claims

1. A silicon-on-insulator chip comprising: a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and a first array of detector remodulators (DRMs), each of the DRMs comprising: a detector; a modulator; and a CMOS circuit connected between the detector and the modulator, the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a modulation waveguide region at which a second semiconductor junction is set horizontally across the modulation waveguide region in that the second semiconductor junction comprises a first doped region of the modulation waveguide region and a second doped region of the modulation waveguide region which is on an opposite side of the modulation waveguide region to the first doped region in a horizontal direction; the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and wherein each DRM is located at an input or output of the AWG, wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.

2. The silicon-on-insulator chip of claim 1, wherein the detectors of the DRMs are located within the plane.

3. The silicon-on-insulator chip of claim 1, wherein a respective DRM of the first array of DRMs is located at each of one or more inputs of the first AWG and at each of one or more outputs of the first AWG.

4. The silicon-on-insulator chip of claim 3, wherein a respective DRM of the first array of DRMs is located at each input of the first AWG and at each output of the first AWG.

5. The silicon-on-insulator chip of claim 3, wherein a signal input waveguide for one or more of the DRMs lies within the plane.

6. The silicon-on-insulator chip of claim 3, wherein a signal input waveguide for one or more of the DRMs impinges the modulator of the DRM from an angle to the plane.

7. A system comprising: the silicon-on-insulator chip of claim 1; and one or more tunable lasers, each tunable laser being for providing a wavelength tuned laser input to the modulator of a respective one or more of the DRMs.

8. The system of claim 7, wherein the one or more tunable lasers are located on the silicon-on-insulator chip.

9. The system of claim 8, wherein the one or more tunable lasers are located within the plane.

10. The system of claim 7, wherein a tunable laser of the one or more tunable lasers is thermally isolated from the first AWG and the DRMs.

11. The system of claim 7, wherein the one or more tunable lasers lies within the plane.

12. The system of claim 7, wherein: a respective DRM of the first array of DRMs; and a respective tunable laser, of the one or more tunable lasers, are located at each input of the first AWG, the tunable laser being configured to provide the wavelength tuned laser input for the modulator of the DRM.

13. The system of claim 7, wherein: a respective DRM of the first array of DRMs; and a respective tunable laser, of the one or more tunable lasers, are located at each output of the first AWG, the tunable laser being configured to provide the wavelength tuned laser input for the modulator of the DRM.

14. The silicon-on-insulator chip of claim 1, wherein: the first AWG has a plurality of inputs and a plurality of outputs; each of the first array of DRMs being located at a respective input of the first AWG, each DRM of the first array of DRMs being configured to receive a wavelength tunable laser input; the first array of DRMs being arranged such that an output of each DRM of the first array of DRMs is configured to form an input signal for the first AWG; the silicon-on-insulator chip further comprising: a second AWG having a plurality of inputs and a plurality of outputs; and a second array of DRMs, each located at a respective input to the second AWG; each DRM of the second array of DRMs being configured to receive a wavelength tunable laser input; the second array of DRMs being arranged such that an output of each DRM of the second array of DRMs is configured to form an input signal for the second AWG; wherein each output of the first AWG is configured to form an input signal for a respective DRM of the second array of DRMs, and wherein: the DRMs of the first array of DRMs, the second AWG, and the DRMs of the second array of DRMs are in the plane.

15. The silicon-on-insulator chip of claim 14, wherein the first and second AWGs are located in an end-to-end arrangement on the silicon-on-insulator chip.

16. The silicon-on-insulator chip of claim 15, wherein the first and second AWGs are positioned in a nested arrangement within the plane.

17. The silicon-on-insulator chip of claim 1, wherein: each DRM of the first array of DRMs is located at an input waveguide of the first AWG, and each DRM of the first array of DRMs is coupled to a tunable laser which is configured to provide a wavelength tuned input for the modulator of the DRM; the silicon-on-insulator chip further comprising: a second array of DRMs; each DRM of the second array of DRMs being located at an output waveguide of the first AWG and each DRM of the second array of DRMs being coupled to a tunable laser which is configured to provide a wavelength tuned input for the modulator of the DRM; an optical demultiplexer, an output of which is configured to form input signals for the first array of DRMs; and an optical multiplexer, the inputs for which are the outputs of the second array of DRMs.

18. A silicon-on-insulator chip comprising: a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and a first array of detector remodulators (DRMs), each of the DRMs comprising: a detector; a modulator; and a CMOS circuit connected between the detector and the modulator, the CMOS circuit having: a first external contact connected to the detector and not connected to the modulator, and a second external contact connected to the modulator and not connected to the detector, the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a second semiconductor junction arranged in the plane; the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and wherein each DRM is located at an input or output of the AWG, wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.

19. A silicon-on-insulator chip comprising: a first arrayed waveguide grating (AWG) comprising a plurality of waveguides in a plane, one or more inputs, and one or more outputs; and a first array of detector remodulators (DRMs), each of the DRMs comprising: a detector; a modulator; and a CMOS circuit connected between the detector and the modulator, the detector being configured to convert an input modulated optical signal to an electrical signal and comprising a first semiconductor junction arranged in the plane and the modulator being configured to modulate an output optical signal using the electrical signal and comprising a second semiconductor junction arranged in the plane; wherein an output of the detector is connected to an input of the CMOS circuit and an output of the CMOS circuit is connected to an input of the modulator; the first array of DRMs being in a planar arrangement with the first AWG such that the modulators of the DRMs are located within the plane; and wherein each DRM is located at an input or output of the AWG, wherein an input waveguide for the input modulated optical signal for one or more of the DRMs lies within the plane.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

[0057] FIG. 1 shows a plan view of an optoelectronic device;

[0058] FIG. 2A shows a cross-sectional view of the device of FIG. 1 along the line A-A;

[0059] FIG. 2B shows a cross-sectional view of the device of FIG. 1 along the line B-B;

[0060] FIGS. 3A-3P show various manufacturing steps;

[0061] FIG. 4 shows a variant device;

[0062] FIG. 5 shows a variant device;

[0063] FIG. 6 shows a variant device;

[0064] FIG. 7 shows a variant device; and

[0065] FIGS. 8-14 show variant structures for the optically active region and/or device.

DETAILED DESCRIPTION

[0066] FIG. 1 is a plan view of an optoelectronic device 104 as disposed on a chip 100. An input waveguide 101 is operable to guide a light signal along direction 102 and through an interface 103 into the device. The interface between the input waveguide and the device is at an angle .sub.1 relative to the guiding direction 102 of the light. The angle .sub.1 may take a value between 0 and 10. In some embodiments .sub.1 is approximately 8.

[0067] The light signal, having passed through the interface into the device 104, enters an optically active region (OAR) 105 where it may be processed or modified. For example, the optically active region may be any of: a photodiode; an electro-absorption modulator; or an avalanche photodiode. Depending on the nature of the optically active region, the light signal may then exit the OAR and device 104 via interface 108, into an output waveguide 106.

[0068] The output waveguide 106 guides light in direction 107, and the interface 108 may be at an angle .sub.2 relative to the guiding direction 107 of the light in the output waveguide. As with angle .sub.1, the angle .sub.2 may take a value between 0 and 10. In some embodiments .sub.2 is approximately 8, and is generally equal to .sub.1.

[0069] FIG. 2A is a cross-sectional view of the device 104 shown in FIG. 1, along the line A-A. The device 104 comprises a silicon substrate 201 which is a lowermost layer of the device. Disposed on top of the substrate are two buried oxide (BOX) layers 202a and 202b; and, between the buried oxide layers, is a cladding layer 203 which may be Si or SiGe. On top of the cladding layer is an optically active region 105 which is connected on either side to the input waveguide 101 and output waveguide 106. The interfaces 103 and 108 between the waveguides and the OAR are shown. A capping SiO.sub.2 layer 206 is shown in this figure. Notably, the buried oxide layers 202a and 202b do not extend under the optically active region 105. The buried oxide layers may extend partially under a slab of the rib waveguide, i.e. under doped regions 210 and 211.

[0070] FIG. 2B is across-sectional view of the device 104 shown in FIG. 1, along the line B-B. This figure shows in more detail an example of the optically active region 105. Disposed on top of the cladding layer is a waveguide that comprises an intrinsic part 205, a first doped region 208 and a second doped region 209 which are formed from the same material as the intrinsic part 205. Alternatively, either doped regions 208 or 209, or both doped regions 208 and 209, may be formed from a different material from the intrinsic part 205 such as Si or SiGe. The doped regions 208 and 209 extend along an upper surface of the cladding layer 203, and up sidewalls of the intrinsic part 205. The dopants in the first doped region are of a different species to the dopants in the second doped region.

[0071] A first portion 210 of the first doped region 208 is heavily doped in comparison to the remaining first doped region. This portion 210 is connected to an electrode 232a, which extends through the SiO.sub.2 capping layer 206. Similarly, a second portion 211 of the second doped region 209 is heavily doped in comparison to the remaining second doped region. This portion 211 is connected to a second electrode 232b, which extends through the capping layer 206. The OAR 105 is generally located in a cavity of a silicon layer, the cavity being partially defined by silicon sidewalls 207a and 207b. The intrinsic part 205 in this example is undoped, and so the OAR can be described as a p-i-n junction. As the intrinsic part 205 extends away from the cladding layer, it may be described as a proud or rib waveguide where the rib is provided by the intrinsic part 205 and a part of first 208 and second 209 doped regions which extend up the side of the intrinsic part 205 and the slab is provided by a part of the doped regions 208 and 209 which extends along the upper surface of the cladding layer 203. The rib waveguide may have a height of around 2.8 m as measured from the upper surface of the cladding layer, and the slabs may have a height of around 200 nm. The width of the rib waveguide (i.e. the horizontal distance between the parts of the first and second doped regions which extend up the side of the intrinsic part 205) may be around 0.8 m. The cladding layer may be approximately 400 nm thick (i.e. as measured from the uppermost surface of the silicon substrate to the uppermost surface of the cladding layer). In such examples, the coupling efficiency from the input waveguide into the waveguide 205 has been computed as approximately 99% for TE mode and 98.7% for TM mode.

[0072] The cladding layer 203 functions to confine light signals entering the OAR into the rib waveguide. It does so primarily by being formed of a material having a refractive index which is less than that of the OAR. For example, the cladding layer may be formed of a silicon layer which may be epitaxially grown or deposited using chemical vapour deposition which can have a refractive index of 3.3 to 3.8. In. In contrast, the waveguide and/or OAR may be formed primarily of silicon germanium (SiGe) which can have a refractive index of 4.0-4.7. This change in refractive index across the interface between the OAR and cladding layer may provide enough index contrast (i.e. n) to confine the light signals to the waveguide. It is notable that good confinement can be achieved without a buried oxide layer below the OAR, as discussed above.

[0073] FIG. 3A-3P discuss manufacturing steps to provide a device as shown in FIGS. 2 and 3, shown along the cross-section B-B. In a first step, shown in FIG. 3A, a silicon-on-insulator wafer is provided. The wafer comprises a silicon substrate 201, a buried oxide layer 202 disposed thereon, and a silicon-on-insulator layer 207. Next, as illustrated in FIG. 3B, a first mask 212 is disposed over a region of the silicon-on-insulator layer and then the unmasked region is etched down to the buried oxide layer 202. This results in a cavity 213 in the silicon-on-insulator layer which is partially defined by sidewalls 207a and 207b. Next, the buried oxide layer in between the sidewalls 207 and 207b is etched away and the first mask is removed, resulting in a structure shown in FIG. 3C. The cavity is now at least partially defined by sidewalls of the silicon-on-insulator layer 207a and 207b as well as sidewalls 202a and 202b of the remaining buried oxide layer.

[0074] Next, as illustrated in FIG. 3D, an insulating liner 215a and 215b may be provided along the sidewalls 207a and 207b of the cavity 213. Indeed, in some embodiments there is no liner provided along the sidewalls of the cavity. The liner may extend along the top of the sidewalls 207a and 207b as illustrated. After the liner has been provided, a cladding layer 203 is grown onto the silicon substrate 201 as shown in FIG. 3E. The cladding layer may be an epitaxially grown semiconductor (for example silicon) layer, and may be referred to as an epitaxial crystalline layer. The liner may ensure that the cladding layer grows with a generally homogenous crystal structure, as it may only grow from the silicon substrate and not from the sidewalls. As an optional extra step after regrowing the cladding layer, the insulating liner 215a and 215b, which may have been provided along the sidewalls 207a and 207b of the cavity 213, may be removed.

[0075] After the cladding layer has been provided, the optically active region 217 is grown as shown in FIG. 3F. Prior to this step, a seed layer may be grown on top of the cladding layer. This can benefit the formation of the optically active region. The optically active region may be provided by the blanket deposition of germanium into the cavity 213. After deposition, the optically active region 217 is planarized by, for example, chemical-mechanical polishing such that an uppermost surface of the OAR is level with an uppermost surface of the liner 215a and 215b, as shown in FIG. 3G. If there is no liner, then the uppermost surface of the OAR would be level with the uppermost surface of the sidewalls 207a and 207b.

[0076] Next, as shown in FIG. 3H, a second mask 218 is provided over a portion of the OAR, and the unmasked region is etched to provide slabs 220a and 220b of the waveguide. The unetched region provides a rib waveguide 219 as discussed above. This completes the key manufacturing steps for providing the optically active region.

[0077] As a further step, shown in FIG. 3I, a capping layer 221 is provided over the OAR. This capping layer is sufficiently thin that dopants can be implanted into regions of the OAR through the capping layer. For example, as shown in FIG. 3J, a third mask or photoresist 222 is provided a region of the device. The unmasked region is then exposed to dopants 223 of a first species, so as to dope a region 208 of the optically active region. In this example, the dopants are injected into a region of the slab 220a which is unmasked as well as a sidewall of the rib of the waveguide. The dopants may be, for example, boron and so the region is doped with a p type species of dopant. The third mask is then removed.

[0078] Similarly, as shown in FIG. 3K, a fourth mask or photoresist 224 is provided over a region of the device. The unmasked region is then exposed to dopants 225 of a second species, so as to dope a region 209 of the optically active region. In this example, dopants are injected into a region of the slab 220b which is unmasked as well as a sidewall of the rib waveguide. The dopants may be, for example, phosphorus and so the region is doped with an n type species of dopant. The fourth mask is then removed.

[0079] So as to decrease the electrical resistance of the first 208 and second 209 doped regions, further doping may be performed as will be discussed. In FIG. 3L, a fifth mask or photoresist 226 is disposed over a region of the device, and an unmasked region is exposed to further dopants 227 of the first species. This results in a first heavily doped region 210 within the first doped region 208. This region may be described as p++ doped relative to the p doped region 208. The fifth mask is then removed. Similarly, as shown in FIG. 3M, a sixth mask or photoresist 228 is provided over a region of the device, and an unmasked region is exposed to further dopants 229 of the second species. This results in a second heavily doped region 211 within the second doped region 209. This region may be described as n++ doped relative to the n doped region 209. The sixth mask is then removed.

[0080] As a further step shown in FIG. 30, a seventh mask 230 may be provided over a region of the device, and the unmasked regions may be etched so as to remove portions of the capping layer 221 above the first 210 and second 211 heavily doped regions. This produces vias 231a and 231b. The seventh mask is then removed. In a final step, shown in FIG. 3P, electrodes 232a and 232b are provided which respectively contact the first 210 and second 211 heavily doped regions through the vias. An electric potential can be applied via electrodes 232a and 232b, resulting an electric field which passes horizontally across the waveguide 219. The device may therefore utilize the Franz-Keldysh effect to modulate the amplitude of light signals passing through.

[0081] A variant device is shown in FIG. 4, where a germanium seed layer 401 is disposed between the cladding layer 416 and the silicon substrate 201. As is also shown in this figure, the seed layer 401 is positioned within a cavity of the silicon substrate 20, such that the cladding layer 416 is disposed in a similar position to previous embodiments. Like features are indicated by like numerals. As will be appreciated, the additional features shown in FIG. 2B may also be present in this device, but for the sake of clarity are not shown.

[0082] Similarly, a further variant device is shown in FIG. 5. Here, the first doped region 501 extends only part of the way up the sidewall of the waveguide 219. As will be appreciated, the additional features shown in FIG. 2B may also be present in this device, but for the sake of clarity are not shown. This device is suitable for providing a bias across the junction to enable control of the phase of light traveling through the junction region via dispersion. The structure of the device and its method of manufacture are similar to that disclosed in WO 2016/0139484 titled Waveguide Modulator Structures, the entire contents of which is incorporated herein by reference.

[0083] Another variant device is shown in FIG. 6. Here, a further silicon layer 601 is doped to provide a first doped region 602 and a second doped region 604. Alternatively, the further silicon layer 601 is not used and the first doped region 602 is made in the cladding layer 203. They respectively include a first heavily doped region 603 and a second heavily doped region 605. In contrast to the previous devices, the first doped region 602 does not extend up a sidewall of the waveguide 219, but instead extends along a lowermost surface of the waveguide 219. Further, the second doped region 604 extends along an uppermost surface of the waveguide 219. Therefore, when a voltage is applied to electrodes 232a and 232b, a vertical electric field can therefore be provided across the waveguide 219 in contrast to the horizontal electric field in previous examples. The structure of the device and its method of manufacture are similar to that disclosed in WO 2017/081196 A1 titled An optoelectronic component, the enter contents of which is incorporated herein by reference.

[0084] A further variant device is shown in FIG. 7. In this Figure, a device is shown comprising a ridge modulation region with a height h.sub.wg; the ridge modulation region being made up of a base 701 manufactured from a first waveguide material M.sub.1 and a ridge 702 manufactured from a second waveguide material M.sub.2 which is different from the first waveguide material.

[0085] The base 701 includes a first slab region extending away from a first sidewall of the waveguide ridge in a first direction, and a second slab region extending away from a second sidewall of the waveguide ridge in a second direction; the second direction being opposite the first direction.

[0086] The device includes a first doped region, the first doped region including a first doped slab region 713a and a first doped sidewall region extending along the first sidewall of the waveguide.

[0087] As shown in the Figure, the ridge of the waveguide is formed from a lower ridge portion 712a and an upper ridge portion 712b. The lower ridge portion is in contact with and extends away from the base; the base and lower ridge portion both being formed from the first material M.sub.1. The upper ridge portion is made from the second material M.sub.2 located on top of the lower ridge portion in that it is in contact with and extends away from the lower ridge portion.

[0088] The first doped sidewall region extends along the entire sidewall of the ridge including both the lower ridge portion 712a and the upper ridge portion 712b. The first doped sidewall region therefore comprises a first lower sidewall portion 713b which extends along the first sidewall at the lower ridge portion of the ridge; and a first upper sidewall portion 713c which extends along the sidewall at the upper ridge portion of the ridge.

[0089] Similarly, at the second side of the rib waveguide, the device comprises a second doped slab region 714a and a second doped sidewall region extending along the second sidewall of the waveguide. The second doped sidewall is made up of a second lower sidewall portion 714b which extends along the second sidewall at the lower ridge portion of the ridge; and a second upper sidewall portion 713c which extends along the sidewall at the upper ridge portion of the ridge.

[0090] The dopant concentration at the doped slab regions and the lower doped sidewall regions are higher than those of the upper doped sidewall regions. In the example shown, the first doped slab region and the first lower sidewall doped region are n++ doped, whilst the first upper sidewall is n doped; the n++ doped region typically contains at least one to two orders of magnitude more dopant per cm.sup.3 as compared to the n doped region. The second doped slab region and second lower sidewall doped region are p++ doped whilst the first upper sidewall is p doped.

[0091] In the example shown, the first material M.sub.1 is formed from silicon (Si) and the second material M.sub.2 is formed of silicon germanium (SiGe) or silicon germanium tin (SiGeSn). However, it is envisaged that the structure of this embodiment could equally be applied to other suitable optical materials. Examples of suitable dopant concentrations for an M.sub.1/M.sub.2 structure of Si/SiGe or Si/SiGeSn are shown in Table 1 below:

TABLE-US-00001 TABLE 1 Doping range Doping type [1/cm.sup.3] n 1e15-1e18 p 1e15-1e18 n++ 1e18-1e20 p++ 1e18-1e20

[0092] As can be seen in FIG. 7, the first doped slab region can be defined by a thickness d.sub.np1 by which it extends downwards into the slabs of the first material M.sub.1. The first lower sidewall portion 713b and second lower sidewall portion 714b each extend upwardly away from the slab by a height h.sub.3 which corresponds to the height of the lower portion of the ridge. These lower sidewall portions 713b, 714b extend into the ridge by respective distances d.sub.np2, d.sub.pp2, each of these respective distances being less than half the total cross-sectional width of the lower ridge portion, such that an undoped region separates the n++ region from the p++ region thereby forming a p-i-n junction.

[0093] An electrical contact (not shown) will be located at each of the slab regions in order to apply a bias across the junction which is formed by the doped regions. These electrical contacts will be located directly onto the slab (i.e. at the upper surface of the lab, on either side of the ridge). Typically the contacts may be equidistant from the respective sidewalls of the ridge.

[0094] The first and second upper sidewall portions 713c, 714c extend into the upper ridge portion of the ridge by a distance d.sub.m d.sub.p respectively, each of which is less than the respective distance d.sub.np2, d.sub.pp2, by which the lower sidewall portions 713b, 714b each extend into the lower portion 712a of the rib waveguide. Examples of typical measurements are given (in nm) in Table 2:

TABLE-US-00002 TABLE 2 Geometry Tolerance h.sub.1 [nm] 100-800 h.sub.2 [nm] 100-400 h.sub.3 [nm] 0-400 d.sub.np1, d.sub.np2 [nm] 50-300 d.sub.pp1, d.sub.pp2 [nm] 50-300 d.sub.p [nm] 50-300 d.sub.n [nm] 50-300

[0095] In this example, the waveguide device takes the form of a waveguide electro-absorption modulator (EAM). However, it is possible that the device could instead take the form of another optoelectronic component such as a waveguide photodiode (PD).

[0096] The structure of the device and its method of manufacture are similar to that disclosed in U.S. 62/429,701, the entire contents of which is incorporated herein by reference.

[0097] FIG. 8 shows an optically active region which is similar to that shown in FIG. 7. However, the region indicated within dotted line 801 which includes the first doped slab portion 713a, the first lower sidewall portion 713b, and the first upper sidewall portion 713c is formed of crystalline or amorphous silicon. Whilst not shown, it is possible that there is a buried oxide layer beneath the base 701 but this is optional.

[0098] FIG. 9 is similar to FIG. 8, except that the region indicated within dotted line 901 now includes the second doped slab portion 714a, the second lower sidewall portion 714b, and the second upper sidewall portion 714c and so these regions are also formed of crystalline or amorphous silicon. Whilst not shown, it is possible that there is a buried oxide layer beneath the base 701 but this is optional.

[0099] FIG. 10 shows a variant optically active region to those previously.

[0100] Here, the entire slab, as well as a portion of the ridge 713b 714b, is within the region indicated within dotted line 1001. This region is formed of crystalline or amorphous silicon. This device is shown with an optionally buried oxide layer 1002 below the region 1001. This is also true of the devices shown in FIGS. 7, 8, 9, 11, and 12.

[0101] FIG. 11 shows an optically active region which is similar to that shown in FIG. 10. However here the dotted region 1101 extends up one side of the rib waveguide and so includes the first upper sidewall portion 713c and so this is also formed of crystalline or amorphous silicon. FIG. 12 is an extension of this, where the second upper sidewall portion 714c is also included and so this is also formed of crystalline or amorphous silicon.

[0102] FIG. 13 shows a further alternative example of the optoelectronic device. Here, as with previous embodiments, a slab 1301 and rib 1302 form a ridge waveguide disposed above a silicon substrate 201. However, in contrast to previous examples, the cladding layer 203 is not as wide as the slab 1301. Instead, first and second portions of a buried oxide layer 202a and 202b are disposed underneath the slab 1301.

[0103] FIG. 14 shows a further alternative example of the optoelectronic device. Generally, this example is similar to any previous example discussed (and so may have, where appropriate, any of the features disclosed with reference thereto). A difference however, shown in FIG. 14, is that this device is provided on a double silicon-on-insulator wafer. Therefore the cladding layer 1401, which confines an optical mode of the device to the optically active region 219, is above a substrate 1402 (which is generally formed of silicon). That substrate 1402 is above a buried oxide layer 1403, for example SiO.sub.2, which is in turn above a second substrate 1404. The manufacturing steps described above apply equally here, where etching is performed at least to a buried oxide layer no longer shown in FIG. 14 but which would have been above substrate 1402.

[0104] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

[0105] All references referred to above are hereby incorporated by reference.

LIST OF FEATURES

[0106] 100 Chip [0107] 101 Input waveguide [0108] 102,107 Light guiding direction [0109] 103 Input waveguide/OAR interface [0110] 104 Optoelectronic device [0111] 105, 205 OAR [0112] 106 Output waveguide [0113] 108 OAR/Output waveguide interface [0114] 201 Silicon substrate [0115] 202a, 202b Buried oxide [0116] 203, 416 Cladding layer [0117] 206 Capping layer [0118] 207a, 207b Silicon-on-insulator layer [0119] 208 First doped region [0120] 209 Second doped region [0121] 210 First heavily doped region [0122] 211 Second heavily doped region [0123] 212 First mask [0124] 213 Cavity [0125] 214 Upper surface of substrate [0126] 215a, 215b Insulating liner [0127] 217 Grown optically active region [0128] 218 Second mask [0129] 219 Ridge of rib waveguide [0130] 220a, 220b Slabs of rib waveguide [0131] 221 Capping layer [0132] 222 Third mask [0133] 223 First dopant implantation [0134] 224 Fourth mask [0135] 225 Second dopant implantation [0136] 226 Fifth mask [0137] 227 Third dopant implantation [0138] 228 Sixth mask [0139] 229 Fourth dopant implantation [0140] 230 Seventh mask [0141] 231a, 231b Via opening [0142] 232a, 232b Electrodes [0143] 401 Seed layer