ENVELOPE TRACKING VOLTAGE CORRECTION IN A TRANSMISSION CIRCUIT

Abstract

Envelope tracking (ET) voltage correction in a transmission circuit is provided. The transmission circuit includes a transceiver circuit and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and the power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit. Herein, the transceiver circuit is configured to apply a complex filter(s) to the time-variant modulation vector and/or the RF signal(s) to compensate for a voltage distortion filter created across a modulation bandwidth of the RF signal(s) by coupling the power amplifier circuit with the RF front-end circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter to thereby improve efficiency and linearity of the power amplifier circuit(s) across the modulation bandwidth of the RF signal(s).

Claims

1. A transmission circuit comprising: a power amplifier circuit coupled to a transmitter circuit via a radio frequency (RF) front-end circuit and configured to amplify an RF signal based on a modulated voltage and provide the amplified RF signal to the RF front-end circuit; an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage based on a modulated target voltage; and a transceiver circuit configured to: generate the RF signal from a time-variant modulation vector; generate the modulated target voltage as a function of the time-variant modulation vector; and apply at least one complex filter to at least one of the time-variant modulation vector and the RF signal to compensate for a voltage distortion filter created on an output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit across a modulation bandwidth.

2. The transmission circuit of claim 1, wherein the at least one complex filter comprises an equalization filter and a digital frequency equalization filter.

3. The transmission circuit of claim 2, wherein the transceiver circuit comprises: a signal processing circuit configured to generate the RF signal from the time-variant modulation vector; a target voltage circuit comprising: an ET lookup table (LUT) circuit configured according to a selected frequency of the RF signal to generate the modulated target voltage; and an equalizer circuit configured to apply the equalization filter to the time-variant modulation vector to generate a filtered time-variant modulation vector; and a digital frequency equalizer configured to apply the digital frequency equalization filter to the time-variant modulation vector to generate an equalized time-variant modulation vector.

4. The transmission circuit of claim 3, wherein the target voltage circuit further comprises a vector-to-real (V2R) converter coupled to the equalizer circuit and configured to extract a selected real parameter from the filtered time-variant modulation vector.

5. The transmission circuit of claim 4, wherein the target voltage circuit further comprises a scaler coupled to the V2R converter and configured to scale the selected real parameter based on a scaling factor that is adapted according to an average power of the RF signal.

6. The transmission circuit of claim 4, wherein the target voltage circuit further comprises a unit converter configured to convert the selected real parameter to a predefined parameter configured in the ET LUT circuit for generating the modulated target voltage.

7. The transmission circuit of claim 3, wherein the equalization filter is expressed as: H.sub.EQ(s)=1/H.sub.RF(s), wherein: H.sub.EQ(s) represents the equalization filter; and H.sub.RF(s) represents a transfer function of the RF front-end circuit.

8. The transmission circuit of claim 3, wherein the digital frequency equalization filter is expressed as H.sub.F(s)=[1/H.sub.ET(s)]*[1/H.sub.RF(s)], wherein: H.sub.F(s) represents the digital frequency equalization filter; H.sub.ET(s) represents a combined complex filter configured to match a combined signal path filter, the combined complex filter is expressed as: H.sub.ET(s)=H.sub.IQ (s)*H.sub.PA(s)*H.sub.IV (s), wherein: H.sub.IQ (s) represents a transfer function of the signal processing circuit; H.sub.PA(s) represents a voltage gain transfer function of the power amplifier circuit; and H.sub.IV (s) represents the voltage distortion filter created on the output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit; and H.sub.RF(s) represents a transfer function of the RF front-end circuit.

9. The transmission circuit of claim 3, wherein the signal processing circuit comprises: a memory digital predistortion (mDPD) circuit configured to digitally pre-distort the equalized time-variant modulation vector to generate a pre-distorted time-variant modulation vector; and a modulator circuit configured to generate the RF signal from the pre-distorted time-variant modulation vector and provide the RF signal to the power amplifier circuit.

10. The transmission circuit of claim 1, wherein the at least one complex filter comprises an equalization filter, a digital frequency equalization filter, and an analog frequency equalization filter.

11. The transmission circuit of claim 10, wherein the transceiver circuit comprises: a digital frequency equalizer configured to apply the digital frequency equalization filter to the time-variant modulation vector to generate an equalized time-variant modulation vector; a target voltage circuit comprising: an ET lookup table (LUT) circuit configured according to a selected frequency of the RF signal to generate the modulated target voltage; and an equalizer circuit configured to apply the equalization filter to the equalized time-variant modulation vector to generate a filtered time-variant modulation vector; a signal processing circuit configured to generate the RF signal from the equalized time-variant modulation vector; and an analog frequency equalizer configured to apply the analog frequency equalization filter to the RF signal.

12. The transmission circuit of claim 11, wherein the equalization filter is expressed as: H.sub.EQ(s)=1, wherein H.sub.EQ(s) represents the equalization filter.

13. The transmission circuit of claim 11, wherein the target voltage circuit further comprises a vector-to-real (V2R) converter coupled to the equalizer circuit and configured to extract a selected real parameter from the filtered time-variant modulation vector.

14. The transmission circuit of claim 13, wherein the target voltage circuit further comprises a scaler coupled to the V2R converter and configured to scale the selected real parameter based on a scaling factor that is adapted according to an average power of the RF signal.

15. The transmission circuit of claim 13, wherein the target voltage circuit further comprises a unit converter configured to convert the selected real parameter to a predefined parameter configured in the ET LUT circuit for generating the modulated target voltage.

16. The transmission circuit of claim 11, wherein: the digital frequency equalization filter is expressed as H.sub.F1(s)=1/H.sub.RF(s), wherein: H.sub.F1(s) represents the digital frequency equalization filter; and H.sub.RF(s) represents a transfer function of the RF front-end circuit; and the analog frequency equalization filter is expressed as H.sub.F2(s)=1/H.sub.ET(s), wherein: H.sub.F2(s) represents the analog frequency equalization filter; and H.sub.ET(s) represents a combined complex filter configured to match a combined signal path filter, the combined complex filter is expressed as: H.sub.ET(s)=H.sub.IQ (s)*H.sub.PA(s)*H.sub.IV (s), wherein: H.sub.IQ (s) represents a transfer function of the signal processing circuit; H.sub.PA(s) represents a voltage gain transfer function of the power amplifier circuit; and H.sub.IV (s) represents the voltage distortion filter created on the output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit.

17. The transmission circuit of claim 11, wherein the signal processing circuit comprises: a memory digital predistortion (mDPD) circuit configured to digitally pre-distort the equalized time-variant modulation vector to generate a pre-distorted time-variant modulation vector; and a modulator circuit configured to generate the RF signal from the pre-distorted time-variant modulation vector and provide the RF signal to the power amplifier circuit.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0010] FIG. 1A is a schematic diagram of an exemplary existing transmission circuit, wherein an unwanted voltage distortion filter may be created on a power amplifier circuit when the power amplifier circuit is coupled to a radio frequency (RF) front-end circuit;

[0011] FIG. 1B is a schematic diagram providing an exemplary illustration of an output stage of the power amplifier circuit in FIG. 1A;

[0012] FIG. 2 is a schematic diagram of an exemplary equivalent model providing an exemplary illustration of the unwanted voltage distortion filter created by a coupling between the power amplifier circuit and the RF front-end circuit 14 in FIG. 1A;

[0013] FIG. 3 is a schematic diagram of an exemplary transmission circuit configured according to an embodiment of the present disclosure to compensate for the unwanted voltage distortion filter in the existing transmission circuit of FIG. 1A;

[0014] FIG. 4 is a schematic diagram of an exemplary transmission circuit configured according to another embodiment of the present disclosure to compensate for the unwanted voltage distortion filter in the existing transmission circuit of FIG. 1A; and

[0015] FIG. 5 is a graphic diagram providing an exemplary illustration of a modulation bandwidth in which the transmission circuits of FIGS. 3 and 4 can be configured to compensate for the unwanted voltage distortion filter in the existing transmission circuit of FIG. 1A.

DETAILED DESCRIPTION

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0019] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Embodiments of the disclosure relate to envelope tracking (ET) voltage correction in a transmission circuit. The transmission circuit includes a transceiver circuit and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and provides the RF signal(s) to the power amplifier circuit(s). The power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit (e.g., filter/multiplexer circuit). Notably, when the power amplifier circuit(s) is coupled to the RF front-end circuit, an output reflection coefficient (e.g., S.sub.22) of the power amplifier circuit(s) can interact with an input reflection coefficient (e.g., S.sub.11) of the RF front-end circuit to create a voltage distortion filter on an output stage of the power amplifier circuit(s), which can cause unwanted distortion in the modulated voltage across a modulation bandwidth of the RF signal(s). In this regard, in embodiments disclosed herein, the transceiver circuit is configured to apply at least one complex filter to apply a complex filter(s) to the time-variant modulation vector and/or the RF signal(s) to compensate for a voltage distortion filter created across the modulation bandwidth of the RF signal(s) by coupling the power amplifier circuit with the RF front-end circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulted from the voltage distortion filter to thereby improve efficiency and linearity of the power amplifier circuit(s) across the modulation bandwidth of the RF signal(s).

[0023] Before discussing the transmission circuit according to the present disclosure, starting at FIG. 2, a brief discussion of an existing transmission circuit is first provided to help understand how an unwanted voltage distortion filter may be created when a power amplifier circuit is coupled to an RF front-end circuit, such as a filter/multiplexer circuit.

[0024] FIG. 1A is a schematic diagram of an exemplary existing transmission circuit 10, wherein an unwanted voltage distortion filter H.sub.IV (s) may be created on a power amplifier circuit 12 when the power amplifier circuit 12 is coupled to an RF front-end circuit 14. Notably, in the unwanted voltage distortion filter H.sub.IV (s), “s” is a notation of Laplace transform. The existing transmission circuit 10 includes a transceiver circuit 16, an envelope tracking (ET) integrated circuit (ETIC) 18, and a transmitter circuit 20, which can include an antenna(s) (not shown) as an example.

[0025] The transceiver circuit 16 is configured to generate an RF signal 22 associated with a time-variant voltage envelope 24 and provides the RF signal 22 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-variant target voltage V.sub.TGT, which is associated with a time-variant target voltage 26 that tracks the time-variant voltage envelope 24 of the RF signal 22. The ETIC 18 is configured to generate a modulated voltage V.sub.CC having a time-variant modulated voltage 28 that tracks the time-variant target voltage 26 of the time-variant target voltage V.sub.TGT and provide the modulated voltage V.sub.CC to the power amplifier circuit 12. The power amplifier circuit 12 is configured to amplify the RF signal 22 based on the modulated voltage V.sub.CC to a time-variant output voltage V.sub.OUT associated with a time-variant output voltage envelope 30. The power amplifier circuit 12 then provides the amplified RF signal 22 to the RF front-end circuit 14. The RF front-end circuit 14 may be a filter circuit that performs further frequency filtering on the amplified RF signal 22 before providing the amplified RF signal 22 to the transmitter circuit 20 for transmission.

[0026] FIG. 1B is a schematic diagram providing an exemplary illustration of an output stage 32 of the power amplifier circuit 12 in FIG. 1A. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.

[0027] The output stage 32 can include at least one transistor 34, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor 34 can include a base electrode B, a collector electrode C, and an emitter electrode E. The base electrode B is configured to receive a bias voltage V.sub.BIAS and the collector electrode C is configured to receive the modulated voltage V.sub.CC. The collector electrode C is also coupled to the RF front-end circuit 14 and configured to output the amplified RF signal 22 at the output voltage V.sub.OUT. In this regard, the output voltage V.sub.OUT can be a function of the modulated voltage V.sub.CC. Understandably, the power amplifier circuit 12 will operate with good efficiency and linearity when the time-variant modulated voltage 28 is aligned with the time-variant output voltage envelope 30.

[0028] FIG. 2 is a schematic diagram of an exemplary equivalent model 36 providing an exemplary illustration of the voltage distortion filter H.sub.IV (s) created by a coupling between the power amplifier circuit 12 and the RF front-end circuit 14 in the existing transmission circuit 10 of FIG. 1A. Elements in FIGS. 1A and 1B are referenced in FIG. 2 without being re-described herein.

[0029] In the equivalent model 36, V.sub.PA and Z.sub.PA represent the output stage 32 of the power amplifier circuit 12 and an inherent impedance of the power amplifier circuit 12, respectively, and Z.sub.11 represents an inherent impedance associated with an input port of the RF front-end circuit 14. Herein, V.sub.OUT represents an output voltage associated with the RF signal 22 before the power amplifier circuit 12 is coupled to the RF front-end circuit 14, and V′.sub.OUT represents an output voltage associated with the RF signal 22 after the power amplifier circuit 12 is coupled to the RF front-end circuit 14. Hereinafter, the output voltages V.sub.OUT and V′.sub.OUT are referred to as “non-coupled output voltage” and “coupled output voltage,” respectively, for distinction.

[0030] A Laplace transform representative of the coupled output voltage V′.sub.OUT can be expressed in equation (Eq. 1) below.

[00001]$\begin{array}{cc}{V}_{\mathrm{OUT}}^{\prime }\left(s\right)=\frac{{{V_{\mathrm{OUT}}\left(s\right)}^{*}\left[1-T_{\mathrm{PA}}\left(s\right)\right]}^{*}\left[1+T_I\left(s\right)\right]}{2^{*}\left[1-{T_{\mathrm{PA}}\left(s\right)}^{*}{T}_I\left(s\right)\right]}={V_{\mathrm{OUT}}\left(s\right)}^{\star }{H}_{\mathrm{IV}}\left(s\right)& \left(\mathrm{Eq}.1\right)\end{array}$$H_{\mathrm{IV}}\left(s\right)=\frac{{\left[1-T_{\mathrm{PA}}\left(s\right)\right]}^{*}\left[1+T_I\left(s\right)\right]}{2^{*}\left[1-{T_{\mathrm{PA}}\left(s\right)}^{*}{T}_I\left(s\right)\right]}$

[0031] In the equation (Eq. 1) above, T.sub.PA(s) represents a reflection coefficient looking back into the output stage 32 of the power amplifier circuit 12 and T.sub.I(s) represents a reflection coefficient looking into the RF front-end circuit 14. Notably, T.sub.PA(s) and T.sub.I(s) are complex filters containing amplitude and phase information. In this regard, the T.sub.PA(s), the T.sub.I(s), and, therefore, the voltage distortion filter H.sub.IV (s) are dependents of such factors as modulation bandwidth, RF spectrum, and/or voltage standing wave ratio (VSWR).

[0032] The equation (Eq. 1) shows that the coupled output voltage V′.sub.OUT will be altered from the non-coupled output voltage V.sub.OUT by the voltage distortion filter H.sub.IV (s) when the power amplifier circuit 12 is coupled to the RF front-end circuit 14. Moreover, the variation of the non-coupled output voltage V.sub.OUT caused by the voltage distortion filter H.sub.IV (s) can happen across an entire modulation bandwidth of the RF signal 22. As a result, the coupled output voltage V′.sub.OUT may become misaligned from the modulated voltage V.sub.cc across the modulation bandwidth of the RF signal 22, thus causing unwanted distortion in the RF signal 22.

[0033] According to various embodiments disclosed herein, it is possible to modify the modulated voltage V.sub.cc to compensate for the voltage distortion filter H.sub.IV (s) to thereby reduce or eliminate the difference between the non-coupled output voltage V.sub.OUT and the coupled output voltage V′.sub.OUT across the modulation bandwidth of the RF signal 22. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter H.sub.IV (s) across the modulation bandwidth of the RF signal 22.

[0034] FIG. 3 is a schematic diagram of an exemplary transmission circuit 38 configured according to an embodiment of the present disclosure to compensate for the unwanted voltage distortion filter H.sub.IV (s) in the existing transmission circuit 10 of FIG. 1A. The transmission circuit 38 is configured to transmit an RF signal 40 modulated in a wide modulation bandwidth. Herein, a modulation bandwidth refers to a range of RF frequencies that the RF signal 40 may be modulated onto. For example, if the RF signal 40 can be modulated between 2554 MHz and 2654 MHz, the modulation bandwidth will then be 100 MHz. In a non-limiting example, the RF signal 40 can be modulated in a modulation bandwidth of 200 MHz or higher and transmitted in a millimeter wave RF spectrum.

[0035] The transmission circuit 38 includes a transceiver circuit 42, a power amplifier circuit 44, and an ETIC 46. The power amplifier circuit 44 is coupled to a transmitter circuit 48 (e.g., an antenna circuit) via an RF front-end circuit 50. In a non-limiting example, the RF front-end circuit 50 can include one or more of a filter circuit and a multiplexer circuit (not shown). The filter circuit may be configured to include a filter network, such as an acoustic filter network with a sharp cutoff frequency. The power amplifier circuit 44 may be identical to or functionally equivalent to the power amplifier circuit 12 in FIG. 1B. As such, the power amplifier circuit 44 may also include the output stage 32 as in the power amplifier circuit 12.

[0036] The transceiver circuit 42 includes a signal processing circuit 52 and a target voltage circuit 54. The signal processing circuit 52 is configured to generate the RF signal 40 from a time-variant modulation vector b.sub.MOD.fwdarw. associated with time-variant amplitudes. The time-variant modulation vector b.sub.MOD.fwdarw. may be generated by a digital baseband circuit (not shown) in the transceiver circuit 42 and includes both in-phase (I) and quadrature (Q) components. Since the time-variant modulation vector b.sub.MOD.fwdarw. is generated in a digital domain, the I and Q components can thus provide a time-variant digital representation of the time-variant amplitudes of the time-variant modulation vector b.sub.MOD.fwdarw..

[0037] The signal processing circuit 52 further includes a modulator circuit 56, which is configured to generate the RF signal 40 in an analog domain based on the time-variant modulation vector b.sub.MOD.fwdarw. and modulate the RF signal 40 onto a selected frequency that falls within the modulation bandwidth of the transmission circuit 38. Understandably, since the modulator circuit 56 generates the RF signal 40 from the time-variant modulation vector b.sub.MOD.fwdarw., the RF signal 40 will be associated with a time-variant power envelope P.sub.ENV that tracks the time-variant amplitudes of the time-variant modulation vector b.sub.MOD.fwdarw.. Accordingly, the I and Q components can also provide a digital representation of the time-variant power envelope P.sub.ENV of the RF signal 40.

[0038] The target voltage circuit 54 is configured to generate a modulated target voltage V.sub.TGT as a function of the time-variant modulation vector b.sub.MOD.fwdarw.. The ETIC 46 is configured to generate a modulated voltage V.sub.cc based on the modulated target voltage V.sub.TGT and provide the modulated voltage V.sub.cc to the power amplifier circuit 44. The power amplifier circuit 44, in turn, amplifies the RF signal 40 from an input power P.sub.IN to an output power P.sub.OUT, which corresponds to an output voltage V.sub.OUT, based on the modulated voltage V.sub.CC. The RF front-end circuit 50 may perform further processes (e.g., filtering, frequency conversion, etc.) on the RF signal 40. As a result, the RF front-end circuit 50 may cause the RF signal 40 to have another output voltage V.sub.OUT1, which can be different from the output voltage V.sub.OUT. Subsequently, the RF front-end circuit 50 provides the RF signal 40 to the transmitter circuit 48 for transmission in the selected frequency.

[0039] Understandably, the closer the modulated voltage V.sub.cc can track the time-variant power envelope P.sub.ENV of the RF signal 40, the better efficiency and linearity can be achieved at the power amplifier circuit 44. However, the voltage distortion filter H.sub.IV (s) resulting from coupling the power amplifier circuit 44 with the RF front-end circuit 50 can change the non-coupled output voltage V.sub.OUT to the coupled output voltage V′.sub.OUT. As a result, the power amplifier circuit 44 can cause undesired instantaneous excessive compression and/or spectrum regrowth in the modulation bandwidth of the transmission circuit 38. As such, it is desirable to reduce the undesired instantaneous excessive compression and/or spectrum regrowth across the modulation bandwidth of the transmission circuit 38.

[0040] As previously described in FIG. 1B, the output voltage V.sub.OUT is a function of the modulated voltage V.sub.CC. In this regard, it is possible to reduce or even eliminate the difference between the non-coupled output voltage V.sub.OUT and the coupled output voltage V′.sub.OUT by generating the modulated voltage V.sub.cc to compensate for the voltage distortion filter H.sub.IV (s). Given that the ETIC 46 is configured to generate the modulated voltage V.sub.cc based on the modulated target voltage V.sub.TGT, it is thus possible to reduce or even eliminate the difference between the non-coupled output voltage V.sub.OUT and the coupled output voltage V′.sub.OUT by generating the modulated target voltage V.sub.TGT to compensate for the voltage distortion filter H.sub.IV (s).

[0041] In this regard, the transceiver circuit 42 further includes an equalizer circuit 58. The equalizer circuit 58 is configured to apply an equalization filter H.sub.EQ(s) to the time-variant modulation vector b.sub.MOD.fwdarw.prior to generating the modulated target voltage V.sub.TGT. In an embodiment, the equalization filter H.sub.EQ(s) can be described by equation (Eq. 2) below.

H.sub.EQ(s)=1/H.sub.RF(s)  (Eq. 2)

[0042] In the equation (Eq. 2) above, H.sub.RF(s) represents a transfer function of the RF front-end circuit 50, which can be expressed as a ratio between V.sub.OUT1 and V.sub.OUT. In this embodiment, the equalizer circuit 58 is configured to apply the equalization filter H.sub.EQ(s) to the time-variant modulation vector b.sub.MOD.fwdarw. to thereby generate a filtered time-variant modulation vector b.sub.MOD-F.fwdarw..

[0043] In an embodiment, the transceiver circuit 42 includes a digital frequency equalizer 60. The digital frequency equalizer 60 is configured to apply a digital frequency equalization filter H.sub.F(s) to the time-variant modulation vector b.sub.MOD.fwdarw. to generate an equalized time-variant modulation vector b.sub.MOD-E.fwdarw.. In a non-limiting example, the digital frequency equalization filter H.sub.F(S) can be described by equation (Eq. 3) below.

H.sub.F(S)=[1/H.sub.ET(S)]*[1/H.sub.RF(s)]

H.sub.ET(S)=H.sub.IQ(s)*H.sub.PA(s)*H.sub.IV(s)  (Eq. 3)

[0044] In the equation (Eq. 3), H.sub.IQ (s) represents a transfer function of the signal processing circuit 52, and H.sub.PA(s) represents a voltage gain transfer function of the power amplifier circuit 44. In this regard, H.sub.ET(S) is a combined complex filter configured to match a combined signal path filter that includes the transfer function H.sub.IQ (s), the voltage gain transfer function H.sub.PA(s), and the voltage distortion filter H.sub.IV (s).

[0045] The target voltage circuit 54 is further configured to include a vector-to-real (V2R) converter 62 that is coupled to the equalizer circuit 58. The V2R converter 62 is configured to extract a selected real parameter X.sub.R from the filtered time-variant modulation vector b.sub.MOD-F.fwdarw.. In a non-limiting example, the selected real parameter X.sub.R can be a real parameter representing the output voltage V.sub.OUT, the input power P.sub.IN, or the output power P.sub.OUT.

[0046] The target voltage circuit 54 can also include a scaler 64 coupled to the V2R converter 62. The scaler 64 can be configured to scale the selected real parameter X.sub.R based on a scaling factor 66 to generate a scaled real parameter X.sub.RS. In an embodiment, the scaling factor 66 can be determined according to an average power (e.g., root-mean-square average) of the RF signal 40. In a non-limiting example, the scaling factor 66 can be adapted between different timeslots or mini timeslots.

[0047] The target voltage circuit 54 also includes an ET look up table (LUT) circuit 68. The ET LUT circuit 68 includes a single LUT (not shown) predetermined according to the selected frequency of the RF signal 40 to correlate the modulated target voltage V.sub.TGT with various types of input parameters. In one example, the LUT can be configured to correlate the modulated target voltage V.sub.TGT with the selected real parameter X.sub.R that represents the output voltage V.sub.OUT. In this regard, if the selected real parameter X.sub.R extracted by the V2R converter 62 indeed represents the output voltage V.sub.OUT, the ET LUT circuit 68 can simply look up the LUT based on the selected real parameter X.sub.R or the scaled real parameter X.sub.RS to generate the modulated target voltage V.sub.TGT.

[0048] In case the selected real parameter X.sub.R extracted by the V2R converter 62 represents something different from the output voltage V.sub.OUT (e.g., the other output voltage V.sub.OUT1), the target voltage circuit 54 may further include a unit converter 70 to convert the selected real parameter X.sub.R to a predefined parameter configured in the LUT. Accordingly, the ET LUT circuit 68 can generate the modulated target voltage V.sub.TGT from the LUT based on the converted real parameter X.sub.R.

[0049] As mentioned earlier, the LUT in the ET LUT circuit 68 may be predetermined based on the selected frequency of the RF signal 40. As the voltage distortion filter H.sub.IV (s) causes the frequency response of the output voltage V.sub.OUT to change, it is equivalent to moving the output voltage V.sub.OUT away from the selected frequency to a different frequency. In this regard, extracting the selected real parameter X.sub.R from the filtered time-variant modulation vector b.sub.MOD-F.fwdarw. is equivalent to moving the LUT along with the frequency change of the output voltage V.sub.OUT. As a result, the modulated target voltage V.sub.TGT generated based on the LUT can compensate for the frequency shift of the output voltage V.sub.OUT.

[0050] The signal processing circuit 52 may further include a memory digital predistortion (mDPD) circuit 72, which is coupled between the digital frequency equalizer 60 and the modulator circuit 56. The mDPD circuit 72 can be configured to digitally pre-distort the equalized time-variant modulation vector b.sub.MOD-E.fwdarw. to generate a pre-distorted time-variant modulation vector b.sub.MOD-DPD.fwdarw.. Accordingly, the modulator circuit 56 is configured to generate the RF signal 40 from the pre-distorted time-variant modulation vector b.sub.MOD-DPD.fwdarw. and provide the RF signal 40 to the power amplifier circuit. 44.

[0051] FIG. 4 is a schematic diagram of an exemplary transmission circuit 74 configured according to another embodiment of the present disclosure to compensate for the unwanted voltage distortion filter H.sub.IV (s) in the existing transmission circuit 10 of FIG. 1A. Common elements between FIGS. 3 and 4 are shown therein with common element numbers and will not be re-described herein.

[0052] The transmission circuit 74 includes a transceiver circuit 76 that includes a digital frequency equalizer circuit 78 and an analog frequency equalizer circuit 80. The digital frequency equalizer circuit 78 is configured to apply a digital frequency equalization filter H.sub.F1 (s) to the time-variant modulation vector b.sub.MOD.fwdarw. to generate an equalized time-variant modulation vector b.sub.MOD-E.fwdarw.. Herein, the mDPD circuit 72 is configured to digitally pre-distort the equalized time-variant modulation vector b.sub.MOD-E.fwdarw. to generate the pre-distorted time-variant modulation vector b.sub.MOD-DPD.fwdarw.. Accordingly, the modulator circuit 56 is configured to generate the RF signal 40 from the pre-distorted time-variant modulation vector b.sub.MOD-DPD.fwdarw..

[0053] The analog frequency equalizer circuit 80 is configured to apply an analog frequency equalization filter H.sub.F2(s) to the RF signal 40 to provide the RF signal 40 to the power amplifier circuit 44. The digital frequency equalization filter H.sub.F1 (5) and the analog frequency equalization filter H.sub.F2(s) can be expressed in equation (Eq. 4) below.

H.sub.F1(s)=1/H.sub.RF(s);H.sub.F2(s)=1/H.sub.ET(s)  (Eq. 4)

[0054] In this embodiment, the equalizer circuit 58 is configured to apply the equalization filter H.sub.EQ(s) to the first equalized time-variant modulation vector b.sub.MOD-E1.fwdarw.. The equalization filter H.sub.EQ(s) is equal to 1.

[0055] FIG. 5 is a graphic diagram providing an exemplary illustration of a modulation bandwidth 82 in which the transmission circuit 38 of FIG. 3 and the transmission circuit 74 of FIG. 4 can be configured to compensate for the unwanted voltage distortion filter in the existing transmission circuit of FIG. 1A. Elements in FIGS. 3 and 4 are referenced in conjunction with FIG. 5 and will not be redescribed herein.

[0056] In this example, the modulation bandwidth 82 is bounded by a lower frequency 84 and an upper frequency 86. The LUT in the ET LUT circuit 68 in FIGS. 3 and 4 is initially determined based on a selected frequency 88 that falls between the lower frequency 84 and the upper frequency 86. In this regard, the selected real parameter X.sub.R extracted from the filtered time-variant modulation vector b.sub.MOD-F.fwdarw. is equivalent to moving the LUT from the selected frequency 88 to any other frequency within the modulation bandwidth 82.

[0057] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.