VOLTAGE RIPPLE SUPPRESSION IN A TRANSMISSION CIRCUIT

Abstract

Voltage ripple suppression in a transmission circuit is disclosed. The transmission circuit includes a power amplifier circuit coupled to an envelope tracking integrated circuit (ETIC) via a conductive path. Notably, the ETIC and the conductive path can present a large source impedance to the power amplifier circuit, which can cause a ripple in the modulated voltage received by the power amplifier circuit. In a conventional approach, the large source impedance may be isolated by a large decoupling capacitor at the expense of increased voltage switching time and battery current drain. In contrast, the ETIC disclosed herein can determine and apply a correction term to the modulated voltage generated by the ETIC to thereby suppress the ripple without requiring the large decoupling capacitor. By eliminating the large decoupling capacitor, the transmission circuit can thus achieve fast voltage switching with lower battery current drain.

Claims

1. A transmission circuit comprising: a power amplifier (PA) circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage received at a PA input; and an envelope tracking (ET) integrated circuit (ETIC) comprising: an ETIC output coupled to the PA input via a conductive path; a voltage modulation circuit configured to generate the modulated voltage at the ETIC output based on a modulated target voltage and a feedback signal that indicates a selected one of the modulated voltage at the ETIC output and the modulated voltage at the PA input; and a control circuit configured to: generate a correction term based on the modulated voltage at the ETIC output and the modulated voltage at the PA input; and apply the correction term to a selected one of the modulated target voltage and the feedback signal to cause the voltage modulation circuit to modify the modulated voltage to thereby suppress a ripple in the modulated voltage at the PA input.

2. The transmission circuit of claim 1, wherein the voltage modulation circuit comprises: a voltage amplifier comprising a positive input configured to receive the modulated target voltage and a negative input configured to receive the feedback signal, the voltage amplifier is configured to generate an initial modulated voltage based on the modulated target voltage and the feedback signal; and an offset capacitor coupled between the voltage amplifier and the ETIC output, the offset capacitor is configured to raise the initial modulated voltage by an offset voltage to thereby generate the modulated voltage at the ETIC output.

3. The transmission circuit of claim 1, further comprising a feedback circuit coupled between the ETIC output and the voltage modulation circuit and configured to generate the feedback signal that indicates the modulated voltage at the ETIC output.

4. The transmission circuit of claim 3, wherein the control circuit is further configured to apply the correction term to the feedback signal to thereby cause the voltage modulation circuit to modify the modulated voltage.

5. The transmission circuit of claim 4, wherein the correction term is a voltage correction term expressed as: −K*ΔV, wherein: ΔV represents a voltage differential between the modulated voltage at the ETIC output and the modulated voltage at the PA input; and K represents a gain factor.

6. The transmission circuit of claim 4, further comprising an input circuit coupled between the control circuit and the voltage modulation circuit, the input circuit is configured to receive the correction term from the control circuit and apply the correction term to the feedback signal.

7. The transmission circuit of claim 6, wherein the input circuit is configured to provide a time advance in the correction term.

8. The transmission circuit of claim 4, wherein the correction term is a current correction term expressed as: −G.sub.m*ΔV, wherein: ΔV represents a voltage differential between the modulated voltage at the ETIC output and the modulated voltage at the PA input; and G.sub.m represents a transconductance that converts the voltage differential into the current correction term.

9. The transmission circuit of claim 8, further comprising an input circuit coupled between the voltage modulation circuit and a ground, the input circuit is configured to convert the current correction term to a voltage correction term.

10. The transmission circuit of claim 3, wherein the control circuit is further configured to apply the correction term to the modulated target voltage to thereby cause the voltage modulation circuit to modify the modulated voltage.

11. The transmission circuit of claim 10, wherein the correction term is a current correction term expressed as: G.sub.m*ΔV, wherein: ΔV represents a voltage differential between the modulated voltage at the ETIC output and the modulated voltage at the PA input; and G.sub.m represents a transconductance that converts the voltage differential into the current correction term.

12. The transmission circuit of claim 11, further comprising a target voltage circuit configured to: receive the modulated target voltage; receive the current correction term from the control circuit; and modify the modulated target voltage based on the current correction term to thereby cause the voltage modulation circuit to modify the modulated voltage.

13. The transmission circuit of claim 11, further comprising a resistor circuit configured to convert the current correction term into a voltage correction term.

14. The transmission circuit of claim 1, further comprising a feedback circuit coupled between the PA input and the voltage modulation circuit and configured to generate the feedback signal that indicates the modulated voltage at the PA input.

15. The transmission circuit of claim 14, wherein the control circuit is further configured to apply the correction term to the feedback signal to thereby cause the voltage modulation circuit to modify the modulated voltage.

16. The transmission circuit of claim 15, wherein the correction term is a voltage correction term expressed as: −K*ΔV, wherein: ΔV represents a voltage differential between the modulated voltage at the ETIC output and the modulated voltage at the PA input; and K represents a gain factor.

17. The transmission circuit of claim 15, further comprising an input circuit coupled between the control circuit and the voltage modulation circuit, the input circuit is configured to receive the correction term from the control circuit and apply the correction term to the feedback signal.

18. The transmission circuit of claim 17, wherein the input circuit is configured to provide a time advance in the correction term.

19. The transmission circuit of claim 1, wherein the control circuit comprises an operational amplifier (op-amp) having a negative op-amp input coupled the ETIC output and a positive op-amp input coupled to the PA input, the op-amp is configured to generate the correction term based on a voltage differential between the modulated voltage at the ETIC output and the modulated voltage at the PA input.

20. The transmission circuit of claim 19, wherein the control circuit further comprises a compensation circuit coupled between the negative op-amp input and the positive op-amp input, the compensation circuit is configured to generate a compensation term in the correction term to thereby offset a variation in the voltage differential resulting from a decoupling capacitor coupled to the PA input and a ground.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1 is a schematic diagram of an exemplary transmission circuit that can be configured based on various embodiments of the present disclosure to support voltage ripple suppression;

[0013] FIG. 2 is a schematic diagram providing an exemplary illustration of an envelope tracking integrated circuit (ETIC) in the transmission circuit of FIG. 1, which can be configured according to embodiments of the present disclosure to enable voltage ripple suppression in the transmission circuit;

[0014] FIGS. 3-7 are schematic diagrams providing exemplary illustrations of the ETIC in FIG. 2 configured according to various embodiments of the present disclosure; and

[0015] FIG. 8 is a schematic diagram providing an exemplary illustration of a control circuit in the ETIC of FIGS. 3-7.

DETAILED DESCRIPTION

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0019] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Embodiments of the disclosure relate to voltage ripple suppression in a transmission circuit. Specifically, the transmission circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage, and an envelope tracking (ET) integrated circuit (ETIC) configured to generate and provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, the ETIC and the conductive path can present a large source impedance to the power amplifier circuit, which can cause a ripple in the modulated voltage received by the power amplifier circuit to potentially distort the RF signal. In a conventional approach, the large source impedance may be isolated by a large decoupling capacitor at the expense of increased voltage switching time and battery current drain. In contrast, the ETIC disclosed herein can determine and apply a correction term to the modulated voltage generated by the ETIC to thereby suppress the ripple without requiring the large decoupling capacitor. By eliminating the large decoupling capacitor, the transmission circuit can thus achieve fast voltage switching with lower battery current drain.

[0023] FIG. 1 is a schematic diagram of an exemplary transmission circuit 10 that can be configured based on various embodiments of the present disclosure to support voltage ripple suppression. The transmission circuit 10 includes a power amplifier circuit 12 and an ETIC 14. The ETIC 14 is configured to generate a modulated voltage V.sub.CC at an ETIC output 16 based on a modulated target voltage V.sub.TGT. The power amplifier circuit 12 is configured to receive the modulated voltage V.sub.CC at a power amplifier input 18. The power amplifier input 18 is coupled to the ETIC output 16 via a conductive path 20, which can be a conductive trace, as an example. Accordingly, the power amplifier circuit 12 can be configured to amplify an RF signal 22 based on the modulated voltage V.sub.CC. In a non-limiting example, the modulated target voltage V.sub.TGT and the RF signal 22 can be generated by a transceiver circuit 24.

[0024] For distinction, the modulated voltage V.sub.CC generated by the ETIC 14 at the ETIC output 16 is hereinafter referred to as “generated modulated voltage V.sub.CC.” In contrast, the modulated voltage V.sub.CC received by the power amplifier circuit 12 at the power amplifier input 18 is hereinafter referred to as “received modulated voltage V.sub.PA.”

[0025] In a non-limiting example, the ETIC 14 has an inherent ETIC impedance Z.sub.ETIC, the conductive path 20 has an inherent trace impedance Z.sub.TRACE (e.g., an inductive impedance), and the power amplifier circuit 12 has an inherent power amplifier impedance Z.sub.PA. In this regard, the ETIC 14 and the conductive path 20 can collectively present a large source impedance (Z.sub.ETIC+Z.sub.TRACE) to the power amplifier circuit 12. The power amplifier circuit 12, on the other hand, is configured to operate as a current source to draw a modulated current I.sub.CC. As such, the large source impedance (Z.sub.ETIC+Z.sub.TRACE) in conjunction with the modulated current I.sub.CC can cause a ripple in the received modulated voltage V.sub.PA to potentially distort the RF signal 22.

[0026] Conventionally, it may be possible to isolate the large source impedance (Z.sub.ETIC+Z.sub.TRACE) from the power amplifier circuit 12, and thereby suppress the ripple in the received modulated voltage V.sub.PA, by coupling a decoupling capacitor (not shown) with a large-enough capacitance to the power amplifier input 18. However, doing so can cause some obvious issues.

I.sub.CC=C*dV.sub.CC/dt   (Eq. 1)

[0027] As shown in equation (Eq. 1), the larger capacitance (C) the decoupling capacitor has, the larger amount of the modulated current I.sub.CC would be needed to change the modulated voltage V.sub.CC at a required change rate (dV.sub.CC/dt). As a result, the transmission circuit 10 may cause a negative impact on battery life. On the other hand, if the modulated current I.sub.CC is kept at a low level to prolong battery life, the transmission circuit 10 may have difficulty meeting the required change rate (dV.sub.CC/dt). Consequently, the transmission circuit 10 may not be able to change the modulated voltage V.sub.CC between orthogonal frequency division multiplexing (OFDM) symbols, especially when the RF signal 22 is modulated with a higher modulation bandwidth (e.g., >200 NHz). Hence, it is desirable to suppress the ripple in the received modulated voltage V.sub.PA without employing the large-capacitance decoupling capacitor to thereby improve battery life and enable fast switching of the modulated voltage V.sub.CC.

[0028] In this regard, FIG. 2 is a schematic diagram providing an exemplary illustration of the ETIC 14 in FIG. 1, which can be configured according to embodiments of the present disclosure to suppress the ripple in the received modulated voltage V.sub.PA without requiring the large-capacitance decoupling capacitor. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0029] In an embodiment, the ETIC 14 includes a voltage modulation circuit 26 and a control circuit 28. The voltage modulation circuit 26 is configured to generate the modulated voltage V.sub.CC (a.k.a. the generated modulated voltage V.sub.CC) at the ETIC output 16 based on the modulated target voltage V.sub.TGT and a feedback signal 30. As described in various embodiments in FIGS. 3 to 7, the feedback signal 30 can indicate a selected one of the generated modulated voltage V.sub.CC and the received modulated voltage V.sub.PA. The control circuit 28, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example, is configured to generate a correction term C.sub.TERM based on a voltage differential ΔV between the generated modulated voltage V.sub.CC and the received modulated voltage V.sub.PA (ΔV=V.sub.CC−V.sub.PA). As further described in various embodiments in FIGS. 3 to 7, the control circuit 28 can apply the correction term C.sub.TERM to a selected one of the modulated target voltage V.sub.TGT and the feedback signal 30 to cause the voltage modulation circuit 26 to modify the generated modulated voltage V.sub.CC to thereby suppress the ripple in the received modulated voltage V.sub.PA. By suppressing the ripple in the received modulated voltage V.sub.PA based on the correction term C.sub.TERM, as opposed to employing the large-capacitance decoupling capacitor, the transmission circuit 10 can thus improve battery life and enable fast switching of the modulated voltage V.sub.CC.

[0030] The ETIC 14 can be configured according to various embodiments of the present disclosure. Specific embodiments of the ETIC 14 are described now with reference to FIGS. 3 to 7. Common elements between FIGS. 1 to 7 are shown therein with common element numbers and will not be re-described herein.

[0031] FIG. 3 is a schematic diagram of an exemplary ETIC 14A configured according to one embodiment of the present disclosure. The voltage modulation circuit 26 includes a voltage amplifier 32 (denoted as “V.sub.PA”). In a non-limiting example, the voltage amplifier 32 can be an operational amplifier (op-amp) having a positive input 34P (denoted as “+”) and a negative input 34M (denoted as “−”). Herein, the positive input 34P is configured to receive the modulated voltage V.sub.TGT and the negative input 34M is configured to receive the feedback signal 30 and the correction term C.sub.TERM. Accordingly, the voltage amplifier 32 is configured to generate an initial modulated voltage V.sub.AMP based on the modulated target voltage V.sub.TGT, the feedback signal 30, the correction term C.sub.TERM, and a supply voltage V.sub.SUP.

[0032] The voltage modulation circuit 26 also includes an offset capacitor C.sub.OFF, which is coupled between the voltage amplifier 32 and the ETIC output 16. The offset capacitor C.sub.OFF is configured to raise the initial modulated voltage V.sub.AMP by an offset voltage V.sub.OFF to thereby generate the modulated voltage V.sub.CC (V.sub.CC=V.sub.AMP+V.sub.OFF) at the ETIC output 16. Notably, by providing the offset capacitor C.sub.OFF, the initial modulated voltage V.sub.AMP will be lower than the modulated voltage V.sub.CC. As a result, an output stage of the voltage amplifier 32 (not shown) can be implemented using a smaller transistor(s) to thereby reduce footprint and improve operating efficiency.

[0033] The ETIC 14A includes a feedback circuit 36 coupled between the ETIC output 16 and the negative input 34M. Accordingly, the feedback circuit 36 is configured to generate the feedback signal 30 to indicate the generated modulated voltage V.sub.CC and provide the feedback signal 30 to the negative input 34M.

[0034] In this embodiment, the control circuit 28 is coupled to the negative input 34M via an input circuit 38. Accordingly, the control circuit 28 is configured to generate the correction term C.sub.TERM based on the voltage differential ΔV and provides the correction term C.sub.TERM to the input circuit 38.

[0035] The input circuit 38 receives the correction term C.sub.TERM from the control circuit 28. Accordingly, the input circuit 38 can apply the correction term C.sub.TERM to the feedback signal 30, which indicates the generated modulated voltage V.sub.CC, to thereby cause the voltage modulation circuit 26 to modify the generated modulated voltage V.sub.CC to suppress the ripple in the received modulated voltage V.sub.PA. In an embodiment, the input circuit 38 may include a time advance circuit 40, which can be a resistor-capacitor (RC) circuit, as an example. The time advance circuit 40 is configured to provide a time advance in the correction term C.sub.TERM before applying the correction term C.sub.TERM to the feedback signal 30. In a non-limiting example, the time advance can be so determined to compensate for a processing delay in the voltage amplifier 32.

[0036] In a non-limiting example, the control circuit 28 can generate the correction term C.sub.TERM as a function of the voltage differential ΔV, as expressed in equation (Eq. 2) below.

C.sub.TERM=−K*ΔV   (Eq. 2)

[0037] In the equation (Eq. 2), K represents a gain factor, which can be expressed in equation (Eq. 3) below.

K=(1+Z.sub.ETIC/Z.sub.TRACE)/(Z.sub.2/Z.sub.1)   (Eq. 3)

[0038] In the equation (Eq. 3), Z.sub.1 represents an inherent impedance of the input circuit 38 and Z.sub.2 represents an inherent impedance of the feedback circuit 36. As a function of the voltage differential ΔV, the correction term C.sub.TERM is a voltage correction term. In this regard, the correction term C.sub.TERM can be applied directly to the feedback signal 30 that indicates the generated voltage V.sub.CC.

[0039] In an alternative embodiment, the control circuit 28 may also be configured to generate the correction term C.sub.TERM as a current correction term. In this regard, FIG. 4 is a schematic diagram of an exemplary ETIC 14B configured according to another embodiment of the present disclosure.

[0040] Herein, the feedback circuit 36 is also configured to generate the feedback signal 30 to indicate the generated modulated voltage V.sub.CC. The input circuit 38, however, is coupled between the negative input 34M and a ground (GND). The control circuit 28, on the other hand, is coupled directly to the negative input 34M and configured to provide the correction term C.sub.TERM directly to the negative input 34M. Herein, the control circuit 28 is configured to generate the correction term C.sub.TERM as a current correction term, as expressed in equation (Eq. 4).

C.sub.TERM=−G.sub.m*ΔV   (Eq. 4)

[0041] In the equation (Eq. 4), G.sub.m represents a transconductance that converts the voltage differential ΔV into the current correction term. The transconductance G.sub.m may be determined based on equation (Eq. 5) below.

G.sub.m=(1+Z.sub.ETIC/Z.sub.TRACE)/Z.sub.2   (Eq. 5)

[0042] Notably, when the current correction term is provided to the negative input 34M, the inherent impedance Z.sub.1 of the input circuit 38 can cause the current correction term to be converted back to a voltage correction term.

[0043] In an embodiment, the voltage amplifier 32 may generate a sensed current I.sub.SENSE to indicate the modulated current I.sub.CC being sourced or sunk by the voltage amplifier 32. The sensed current I.sub.SENSE may be used by a stability circuit 42 to help improve stability of the correction term C.sub.TERM across a modulation bandwidth of the RF signal 22.

[0044] Alternative to applying the correction term C.sub.TERM to the feedback signal 30, it is also possible to apply the correction term C.sub.TERM to the modulated voltage V.sub.TGT, as described next in FIGS. 5 and 6.

[0045] FIG. 5 is a schematic diagram of an exemplary ETIC 14C configured according to another embodiment of the present disclosure. The ETIC 14C includes a target voltage circuit 44. The target voltage circuit 44 is configured to receive the modulated target voltage V.sub.TGT and the correction term C.sub.TERM from the control circuit 28. Accordingly, the target voltage circuit 44 modifies the modulated target voltage V.sub.TGT based on the correction term C.sub.TERM to generate a modified target voltage V′.sub.TGT and provides the modified target voltage V′.sub.TGT to the positive input 34P to thereby cause the voltage modulation circuit 26 to modify the generated modulated voltage V.sub.CC.

[0046] In a non-limiting example, the modified target voltage V′.sub.TGT can be expressed in equation (Eq. 6) below.

V′.sub.TGT=V.sub.TGT+V.sub.CORRECTION   (Eq. 6)

[0047] In the equation (Eq. 6), V.sub.CORRECTION represents a target voltage correction term to be added to the modulated voltage V.sub.TGT. Herein, the control circuit 28 is configured to generate the correction term C.sub.TERM as a current correction, as expressed in equation (Eq. 7) below.

C.sub.TERM=G.sub.m*ΔV   (Eq. 7)

[0048] In the equation (Eq. 7), G.sub.m represents a transconductance that converts the voltage differential ΔV into the current correction term. In this regard, the target voltage circuit 44, which as an inherent impedance Z.sub.0, needs to convert the correction term C.sub.TERM into the target voltage correction term V.sub.CORRECTION to be added to the modulated voltage V.sub.TGT.

[0049] The target voltage circuit 44 may be replaced by a resistor circuit with the inherent impedance Z.sub.0. In this regard, FIG. 6 is a schematic diagram of an exemplary ETIC 14D configured according to another embodiment of the present disclosure.

[0050] The ETIC 14D includes a resistor circuit 45 coupled between the positive input 34P and the GND. Notably, the resistor circuit 45 can effectively convert the correction term C.sub.TERM, which was generated as the current correction term based on the equation (Eq.7), into the target voltage correction term V.sub.CORRECTION to be added to the modulated voltage V.sub.TGT.

[0051] Alternative to generating the feedback signal 30 to indicate the generated modulated voltage V.sub.CC, as described in FIGS. 3 to 6, it is also possible to generate the feedback signal 30 to indicate the received modulated voltage V.sub.PA. In this regard, FIG. 7 is a schematic diagram of an exemplary ETIC 14E configured according to another embodiment of the present disclosure.

[0052] Herein, the feedback circuit 36 is configured to generate the feedback signal 30 to indicate the received modulated voltage V.sub.PA at the power amplifier input 18. In this regard, the control circuit 28 can determine the correction term C.sub.TERM in accordance with equation (Eq. 8) below.

C.sub.TERM=−K*ΔV   (Eq. 8)

[0053] In the equation (Eq. 8), K represents a gain factor, which can be expressed in equation (Eq. 9) below.

K=[(Z.sub.ETIC+Z.sub.PA)/Z.sub.TRACE]*(Z.sub.1/Z.sub.2)   (Eq. 9)

[0054] With reference back to FIG. 1, although it is undesirable to couple a large-capacitance decoupling capacitor to the power amplifier input 18, it is nevertheless possible to provide a much smaller decoupling capacitor C.sub.PA inside the power amplifier circuit 12 to help provide some level of impedance isolation. As such, the correction term C.sub.TERM may need to take into consideration the possible interaction between the decoupling capacitor C.sub.PA and the modulated current I.sub.CC. As such, the control circuit 28 may be configured to add a compensation term to the correction term C.sub.TERM to compensate for impact caused by the decoupling capacitor C.sub.PA.

[0055] In this regard, FIG. 8 is a schematic diagram providing an exemplary illustration of the control circuit 28 in FIGS. 2 to 7 according to an embodiment of the present disclosure. Common elements between FIGS. 2 to 8 are shown therein with common element numbers and will not be re-described herein.

[0056] The control circuit 28 includes an op-amp 46. The op-amp 46 includes a positive op-amp input 48P and a negative op-amp input 48M. The negative op-amp input 48M is coupled to the ETIC output 16 to receive the generated modulated voltage V.sub.CC. The positive op-amp input 48P is coupled to the power amplifier input 18 to receive the received modulated voltage V.sub.PA. The op-amp 46 is configured to generate the correction term C.sub.TERM as a function of the voltage differential ΔV and output the correction term C.sub.TERM via an op-amp output 50. Notably, the op-amp 46 is configured to generate the correction term C.sub.TERM as a voltage correction term. In this regard, the op-amp 46 may be further configured to include or be coupled to a transconductance stage (not shown) to convert the voltage correction term into a current correction term, as needed.

[0057] The control circuit 28 may further include a compensation circuit 52 coupled between the positive op-amp input 48P and the negative op-amp input 48M. In a non-limiting example, the compensation circuit 52 includes a compensation op-amp 54, which includes a positive compensation input 56P, a negative compensation input 56M, and a compensation output 58. The compensation circuit 52 also includes multiple resistor-capacitor (RC) circuits 60(1)-60(4).

[0058] The RC circuit 60(1) may be provided between the ETIC output 16 and the negative op-amp input 48M. The RC circuits 60(2) and 60(4) may be provided in series between the power amplifier input 18 and the positive op-amp input 48P. The RC circuit 60(3) may be provided between the compensation output 58 and the negative op-amp input 48M. The negative compensation input 56M is coupled to the positive op-amp input 48P via a capacitor C.sub.1 and the RC circuits 60(2) and 60(3). The positive compensation input 56P may be coupled to the GND.

[0059] In an embodiment, the compensation circuit 52 is configured to generate a compensation term V.sub.CORR in the correction term C.sub.TERM to thereby offset a variation in the voltage differential ΔV resulting from the decoupling capacitor C.sub.PA. Specifically, the correction term C.sub.TERM can be determined based on a second order transfer function as expressed in equation (Eq. 10) below.

C.sub.TERM=−ΔV*(R.sub.4/R.sub.2)*(1+R.sub.2*C.sub.2*s)+V.sub.PA*(R.sub.1*R.sub.4*C.sub.1*C.sub.3*s.sup.2)/(1+R.sub.3*C.sub.3*s)   (Eq. 10)

[0060] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.