Control strategy of a dual lane fault tolerant permanent magnet motor to reduce drag torque under fault condition
10320183 ยท 2019-06-11
Assignee
Inventors
Cpc classification
H02P29/028
ELECTRICITY
H02P29/032
ELECTRICITY
International classification
H02P29/032
ELECTRICITY
Abstract
A motor drive circuit comprising two or more inverters to provide current to a permanent magnet motor. Each inverter includes a respective switch arm comprising one or more switches for each phase of the motor to be driven. The motor drive circuit includes means for detecting a switch short circuit for any switch within one of the inverters and means for determining the speed of the motor. The motor drive circuit further includes a controller configured to short circuit each switch arm of the inverter containing the switch short circuit if the motor speed exceeds a predetermined threshold, but not if the motor speed does not exceed the predetermined threshold.
Claims
1. A motor drive circuit comprising: two or more inverters to provide current to a dual lane fault tolerant three-phase permanent magnet motor, each inverter comprising, for each phase of the motor to be driven, a respective switch arm comprising one or more switches; means for detecting a switch short circuit for any switch within one of the inverters; means for determining the speed of the motor; and a controller configured, in the event a switch short circuit is detected within one of the inverters, to: a): close all switch arms of the inverter containing the switch short circuit when the motor speed exceeds a predetermined threshold, and b): not to close any of the switch arms not containing the short-circuited switch if the motor speed does not exceed the predetermined threshold.
2. The motor drive circuit of claim 1, wherein each switch arm comprises two switches connected in series.
3. A method of controlling a motor drive circuit for driving a dual lane fault tolerant permanent magnet motor, the method comprising: monitoring the motor speed of the dual lane fault tolerant permanent magnet motor; detecting when a switch short circuit occurs in any switch in any of two inverters connected to the dual lane fault tolerant permanent magnet motor; comparing the motor speed to a predetermined threshold; short-circuiting all motor phases of a the dual lane fault tolerant motor connected to the inverter in response to detection of both: i) a switch short circuit in any switch in the inverter, and ii) the motor speed exceeding a predetermined threshold; and not short-circuiting any motor phases not containing the short-circuited switch if the motor speed does not exceed the predetermined threshold.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Preferred embodiments will now be described by way of example only, with reference to the drawings.
(2)
(3)
(4)
(5)
DETAILED DESCRIPTION
(6)
(7) As can be seen from
(8) If, for example, switch 1 of
(9) This can also be seen with reference to
(10) In the example shown, a faulta short circuit in switch 1is detected in the inverter shown to the left of the diagram.
(11) This inverter is then deactivated and control is switched over to the healthy inverter.
(12) As mentioned above, a problem is that even though the faulty inverter is no longer driving the motor, there will still be some residual loss and drag torque effects from it.
(13) As can be seen in
(14) The description is presented in relation to a so-called 3n+3 architecture, where n represents the number of channels in a multiple three phase system. The invention can also apply to n+1 architectures (as shown in
(15) This method of control enables the reduction of the size and weight of the system for fault tolerant motor drive architectures.