Control strategy of a dual lane fault tolerant permanent magnet motor to reduce drag torque under fault condition

10320183 ยท 2019-06-11

Assignee

Inventors

Cpc classification

International classification

Abstract

A motor drive circuit comprising two or more inverters to provide current to a permanent magnet motor. Each inverter includes a respective switch arm comprising one or more switches for each phase of the motor to be driven. The motor drive circuit includes means for detecting a switch short circuit for any switch within one of the inverters and means for determining the speed of the motor. The motor drive circuit further includes a controller configured to short circuit each switch arm of the inverter containing the switch short circuit if the motor speed exceeds a predetermined threshold, but not if the motor speed does not exceed the predetermined threshold.

Claims

1. A motor drive circuit comprising: two or more inverters to provide current to a dual lane fault tolerant three-phase permanent magnet motor, each inverter comprising, for each phase of the motor to be driven, a respective switch arm comprising one or more switches; means for detecting a switch short circuit for any switch within one of the inverters; means for determining the speed of the motor; and a controller configured, in the event a switch short circuit is detected within one of the inverters, to: a): close all switch arms of the inverter containing the switch short circuit when the motor speed exceeds a predetermined threshold, and b): not to close any of the switch arms not containing the short-circuited switch if the motor speed does not exceed the predetermined threshold.

2. The motor drive circuit of claim 1, wherein each switch arm comprises two switches connected in series.

3. A method of controlling a motor drive circuit for driving a dual lane fault tolerant permanent magnet motor, the method comprising: monitoring the motor speed of the dual lane fault tolerant permanent magnet motor; detecting when a switch short circuit occurs in any switch in any of two inverters connected to the dual lane fault tolerant permanent magnet motor; comparing the motor speed to a predetermined threshold; short-circuiting all motor phases of a the dual lane fault tolerant motor connected to the inverter in response to detection of both: i) a switch short circuit in any switch in the inverter, and ii) the motor speed exceeding a predetermined threshold; and not short-circuiting any motor phases not containing the short-circuited switch if the motor speed does not exceed the predetermined threshold.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Preferred embodiments will now be described by way of example only, with reference to the drawings.

(2) FIG. 1 is a block diagram of a typical 3-phase motor drive system;

(3) FIGS. 2 and 3 are block diagrams of a multi-channel, 3-phase (3+3) motor drive system;

(4) FIGS. 4 and 5 show drag torque and ohmic losses occurring when a single or three-switch short circuits;

(5) FIG. 6 is a circuit diagram for a multichannel, singe phase motor drive system.

DETAILED DESCRIPTION

(6) FIG. 5 shows drag torque and ohmic loss in systems operating as described in relation to the prior art, in the event of an inverter switch short-circuit failure. FIG. 5 also shows, in contrast, the ohmic loss and drag torque characteristics if the other switches of the faulty inverter are closed or shorted.

(7) As can be seen from FIG. 5, below motor speed N_tran, the ohmic losses for a system where all of the inverter switches are shorted, in the case of a faulty inverter switch, within a given lane, are very high but, for this mode of operation, after the speed has increased to beyond N_tran, the losses sink considerably. On the other hand, for speeds below N_tran, the losses in the prior art systems are comparatively less, but are higher at higher speeds. This effect is taken into account when operating the invention such that, according to motor speed, an appropriate mode is selected. The present invention reads the motor speed and the controller decides whether to short the phases of the motor connected to the faulty inverter or continue to work as it is. The transition speed is N_trans. If the present invention were not brought into effect, at these higher speeds, an inverter switch short-circuit would result in a high level of drag torque and extremely high losses. By shorting all of the motor phases in the faulty lane, at speeds greater than N_tran, drag torque and losses are greatly reduced and the system can, accordingly, be smaller in size.

(8) If, for example, switch 1 of FIG. 2 is shorted, then by closing switches 3 and 5, the three phases of the motor will be shorted. On the other hand, if a lower switch (4, 6 or 2) is shorted, then by closing the remaining two switches on the lower leg of the inverter, the three motor phase windings are shorted.

(9) This can also be seen with reference to FIG. 3. Here, for a three-phase motor, two inverters are provided to allow switching to a healthy inverter in the event of one inverter being faulty.

(10) In the example shown, a faulta short circuit in switch 1is detected in the inverter shown to the left of the diagram.

(11) This inverter is then deactivated and control is switched over to the healthy inverter.

(12) As mentioned above, a problem is that even though the faulty inverter is no longer driving the motor, there will still be some residual loss and drag torque effects from it.

(13) As can be seen in FIG. 5, and as described above, at lower motor speeds, the ohmic losses and drag torque are minimised by not closing other (non-shorted) switches of the faulty inverter, but above a certain motor speed N_tran, the loss/drag torque characteristics change and are significantly reduced if the feature of the present invention is implemented, namely that the other switches (in the example shownswitches 3 and 5) are also shorted.

(14) The description is presented in relation to a so-called 3n+3 architecture, where n represents the number of channels in a multiple three phase system. The invention can also apply to n+1 architectures (as shown in FIG. 6), where n represents the number of channels in a multiple single phase system. FIG. 6, for example, shows a multi-channel drive for a single phase motor. Here, four switches are required. The general operation, however, is the same as for the multi-phase drives described above.

(15) This method of control enables the reduction of the size and weight of the system for fault tolerant motor drive architectures.