Electro-optic display backplane structure with drive components and pixel electrodes on opposed surfaces

Abstract

The subject matter presented herein relates to a method for producing a backplane for electro-optic displays. The method may include providing a substrate coated with a first conductive material on a first side and a second conductive material on a second side, the second side being positioned opposite from the first side, patterning the first conductive material by cutting through the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit and creating a plurality of vias on the substrate, the plurality of vias extending through the substrate and providing electrical conductivity between the first and second sides. The method may further include creating a plurality of conductive traces on the second side of the substrate by patterning the second conductive material by locally align the vias to the driver circuit.

Claims

1. A method for producing a backplane for electro-optic displays comprising: providing a substrate coated with a first conductive material on a first side and a second conductive material on a second side, the second side being positioned opposite from the first side, wherein the substrate is at least 24 inches by 48 inches in size; patterning the first conductive material by scribing the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit; creating a plurality of vias through the substrate, the plurality of vias extending through the substrate and providing electrical conductivity between the first and second sides; and creating a plurality of conductive traces on the second side of the substrate by patterning the second conductive material by locally align the vias to the driver circuit.

2. The method of claim 1, wherein the pattering the first conductive material step comprising cutting through the first conductive material using mechanical forces.

3. The method of claim 1, wherein the patterning the first conductive material step comprising cutting through the first conductive material using a beam of energy or particles.

4. The method of claim 3, wherein cutting through the first conductive material comprising using a laser.

5. The method of claim 4, wherein the creating a plurality of conductive traces step comprising placing conductive material from the vias to the driver circuit.

6. A method for producing a backplane for electro-optic displays comprising: providing a substrate coated with a first conductive material on a first side, wherein the substrate is at least 24 inches by 48 inches in size; patterning the first conductive material by scribing the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit; creating a plurality of vias through the substrate, the plurality of vias extending through the substrate; and creating a plurality of conductive traces on a second side of the substrate connecting the vias to the driver circuit, the second side being position opposite to the first side of the substrate.

7. The method of claim 6, wherein placing conductive material comprising using a plotter to place conductive material between the vias and the driver circuit.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic circuit diagram of one pixel of an active matrix electro-optic display according to some embodiments.

(2) FIG. 2 is a top plan view showing a single pixel of the viewing surface of a display according to some embodiments.

(3) FIG. 3 is a top plan view of the front surface of a backplane of the present invention having a 55 pixel array.

(4) FIG. 4 is a plan view of the reverse surface of the backplane shown in FIG. 3 a single driver and connections thereto.

(5) FIG. 5 is a plan view similar to that of FIG. 4 but is an embodiment showing two drivers and connections thereto.

(6) FIG. 6 is an illustrative representation of the present invention used in a large scale sign.

(7) FIG. 7 is a cross-sectional view of a backplane of the invention showing a pixel electrode, via, and driver chip.

(8) FIG. 8 illustrates an exemplary pixel conductor layer with a plurality of irregularly shaped pixel driving electrodes in accordance with the subject matter presented herein;

(9) FIG. 9 illustrates an exemplary substrate for assemble a backplane in accordance with the subject matter presented herein;

(10) FIG. 10 illustrates a reverse side conductor layer with conductive traces in accordance with the subject matter presented herein.

DETAILED DESCRIPTION

(11) The use of electro-optic display technology is expanding beyond electronic document reader applications to a variety of electronic display products including product labels, retail shelf labels, device monitoring indicators, wristwatches, signs, and promotional or advertising displays. Typically, electro-optic displays are encased by a frame or a bezel to hide the electrical connections of the display which generally lay alongside the display. In some applications, specifically, large scale tiled displays, it is generally preferred that the entire viewing area of an electro-optic display be optically active; for example, a billboard made by tiling a plurality of electro-optic displays together to create a large display, where the entire viewing surface of each individual display is optically active and the space between each display is minimized, such that the large display appears as a single continuous display.

(12) Accordingly, this invention provides for an electro-optic display having a backplane with circuit elements on at least two surfaces, a plurality of pixel electrodes arranged in an array of rows and columns on the front surface of the backplane having row and column lines, at least one driver chip on the reverse surface (opposite the front surface of the backplane), and conductive vias connecting the row and column lines of the plurality of pixel electrodes on the front surface to the driver chip on the reverse surface, such that the entire viewing surface area may be optically active.

(13) In another aspect, this invention provides for an electro-optic display having a backplane with two major surfaces wherein a first major surface has a plurality of pixel electrodes, and a second major surface opposed to the first major surface has at least one driver chip, a plurality of gate lines with a conductive via for each gate line, a plurality of source lines with a conductive via for each source line, a plurality of common lines with at least one conductive via to electrically connect the plurality of pixel electrodes to the driver chip, such that the entire viewing surface area may be optically active.

(14) In another aspect, this invention provides for an electro-optic assembly containing a backplane having a plurality of pixel electrodes on the front surface, at least one driver on the reverse surface and electrical connections between the pixel electrodes and the driver, such that almost 100% of the viewing surface may be optically active.

(15) The term backplane is used herein consistent with its conventional meaning in the art of electro-optic displays and in the aforementioned patents and published applications, to mean a rigid or flexible material provided with one or more electrodes. The backplane may also be provided with electronics for addressing the display, or such electronics may be provided in a unit separate from the backplane. A backplane may contain multiple layers. A backplane may be referred to as a rear electrode structure. The front surface of a backplane refers to the surface closest to the front electrode of the display. The reverse surface of a backplane refers to the surface farthest from the front electrode.

(16) The term viewing surface is used herein consistent with its conventional meaning in the art of electro-optic displays and in the aforementioned patents and published applications, to mean the surface closest to the front electrode (the surface remote from the backplane).

(17) The term non-viewing surface is used herein to mean any surface or side that is not the viewing surface. This includes the reverse side of a backplane, the sides of a backplane and, if multi-layered, any layer of the backplane that is not on the viewing surface.

(18) Typically, a backplane has an array of pixel electrodes. Each pixel electrode forms part of a pixel unit which usually also includes a thin-film transistor, a storage capacitor, and conductors that electrically connect each pixel unit to a driver chip. Although a pixel electrode is technically a subpart of a pixel unit, the terms pixel and pixel electrode are commonly used interchangeably and refer to a unit cell of a backplane active area. The terms column lines and row lines generally refer to the gate lines and source lines of a pixel transistor. These terms are used interchangeably herein.

(19) FIG. 1 is an illustrative schematic of the circuitry of a type of single thin film transistor pixel (100), including a pixel electrode (105), a capacitor electrode (104), a thin-film transistor (106), a gate line (103), a source line (101) and a common (ground) line (102). The source line (101) is connected to the source of the transistor (106), the gate line (103) is connected to the gate of the transistor (106) and the drain of the transistor (106) is connected to the pixel electrode (105). The capacitor electrode (104) is connected to the ground line (102) so that the pixel electrode (105) and the capacitor electrode (104) together form a storage capacitor (107).

(20) FIG. 2 is an illustrative schematic of the present invention of a single pixel including a pixel electrode (105), a capacitor electrode (104), a thin-film transistor (106), a gate line (103), a source line (101) and a common (ground) line (102). Conductive vias at each gate line (201) and at each source line (200) electrically connect the pixel electrode to the driver on the reverse surface of the backplane. A conductive via (203) connects the ground lines (102) to the driver on the reverse surface.

(21) The thin-film transistor of the pixel electrode may be electrically connected to the driver chip by formation of via apertures through the backplane. The apertures may be filled with conductive material to form vias interconnecting electronic components on the viewing side to electronic components on the reverse side of the backplane. The via apertures may be, for example, etched, punched, drilled or laser-drilled through the polymeric material of the backplane so as to connect the electronic components on the viewing side to the drivers on the reverse side. The via apertures may be filled using a variety of materials and techniques including printing (for example, ink-jet, screen, or offset printing) application of conductive resins, shadow-mask evaporation or conventional photolithographic methods. Simple electrical connections may be made along the edge of the substrate using thick film conductors.

(22) FIG. 3 is an illustrative schematic of a 55 array of pixels of a backplane of the present invention which includes pixel electrodes (105), capacitor electrodes (104), thin-film transistors (106), gate lines (103), source lines (101), common (ground) lines (102), source line conductive vias (200), gate line conductive vias (201) and a common line conductive via (203). The pixel components are layered or sandwiched between semiconductor layers to provide electrical connections and prevent cross-talk between neighboring components. The pixel electrode, usually, is on the front surface of the backplane and is the closest layer to the viewing surface. The electro-optic layer attaches to the pixel electrode layer such that, essentially, the entire viewing surface is optically active. The pixel electrode layer may be light transmissive when the electro-optic layer acts to mask the underlying components on the backplane.

(23) The array of transistors shown in FIG. 3 can be manufactured using any one of many appropriate methods. For example, vacuum based methods such as evaporation or sputtering can be used to deposit the materials necessary to form the transistor and thereafter the deposited material can be patterned. Alternatively, wet printing methods or transfer methods can be used to deposit the materials necessary to form the transistors. For fabrication of thin-film transistors, the substrate may be, for example: a silicon wafer; a glass plate; a steel foil; or a plastic sheet. The gate electrodes, for example, may be any conductive material such as metal or conductive polymer. The materials for use as the semiconductor layer, for example, can be inorganic materials such as amorphous silicon or polysilicon. Alternatively, the semiconductor layer may be formed of organic semiconductors such as: polythiophene and its derivatives; oligothiophenes; and pentacene. In general, any semiconductive material useful in creating conventional thin film transistors can be used in this embodiment. The material for the gate dielectric layer may be an organic or an inorganic material. Examples of suitable materials include, but are not limited to, polyimides, silicon dioxide, and a variety of inorganic coatings and glasses. The source and gate electrodes may be made of any conductive material such as metal or conductive polymer.

(24) The array of transistors described in reference to FIG. 3 may be any type of transistors used for addressing an electronic display. Additional (i.e., resistors) or alternative (i.e., capacitors and transistors) drive components may be used as well. In another implementation, the addressing electronic backplane could incorporate diodes as the nonlinear element, rather than transistors. The present invention is applicable to a variety of electronic displays, including electrophoretic displays, liquid crystal displays, emissive displays (including organic light emitting materials) and rotating ball displays.

(25) Alternatively, a passive matrix backplane rather than an active matrix backplane may be used to drive the display. As is well-known in the art, a passive matrix backplane uses two sets of elongate electrodes extending at right angles to display an image on the screen. Each pixel is defined by the intersection of two electrodes, one from each set. By altering the electrical charge at a given intersection, the electro-optic properties of the corresponding pixel may be changed.

(26) FIG. 4 is an illustrative schematic of a reverse surface of a backplane of the present invention showing a driver (400), conductive vias (200, 201, 203) and conductors (401, 402) connecting the pixels in a 55 array on the front surface to the driver on the reverse surface. FIG. 4 shows the conductive vias located at the end of each column and row according to the preferred embodiment, however, the vias may be located anywhere along the gate and source lines to make the electrical connection.

(27) FIG. 4 illustrates a plan view of the conductive leads and the elements for an array of transistors for driving a display. An array comprises source lines and gate lines with conductive vias connecting a driver to pixel electrodes. To address a pixel electrode, voltages are applied to appropriate source lines and gate lines. Changes in the optical characteristics of a display element are achieved by addressing a pixel electrode that is associated with the display element.

(28) From the foregoing, it will be seen that the present invention provides for an electro-optic assembly containing a backplane having a plurality of pixels arranged in rows and columns on the front surface, at least one driver on the reverse surface and electrical connections between the row and column lines of the pixel array and the driver, such that 100% of the viewing surface may be optically active.

(29) Display size and resolution may be optimized according to the electro-optic display application, substrate materials and PCB design guidelines. Pixel size may vary from approximately 100 m to more than 10 mm per side (approximately 10,000 m.sup.2 to 100 mm.sup.2). Conductive vias may range in size from 25 m to 250 m depending on the pixel size of the display. Individual display sizes may range from as large as multiple feet squared to as small as less than an inch squared. For large scale displays with a large viewing distance, a larger pixel size is preferred. For example, a billboard display may be constructed from individual displays of approximately 400 mm400 mm with 4 mm4 mm pixels and conductive vias that are approximately 250 m. For large scale displays with a shorter viewing distance, a smaller pixel size is preferred. For example, a wall display may be constructed from individual displays of approximately 200 mm200 mm with 200 m200 m pixels.

(30) The number of driver chips may be optimized according to design rules. At least one driver chip may be used. Preferably, at least two driver chips are used; one to drive the gate lines and one to drive the source lines.

(31) FIG. 5 is an illustrative schematic of the present invention showing two drivers (500, 501), conductive vias to the source lines (200) and gate lines (201), a conductive via to the common lines (203) and conductors (401, 402) connecting the pixels in a 55 array on the front surface to the driver on the reverse surface. One driver (500) addresses the source lines and the other driver (501) addresses the gate lines and common lines.

(32) In one aspect of the present invention, a thin-film transistor, capacitor electrode and pixel electrode may be fabricated on the front surface of the backplane while a driver and connecting gate and source lines (and any additional electronic components) are formed on the opposed surface, then the via apertures are formed, and finally the via apertures are filled to form vias. Vias may be filled with a conductive substance, such as solder or conductive epoxy, or an insulating substance, such as epoxy. Alternatively, the gate and source lines may be formed on the front surface of the backplane. In another alternative, the substrate may be drilled and filled to form vias, then, the thin film transistor array is formed with the source and gate lines landing on (aligning with) the conductive vias.

(33) In another alternative, the backplane may be formed by printing the source lines, gates lines and thin film transistors on a substrate, then, drilling an filling conductive vias, then, covering the vias with dialectric and, finally, printing the pixel electrodes.

(34) The backplane substrate material may be any suitable material that allows for the fabrication of one or more via apertures, such as polyester, polyimide, multilayered fiberglass, stainless steel, PET or glass. Holes are punched, drilled, abraded, or melted through where conductive paths are desired, including through any dielectric layers as necessary. Alternatively, the apertures may be formed on the backplane materials prior to assembly and then aligned when assembled. A conductive ink may be used to fabricate and fill the holes. The pixel electrode may be printed using a conductive ink as is known in the art. The ink viscosity, as well as the aperture size and placement, may be optimized so that the ink fills the apertures. When the reverse surface structures are printed, again using conductive ink, the holes are again filled. By this method, the connection between the front and back of the substrate may be made automatically.

(35) The backplane of the display may comprise a substrate having a thin-film transistor array on the front surface, conductive vias located at each column and row, a driver on the reverse surface of the substrate, and gate and source lines connecting the thin-film transistor array to the driver.

(36) Alternatively, a printed circuit board may be used as the rear electrode structure. The front of the printed circuit board may have copper pads etched in the desired shape. The plated vias connect the electrode pads to an etched wire structure (or conductor) on the reverse surface of the printed circuit board. The wires may be run to the reverse surface rear of the printed circuit board and a connection can be made using a standard connector such as a surface mount connector or using a flex connector and anisotropic glue.

(37) Alternatively, a flex circuit such a copper-clad polyimide may be used for the rear electrode structure. Printed circuit board may be made of polyimide, which acts both as the flex connector and as the substrate for the electrode structure. Rather than copper pads, electrodes may be etched into the copper covering the polyimide printed circuit board. The plated through vias connect the electrodes etched onto the substrate the rear of the printed circuit board, which may have an etched conductor network thereon (the etched conductor network is similar to the etched wire structure).

(38) Alternatively, the rear electrode structure can be made entirely of printed layers. A conductive layer can be printed onto the back of a display comprised of a clear, front electrode and a printable display material. A clear electrode may be fabricated from indium tin oxide or conductive polymers such as polyanilines and polythiophenes. A dielectric coating may be printed leaving areas for vias. Then, the back layer of conductive ink may be printed. If necessary, an additional layer of conductive ink can be used before the final ink structure is printed to fill in the holes.

(39) This technique for printing displays can be used to build the rear electrode structure on a display or to construct two separate layers that are laminated together to form the display. For example an electronically active ink may be printed on an indium tin oxide electrode. Separately, a rear electrode structure as described above can be printed on a suitable substrate, such as plastic, polymer films, or glass. The electrode structure and the display element can be laminated to form a display.

(40) Moreover, the encapsulated electrophoretic display is highly compatible with flexible substrates. This enables high-resolution thin-film transistor displays in which the transistors are deposited on flexible substrates like flexible glass, plastics, or metal foils. The flexible substrate used with any type of thin film transistor or other nonlinear element need not be a single sheet of glass, plastic, metal foil, though. Instead, it could be constructed of paper. Alternatively, it could be constructed of a woven material. Alternatively, it could be a composite or layered combination of these materials.

(41) FIG. 6 is an illustrative representation of the present invention used in a large scale sign. The individual electro-optic displays (600) are tiled in a 5 by 4 array. The dotted lines (601) represent the edges of the individual displays. This figure shows a sign for a train station that displays icons and words (602) indicating the direction to the trains.

(42) The electro-optic display may have a front plane comprising, in order beginning from the backplane, a layer of electro-optic material disposed on the thin-film transistor array, a single continuous electrode disposed on the electro-optic material and, optionally, a front protective layer or other barrier layers. The upper surface of the protective layer forms the viewing surface of the display. An edge seal may extend around the periphery of the electro-optic material to prevent the ingress of moisture to the electro-optic material.

(43) In another aspect, this invention provides for an electro-optic display wherein the electro-optic material masks the electrical connections such that the viewing surface may be completely optically-active. The electro-optic material of the front plane laminate may overlay the pixel electrodes to obscure the backplane connections from the viewing surface. In another aspect, the electro-optic material of the front plane laminate may extend beyond the pixel electrodes to obscure the backplane connections from the viewing surface.

(44) In another aspect, as described in U.S. Pat. No. 8,705,164, front electrode connections may be on a non-viewing side of the backplane. Alternatively, front electrode connections may be made on the viewing surface. Such connections create non-active areas on the viewing surface. These non-active areas are usually approximately 2 mm in diameter but may be larger or smaller depending on the display voltage requirements and the total number of connections. In comparison to the overall active viewing area, the display may still appear to be 100% active. In the present invention, an active viewing area of at least 95% is preferred.

(45) Furthermore, the subject matter presented herein provides for a backplane for use in an electro-optic display, this backplane, in some embodiments, may include a pixel conductor layer, a substrate layer and a reverse side conductor layer, where the substrate layer can be positioned between the pixel conductor layer and the reverse side conductor layer. Driving electrodes for display pixels or pixel segments can be defined and fabricated on the pixel conductor layer. In a preferred embodiment, the driving electrodes are firstly patterned on the pixel conductor layer using a beam of energy or particles (e.g., laser scribing), where laser scribing allows for the fabrication of driving electrodes of various sizes and geometric shapes without using complex machineries. Subsequently, vias can be created through the substrate layer and conductive traces can be drawn on the reverse side conductor layer, where the conductive traces are used for transmitting electrical voltage or driving waveforms to the driving electrodes through the vias. In this fashion, the backplane is assembled without having to use size-limiting techniques such as photolithography or global alignments, techniques usually required by screen printing or PCB manufacturing. As such, large sized backplanes with variable sized driving electrodes can be conveniently and cheaply assembled.

(46) In some instances, unique display applications will require a display to use pixel or pixel segments of irregular geometric shapes. The present invention enables the assembly of a backplane for accommodating an electro-optic display with a plurality of irregular shaped display pixel segments at a cheap price. FIG. 8 illustrates a pixel conductor layer 800 for a backplane for driving an electro-optic display with a plurality of irregular shaped pixel segments. As illustrated in FIG. 8, the pixel conductor layer 800 may include a plurality of variable sized driving electrodes 811-817 for driving the plurality of irregular shaped pixel segments (not shown), where the shapes and positions of the driving electrodes 811-817 will match the shapes and positions of the corresponding pixel segments. In some embodiments, the pixel conductor layer 800 may be formed by coating a continuous layer of conducting material such as ITO onto a substrate. Other conductive materials may also be sputtered onto a substrate form the continuous layer, materials such as, but not limited to, various types of conductive oxides, gold, inert metals, nickel boron, carbon, carbon nanotubes, graphene, and poly(3,4-ethylenedioxythiophene) or also known as PEDOT. In some other embodiments, conductive material such as copper, nickel, aluminum, silver nanowires and printed silver may also be used depending on the specific requirements of the display application.

(47) In an exemplary backplane assembling process in accordance with the subject matter presented herein, this continuous layer of conductive material may be scribed by a laser to pattern the various shaped driving electrodes 811-817. The scribing may cut deep enough into the conductive material layer to electrically isolate each driving electrodes but not so deep as to cut through the underneath substrate or substantially weaken the substrate to make it fragile. Laser scribing allows for the patterning of driving electrodes of various geometrical configurations without having to do photolithography or global alignments, which can be both expensive and prohibitively expensive for large sized backplanes. FIG. 8 illustrates star shaped 820 and circular 822 driving electrodes, but it should be appreciated that other geometrical shapes can be easily patterned using laser scribing or other comparable etching methods commonly adopted in the industry.

(48) Once the driving electrodes have been patterned, vias can be created through the substrate to connect the driving electrodes to driver circuits (not shown). FIG. 9 illustrates an exemplary substrate 900 in accordance with the subject matter presented herein. In some embodiments, the substrate 900 may be manufactured using materials such as PET, Polyethylene naphthalate (PEN), cyclic olefins, paper, fabrics, polyimide, or polycarbonate. To provide electrical connections to the driving electrodes 811-817 as shown in FIG. 8, one or more vias 921-927 may be created through the substrate 900 for each of the driving electrodes 811-817. Vias 921-927 may be created by cutting through the substrate 900 using lasers, but it should be appreciated that mechanical drilling or other puncturing methods commonly used in the art can be easily adopted. In some embodiments, a via cut into a driving electrode may be at least 200 m in diameter and usually no more than 3 mm to minimize the appearance of the hole in the final display. It should appreciated that in other embodiments, vias may be formed before the driving electrodes have been patterned, for example, a substrate may come pre-fabricated with vias in place configured to backplane assembling.

(49) After the vias 921-927 are created, conductive material (not shown) may be dispensed into the vias 921-927 with a porous paper behind the substrate and with vacuum pulling on the porous paper. The vacuum force will pull the conductive material through the vias 921-927 and plates the sides of the vias 921-927 or fill the volume of the vias 921-927, connecting the driving electrodes 811-817 to the reverse side of the substrate 900. It is preferred that the finished vias have surfaces co-planar with both the pixel conductor layer and the reverse side conductor layer to avoid bumps resulting from too much filler or lamination void due to insufficient via filling. In some embodiments, the vias 921-927 may be filled with a hot melt adhesive with a melting temperature around the lamination temperature of the electrophoretic ink material (e.g., 250F), provided that the flow viscosity of the hot melt adhesive is low enough to prevent ink capsule rupture.

(50) The properly filled vias 921-927 can provide electrical connections between the driving electrodes 811-817 and the conductive traces that are to be formed on the reverse side (i.e., the side opposite to the pixel conductor layer) of the substrate 900. Prior to the formation of the conductive traces, in some embodiments, an ink FPL stack (not shown) may be firstly laminated to the driving electrodes 811-817. This is done in this fashion such that the thickness of the traces would not press through the substrate 900 and make impressions on the FPL layer during lamination.

(51) The subsequent formation of the conductive traces may be carried out in various fashions. In some embodiments, conductive traces may be printed onto the reverse side beginning at the vias and extend according to a pre-determined layout for routing all of the lines from the pixel locations, without crossing, to one condensed area that matches the pad pitch for the electronics to be attached to the device. The printing of the conductive traces may be accomplished manually for small numbers of backplane units, or alternatively, an XY plotting machine with controlled dispensing of printable conductive material may be used. Camera vision alignment may be adopted to locate the vias and a XY plotter may be aligned to that location to start drawing the conductive traces. It should be appreciated that other trace producing methods commonly used in the industry can be conveniently adopted, methods such as, but not limited to, inkjet with conductive inks, rollers, tapes, etc. Some examples of suitable trace materials are silver or carbon filled printing inks. In this fashion, no global alignment may be required to create the conductive traces. For example, local alignment may be perfectly sufficient to places the traces to connect the vias to a driver circuit. By not having to perform global alignments, large sized (e.g., backplanes larger than 24 inches by 48 inches in sizes) backplanes can be conveniently assembled because global alignments can be hard to design for and expensive to perform.

(52) Alternatively, conductive traces may be etched or scribed onto a continuous conductive layer, similar to the patterning of the driving electrodes 811-817 mentioned above. In some embodiments, a continuous layer of conductive material may be coated on the reverse side of the substrate 900. After the FPL stack has been laminated onto the driving electrodes 811-817, conductive traces may be etched into the continuous conductive layer with a laser such that each conductive trace is electrically isolated but not cutting into the substrate enough to cut through or make it fragile. FIG. 10 illustrates an exemplary reverse side 1000 of the substrate 900 presented in FIG. 9 with conductive traces 1001-1007 etched into a continuous conductive layer in accordance with the subject matter presented herein. As illustrated, the cutting of each conductive trace can include the via for the driving electrode and a small circle around the via adding the width of the conductive trace around each via to ensure continuity to that driving electrode. The alignment to each via may be accomplished with a camera vision alignment system to find and align to each via to locate the conductive trace path. The conductive traces 1001-1007 can extend in a pre-determined layout for routing all of the lines from the pixel locations, without crossing, to one condensed area that matches the pad pitch for the electronics to be attached to the device.

(53) For conductive fabric designs, it may be convenient to firstly produce patterns for the driving electrodes and the conductive traces, then paste them onto a substrate which could be a fabric or film depending on the requirements of the display application. Other suitable substrate material include PET, Polyethylene naphthalate (PEN), cyclic olefins, paper, fabrics, polyimide, or polycarbonate, etc.

(54) In general, variations can be made to the backplane assembly processes described above while still producing backplanes that are substantially comparable in performances. For example, roll to roll machines may be used to assemble backplanes that are in accordance with the subject matter presented herein. In some embodiments, continuous rolls of substrate coated with conductive materials can be processed at multiple assembling stations including a laser cutting/etching station and a XY plotting station, both equipped with camera vision alignment systems. These two stations may be distinct units or may be part of a single assembly station (e.g., both the laser cutter and the plotter can be part of an XY gantry system). Furthermore, a roll to roll machine may further include a station for heated lamination of ink FPL or other materials for assembling display units. This arrangement can be advantageous for at least the reason that the conductive traces can now be radiation cured (e.g., UV cured) at the roll to roll machine, which saves production time and cost by not having to use conventional heat drying ovens.

(55) In another embodiment, vias can be cut in a substrate roll prior to the deposition of conductive materials, which permits the filling of the vias using the deposited conductive material. In this fashion, a separate assembling step to fill the vias may be eliminated, further reducing production cost.

(56) In yet another embodiment, vias may be left unfilled prior to the lamination of the FPL to a display stack. The subsequent dispensing of the conductive traces to the reverse side of the substrate can in effect fulfill the vias to provide connection between the driving electrodes and the conductive traces.

(57) From the foregoing, it will be seen that the present invention can provide processes for assemble large sized backplanes for electro-optic displays conveniently and cheaply. Because the backplanes can be assembled using laser scribing and local alignments, there is no need for otherwise expensive machineries to accommodate the large size requirement and the irregular driving electrode shapes.

(58) It will be apparent to those skilled in the art that numerous changes and modifications can be made in the specific embodiments of the invention described above without departing from the scope of the invention. Accordingly, the whole of the foregoing description is to be interpreted in an illustrative and not in a limitative sense.