Sensing Device for Sensing Minor Charge Variations

Abstract

The present invention relates to a charge sensing device for sensing charge variations in a charge storage area including: a TFET having at least one sense gate; a capacitive coupling for coupling the charge storage area with the sense gate.

Claims

1. A charge sensing device for sensing charge variations in a charge storage area including: a TFET having at least one sense gate; a capacitive coupling for coupling the charge storage area with the sense gate.

2. The charge sensing device according to claim 1, wherein a measurement unit is included which is configured to apply an electrical quantity, in particular a drain to source voltage, to the TFET and measure resulting electrical characteristics, in particular a drain source current.

3. The charge sensing device according to claim 1, wherein the TFET has a source region and a drain region which sandwich an intrinsic channel region, wherein the source region is an n+region and wherein the drain region is a p+region.

4. The charge sensing device according to claim 3, wherein a junction between the source region and the channel region is formed as a heterojunction, particularly including silicon, IV and III-V semiconductors, and/or wherein the junction between the drain region and the channel region is formed as a homojunction, particularly including silicon.

5. The charge sensing device according to claim 4, wherein the channel region of the TFET is capacitively coupled with the sense gate and with a biasing gate separate therefrom, particularly opposing each other with respect to the channel region.

6. The charge sensing device according to claim 5, wherein the sense gate is shorter than the biasing gate with respect to a length of the channel region between the source region and the drain region, wherein particularly the sense area is coupled to a junction between the source region and the channel region.

7. The charge sensing device according to claim 6, wherein a/the measurement unit is configured to apply a predetermined biasing voltage to the biasing gate.

8. The charge sensing device according to claim 2, wherein the TFET has a source region and a drain region which sandwich an intrinsic channel region, wherein the source region is an n+region and wherein the drain region is a p+region.

9. The charge sensing device according to claim 8, wherein a junction between the source region and the channel region is formed as a heterojunction, particularly including silicon, IV and III-V semiconductors, and/or wherein the junction between the drain region and the channel region is formed as a homojunction, particularly including silicon.

10. The charge sensing device according to claim 9, wherein the channel region of the TFET is capacitively coupled with the sense gate and with a biasing gate separate therefrom, particularly opposing each other with respect to the channel region.

11. The charge sensing device according to claim 10, wherein the sense gate is shorter than the biasing gate with respect to a length of the channel region between the source region and the drain region, wherein particularly the sense area is coupled to a junction between the source region and the channel region.

12. The charge sensing device according to claim 11, wherein a/the measurement unit is configured to apply a predetermined biasing voltage to the biasing gate.

13. The charge sensing device according to claims 1, further comprising a charge storage area, such as a quantum dot or an SET structure, so that a charge variation of the charge storage area causes an electrostatic potential of an intrinsic channel region to variate.

14. A method for operating a charge sensing device according to claim 10, wherein a drain to source voltage is applied on the TFET, wherein a biasing voltage is applied on the biasing gate and wherein characteristics of an electrical quantity, in particular characteristics of a drain source current, are measured to detect a charge variation of the charge storage area.

15. Method according to claim 14, wherein the biasing voltage is set to a value so that the sensitivity of the charge sensing device is maximized.

16. A use of a TFET in a charge sensing device for sensing a charge variation of a charge storage area, wherein the charge storage area is capacitively coupled with a sense gate of the TFET, so that a charge variation of the charge storage area causes an electrostatic potential of an intrinsic channel region to variate.

17. Method for fabricating a charge sensing device according to claim 1, wherein the charge sensing device is formed on a silicon-on-insulator substrate, wherein a source region is formed by an underetching and deposition process of a IV or III-V semiconductor material.

18. Method according to claim 17, wherein a sense gate and a biasing gate are formed wherein the sense gate is shorter than the biasing gate with respect to a length of the channel region between a source region and a drain region, wherein particularly the sense area is coupled to a junction between the source region and the channel region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments are described in more detail in conjunction with the accompanying drawings in which:

[0036] FIG. 1 shows a schematic diagram for illustrating a circuitry with a charge sensing device for sensing a change in charge in a charge storage area;

[0037] FIG. 2 schematically shows the structure of a charge-sensing device;

[0038] FIG. 3 schematically shows the structure of a further charge-sensing device with a high sensitivity;

[0039] FIGS. 4a and 4b show diagrams for illustrating the characteristics of a drain current vs. a gate voltage and characteristics of the subthreshold swing vs. the drain current;

[0040] FIGS. 5a to 5b show diagrams for illustrating a threshold voltage shift for different injected charges in different TFET structures of the charge sensing device;

[0041] FIGS. 6a to 6c show diagrams for illustrating transfer characteristics for the TFET for different temperatures; and

[0042] FIGS. 7a to 7l show steps of a process flow sketch for fabricating a TFET sensing device of the sensing device of FIG. 3.

DETAILED DESCRIPTION OF EMBODIMENTS

[0043] FIG. 1 schematically shows a read-out circuitry 1 for a charge storage with a charge storage area 2, which can e.g. be formed with an SET-like structure wherein the charge storage area 2 is capacitively coupled by means of the capacitive coupling element 3 with a sense gate of a TFET 4. The TFET 4 is part of a sensing device 3 according to the present invention. Furthermore, a measurement unit 5 is electrically connected with the TFET 4 to perform the reading out of an electrical quantity.

[0044] The TFET 4 further has a source terminal 4S and a drain terminal 4D above which a predetermined drain to source voltage VDS is applied by the measurement unit 5. Moreover, the measurement unit 5 is configured to detect the current flow. Changes of the current flow through the TFET 4 represent a change in charge causing a potential change of the sense gate of the TFET 4.

[0045] In FIG. 2, the structure of the TFET which is included in the sensing device is illustrated. In general, a TFET has a similar structure as a metal-oxide-semiconductor field-effect transistor, whereas the fundamental switching mechanism differs. TFETs characteristic is governed by modulating quantum tunneling through a barrier instead of modulating thermionic emission over a barrier as in traditional MOSFETs. Because of this, TFETs are not limited by the thermal Maxwell-Boltzmann tail of carriers, which limits MOSFET drain current subthreshold swing to about 60 mV/decade of current at room temperature. The subthreshold swing is proportional to the transistor speed so that with lower subthreshold swing the operating frequency of the TFET can be increased.

[0046] A TFET generally has a P-I-N (p-type, intrinsic, n-type) junction structure, in which the electrostatic potential of an intrinsic channel region is controlled by a gate terminal. The TFET 4 has an n+source region 41 which may be formed of Ge and a p+drain region 42 between which an intrinsic channel region 43 is formed. On opposite sides across the channel region 43, a sense gate oxide 44 and a biasing gate oxide 45 are provided which separate a sense gate electrode 46 and a biasing gate electrode 47 from the channel region 43, respectively. Both gates 46, 47 are used to control the electrostatic potential of the intrinsic channel region 43.

[0047] The TFET 4 is operated by applying a gate potential so that electron accumulation occurs in the intrinsic channel region 43. At sufficient gate potential, band-to-band tunneling (BTBT) occurs when the conduction band of the intrinsic channel region 43 aligns with the valence band of the P region. Electrons from the valence band of the p-type drain region tunnel into the conduction band of the intrinsic channel region 43 and current can flow across a drain-source path. As the gate bias is reduced, the bands become misaligned and current can no longer flow.

[0048] As very little charges, in a range of single or few elementary charges, shall be detected gates are separated in sense gate 44, 46 and biasing gate 45, 47. The biasing gate 45, 47 is controlled by the measurement unit 5 and a sufficient biasing gate potential (biasing voltage) is applied to ensure BTBT. So, the control of the biasing gate 45, 47 is used to bias the TFET 4 to provide the best sensitivity.

[0049] The shown TFET 4 may have following device characteristics, such as channel thickness 10 nm, biasing gate oxide thickness 2.5 nm, a sense guide oxide thickness 2.5 nm, device width 10 nm, source/drain doping 10.sup.20 cm.sup.3, channel length 50 nm.

[0050] FIG. 3 shows a preferred embodiment which differs from the embodiment of FIG. 2 in that the configuration of the sense gate 44, 46 is made smaller. The sense gate oxide 44 is only present around the tunneling junction between the source region and the channel region 43 not covering the full length L.sub.channel of the channel region 43. In other words, the shortened sense gate extends from the junction with a reduced length over the channel region. For the above configuration the length L.sub.sense of the sense gate 44, 46 can be between 5 to 30 nm, preferably between 5% and 50% of the length L.sub.channel of the channel region. By means of the shortened sense gate 44, 46 the electrical field caused by the charged sense gate 44, 46 can thereby be focused toward the tunneling junction which allows increasing the sensitivity of the charge sensing device 3.

[0051] With respect to FIGS. 4a and 4b, it is shown a transfer characteristics for different injected charges into a sense gate 44 ,46 while sweeping the biasing voltage VGs. It is observed a shift in proportion to the injected charges. For the exemplary TFET which is characterized by the diagrams of FIGS. 4 to 7, a subthermal subthreshold swing is up to about I.sub.D=10.sup.11 A. Moreover, the subthreshold swing behavior remains the same for up to 20 electrons. For larger values, the floating gate voltage induced by the gate becomes large enough such that the voltage drop across the tunneling junction becomes pinned due to inversion layer formation beneath the sense gate 44, 46 screening the field effect of the tunneling region.

[0052] In FIG. 5a, the threshold voltage shift V.sub.TH induced by the injected charges into the sense gate 44, 46 is shown. The threshold voltage shift V.sub.TH is defined as gate voltage applied when I.sub.D=10.sup.11 A. It can be seen that the embodiment as illustrated in FIG. 3 is more than twice time sensitive to charges than the TFET structure of FIG. 2. The reduced sense gate 44, 46 length (L.sub.sense) further provides a smaller capacitance which increases the electric field underneath the sense gate 44, 46 and causing it to reach inversion formation for a smaller amount of charge. This reduces sensitivity when the number of electrons is increased above about 20 electrons as can be seen in the diagram of FIG. 5b.

[0053] FIGS. 6a, 6b and 6c show the above diagrams in terms of the temperature dependency. It can be seen that one ideal property of TFETs is the relative insensitivity of the on-current and the subthreshold swing due to temperature variations. FIGS. 6a and 6b show the transfer characteristics of the TFET 4 for different temperatures which indicate an expected decrease of the SRH recombination (Shockley-Read-Hall recombination) current with decreasing temperature. FIG. 6c shows the threshold voltage shift AVTH for different temperatures between 200 K and 300 K. It can be clearly seen the minimal difference between the shifts for the temperature.

[0054] FIGS. 7a to 7l briefly show the process steps for fabrication of the sensing device according to FIG. 3. In step of FIG. 7a, a silicon on insulator substrate 100 is provided. The silicon on insulator substrate 100 has a silicon layer 101 thereon to be processed further.

[0055] In step of FIG. 7b, on the surface of the silicon layer 101, a sacrificial oxide 102 is deposited which forms a mask for defining the area of the sensing device to be produced.

[0056] In step of FIG. 7c, by means of an anisotropic etching, the silicon layer 102 is removed in areas not covered by the sacrificial oxide 102 so that only a silicon area remains which defines the TFET structure of the sensing device to be produced.

[0057] In step of FIG. 7d, an implant hard mask 103 is provided on a part of the TFET structure area which defines an area to form the drain region of the TFET.

[0058] In step of FIG. 7e, by means of an implantation process, the drain region 105 is formed as an implant process, the implant hard mask 103 for defining the drain region 105 is removed.

[0059] In step of FIG. 7f, a further implant hard mask 106 for defining the source region is deposited.

[0060] In step of FIG. 7g, under the remaining sacrificial oxide 102 an anisotropic etching of the silicon is performed so that a cavity 107 between the insulator of the substrate 100 and the sacrificial oxide 102 is formed.

[0061] In step of FIG. 7h, the cavity 107 is filled with in situ doped Ge by means of an appropriate deposition or growth process.

[0062] In step of FIG. 7i, the further implant hard mask for defining the source region is removed.

[0063] In step of FIG. 7j, the so formed structure is covered by a high K oxide 109 so that the surface and the side etches are covered by the high K oxide and thereafter a gate metal layer 110 is applied thereon.

[0064] In step of FIG. 7k, the top layer of the structure is removed, and also the oxide and metal applied on the edges of the source and drain regions are removed by etching.

[0065] In step of FIG. 7l, a top-down view onto the sensing device is shown.

[0066] It remains the oxide and gate metal at the side edges of the remaining silicon layer which form opposing sense and biasing gate electrodes of the sensing device which are laterally arranged. By means of an appropriate masking, the sense gate electrode can be formed smaller and substantially arranged close to the source-channel junction to provide a better sensitivity as described with respect to FIG. 3.