INTEGRATED CHIP SCALE PACKAGES

Abstract

Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.

Claims

1. A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack.

2. (canceled)

3. A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub.

4. The chip scale package according to claim 1, wherein the dielectric support comprises a second portion embedded in the carrier at the passageway.

5. The chip scale package according to claim 1, wherein the dielectric support comprises an annular disk.

6. The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub.

7. The chip scale package according to claim 1, comprising a chip disposed therein electrically connected to the stub.

8. The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub by a wirebond.

9. The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub by a solder bump.

10. A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising a coaxial connector mounted thereto, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection.

11. The chip scale package according to claim 1, wherein the continuous stacks of the carrier and conductive stub comprise metal.

12. The chip scale package according to claim 1, comprising a lid hermetically sealed thereto to hermetically seal the chip in the carrier.

13. The chip scale package according to claim 1, comprising a plurality of passageways extending between the exterior and interior of the carrier, the passageways each having a respective conductive stub extending therethrough, each stub suspended in the respective passageway by a dielectric support, each stub and respective support cooperating to create a hermetic seal at the respective passageway between the exterior and interior of the carrier.

14. The chip scale package according to claim 1, wherein the passageway comprises a plurality of conductive stubs disposed therein, each stub hermetically sealed in the passageway.

15. A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack.

16. The method according to claim 15, comprising electrically connecting an electronic chip to the stub within the interior of the carrier.

17. The method according to claim 16, comprising hermetically sealing a lid onto the carrier to hermetically seal the chip in the carrier.

18. A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub.

19. The method according to claim 15, wherein the dielectric support comprises a second portion embedded in the carrier at the passageway.

20. The method according to claim 15, wherein the dielectric support comprises an annular disk.

21. The method according to claim 16, wherein the electronic chip is electrically connected to the stub by a wirebond.

22. The method according to claim 16, wherein the electronic chip is electrically connected to the stub by a solder bump.

23. A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising mounting a coaxial connector to the carrier, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection.

24. The method according to claim 15, wherein the continuous stacks of the carrier and conductive stub comprise metal.

25. The method according to claim 15, wherein the carrier comprises a plurality of passageways extending between the exterior and interior of the carrier, the passageways each having a respective conductive stub extending therethrough, each stub suspended in the respective passageway by a dielectric support, each stub and respective support cooperating to create a hermetic seal at the respective passageway between the exterior and interior of the carrier.

26. The method according to claim 15, wherein the passageway comprises a plurality of conductive stubs disposed therein, each stub hermetically sealed in the passageway.

27. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The foregoing summary and the following detailed description of exemplary embodiments of the present invention may be further understood when read in conjunction with the appended drawings, in which:

[0008] FIG. 1A schematically illustrates an isometric cut-away view of exemplary chip level packaging in accordance with the present invention;

[0009] FIG. 1B schematically illustrates a top of the package of FIG. 1A with the lid removed;

[0010] FIG. 1C schematically illustrates a side elevational view of the package of FIG. 1A;

[0011] FIG. 1D schematically illustrates an enlarged view of the center conductor aperture region of the package of FIG. 1A;

[0012] FIG. 1E schematically illustrates an enlarged view of the center conductor via region similar to that of the package of FIG. 1A but having multiple conductive stubs;

[0013] FIG. 2 schematically illustrates a fragmentary side view of the lower portion of the package of FIG. 1A with an exemplary electrical connection (solder ball) of a chip to the package center conductor;

[0014] FIG. 3 schematically illustrates a fragmentary side cross-sectional view of an exemplary device structure in accordance with the present invention showing multiple vias having dielectric collars to provide a hermetic seal;

[0015] FIG. 4 illustrates the simulated insertion loss and return loss of from the package into the chip for a package as configured in FIG. 1; and

[0016] FIG. 5 schematically illustrates a side elevation cross-sectional view of the package of FIG. 2 showing transition from circular LAN pads.

DETAILED DESCRIPTION OF THE INVENTION

[0017] Referring now to the figures, wherein like elements are numbered alike throughout, FIGS. 1A-1D schematically illustrate an exemplary integrated chip scale package 100 in accordance with the present invention having a carrier 110 with a chip 140 integrally mounted therein with the carrier 110 sealed by a lid 160. The carrier 110 may include a plurality of layers of a material, such as a metal, which may be laid down as a plurality of sequentially deposited layers using PolyStrata sequential layer build technology. The carrier may include one or more apertures 112 disposed at a selected surface thereof, the apertures 112 extending through a wall of the carrier to permit communication between, or pass power between, the interior and exterior of the carrier 110. One or more conductive stubs 130 may be provided in each aperture 112 to permit electrical communication between the interior and exterior of the carrier 110 and package 100. The conductive stubs 130 may be suspended within the apertures 112 by insulative dielectric materials 120 to prevent direct contact with, and prevent electrical communication between, the conductive stubs 130 and the carrier 110 in the region of the apertures 112. (A multiplicity of conductive stubs 230 may be suspended within the apertures of a carrier 210 by insulative dielectric materials 220, FIG. 3.) The conductive stubs 130 may include a plurality of sequentially deposited layers using Poly Strata sequential layer build technology. The dielectric material 120 may also be provided as part of the PolyStrata sequential layer build process. The dielectric material 120 may include a ceramic material such as alumina, or a glass such as Corning 7070 or 3D photo imaged glass. The dielectric material 120 may be kept thin in a range from 50 to 75 micrometers in height.

[0018] The dielectric material 120 may be provided in the form of an annular disk, such as in the shape of a washer, where the outer periphery of the dielectric material 120 may be embedded in the carrier 110 and the inner portion of the dielectric material 120 may be embedded in the conductive stubs 130. Thus, the dielectric materials 120 may be structured and positioned to provide a hermetic seal about the conductive stubs 130, in turn hermetically sealing the apertures 112. With the addition of a lid 160 to the carrier 110, a hermetically sealed integrated chip scale package 100 may be provided.

[0019] The chip 140 may electrically communicate with the conductive stubs 130 via one or more wirebonds 152 which may be electrically connected to a microstrip line 150 of the chip 140, FIG. 1B. Such a configuration may be particularly suitable for RF connections through the conductive stubs 130 and aperture 112. RF connections may be designed in conjunction with the wire bonds 152 to provide a suitable match over frequencies from DC through at least 50 GHz in the current design. Further optimization can enable a good match at frequencies up to at least 100 GHz. The transition from the bottom of the conductive stub 130 into a microstrip 150 in the chip 140 can achieve an excellent match up to millimeter wave frequencies. In the preliminary design, simulations show a match better than 22 dB up to 40 GHz and better than 12.5 dB up to 50 GHz. Further tuning can enable a match better than 15 dB up to 100 GHz. For DC applications, multiple conductive stubs 330 may be provided in a single aperture 312 to provide a higher density of conductive stubs, such as a pitch as low as 0.15 mm, FIG. 1E. For the DC aperture 312 multiple conductive stubs 330 can be passed through a single dielectric layer 320.

[0020] The chip 140 may be adhered to the carrier 110 via a solder or epoxy 142, and the carrier 110 may serve as a ground, FIG. 1C. The chip 140 may alternatively electrically communicate with the conductive stubs 130 via solder 143, such as by flip-chip mounting, FIG. 2.

[0021] One advantage to the approach of the present invention is that the conductive stubs 130, 230 can directly transition into rectangular (or other shaped) coaxial transmission lines, and microwave circuits including couplers, combiners, and filters, fabricated by PolyStrata sequential layer build technology. An example of this is provided in FIG. 5, where the carrier 110 of FIG. 1A is electrically connected to rectangular coaxial transmission lines 170, 172 via solder 145, rather than directly to the chip 140, to provide a package 500. For instance, a region under the chip 140 may include circuits or lines, or can be solid copper to provide an efficient thermal path below the chip to a host interface. Once the chip 140 is integrated into the Poly Strata sequential layer build technology carrier 110, the chip/carrier combination can be tested before the lid 160 is sealed allowing for rework if required. This chip/carrier combination can include one or more chips 140.

[0022] Once the package 100 has been fabricated and tested, it can be integrated with other components using several techniques. For instance, the package 100 can be directly connectorized using standard RF and DC connectors. These standard connectors can be edge launch or normal launch. However, more compacted methods for assembling multiple packages 100 together may include vertical and planar epoxy connections that can be made directly to printed circuit boards, to additional packages 100, or to other Poly Strata sequential layer build technology boards.

[0023] These and other advantages of the present invention will be apparent to those skilled in the art from the foregoing specification. Accordingly, it will be recognized by those skilled in the art that changes or modifications may be made to the above-described embodiments without departing from the broad inventive concepts of the invention. It should therefore be understood that this invention is not limited to the particular embodiments described herein, but is intended to include all changes and modifications that are within the scope and spirit of the invention as set forth in the claims.