Integrated circuit connection device

Abstract

The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (V.sub.DD) and part of the circuit operates using at least one internal regulated voltage (V.sub.REG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (V.sub.DD) and earth (V.sub.SS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (V.sub.esd). The connection device further includes switching means (3) for modifying the control signals (V.sub.esd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (V.sub.DD) and the internal regulated voltage (V.sub.REG). This allows the voltage range of said integrated circuit to be adapted to an external component connected to the external contact pad (2).

Claims

1. An integrated circuit connection device for connecting an external component, said integrated circuit being powered by a supply voltage and one part of the circuit operating using at least one internal regulated voltage, said connection device including two active transistors of different conductivity series connected between the supply voltage and earth, the drains of these two active transistors being connected to each other so as to form an external contact pad, the gates of said active transistors being intended to be controlled by voltage signals having the same amplitude at different times such that the active transistors are opened and closed without any overlap and are not conductive at the same time, wherein the connection device further includes switching means connected to the gates of the active transistors, to the supply voltage, and to said at least one internal regulated voltage, for modifying the amplitude level of the voltage signals applied across the gates of the active transistors, without exceeding the highest voltage between the supply voltage and the internal regulated voltage so as to adapt the voltage level applied to the gates of the active transistors to the voltage level of an external component connected to the external contact pad, wherein the switching means includes selection means for giving the voltage signals to be applied to the gates of said active transistors either the voltage level matching the supply voltage, or the voltage level matching the internal regulated voltage, the higher of the two voltages being selected.

2. The connection device according to claim 1, wherein a first active transistor is of the NMOS type and a second transistor is of the PMOS type.

3. The connection device according to claim 1, wherein the switching means also includes conversion means for adapting the amplitude level of the voltage signals to control the transistors with the selected voltage.

4. The connection device according to claim 2, wherein the switching means also includes conversion means for adapting the amplitude level of the voltage signals to control the transistors with the selected voltage.

5. The connection device according to claim 1, wherein said connection device includes a voltage level shifter receiving at input a first transistor gate control signal which operates at the internal regulated voltage, and supplying at output a first output signal to a control circuit, which will process said first output signal and apply the control signals working at the selected voltage to the transistors.

6. The connection device according to claim 2, wherein said connection device includes a voltage level shifter receiving at input a first transistor gate control signal which operates at the internal regulated voltage, and supplying at output a first output signal to a control circuit, which will process said first output signal and apply the control signals working at the selected voltage to the transistors.

7. The connection device according to claim 5, wherein said connection device includes a second voltage level shifter, receiving at input a second transistor gate control signal which operates at the internal regulated voltage, and supplying at output a second output signal to the control circuit, which will process said second output signal so as to apply the control signals to the transistors to set said transistors in high impedance mode.

8. The connection device according to claim 6, wherein said connection device includes a second voltage level shifter, receiving at input a second transistor gate control signal which operates at the internal regulated voltage, and supplying at output a second output signal to the control circuit, which will process said second output signal so as to apply the control signals to the transistors to set said transistors in high impedance mode.

9. The connection device according claim 1, wherein the voltage level is manually selected.

10. The connection device according claim 2, wherein the voltage level is manually selected.

11. The connection device according to claim 1, wherein the voltage level is selected automatically.

12. The connection device according to claim 2, wherein the voltage level is selected automatically.

13. The connection device according to claim 2, wherein the PMOS transistor includes a well, which is biased at a voltage corresponding to the maximum amplitude value of the voltage signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The objects, advantages and features of the connection device will appear more clearly in the following detailed description of at least one embodiment of the invention given solely by way of non-limiting example and illustrated by the annexed drawings, in which:

(2) FIG. 1 shows schematically the connection device according to the present invention;

(3) FIG. 2 shows schematically the voltage shift device used, and

(4) FIG. 3 shows schematically the connection device according to a preferred embodiment.

DETAILED DESCRIPTION OF THE INVENTION

(5) In the following description, all those parts of the integrated circuit that are well known to those skilled in the art in this technical field will be described only in a simplified manner.

(6) FIG. 1 shows schematically connection device 1 according to the present invention. This device 1 includes a buffer formed of two active transistors. The buffer includes more specifically one transistor P1 and one transistor N1 connected in series. Thus, the drains of the two transistors N1, P1 are connected to each other, whereas the source of transistor P1 is connected to supply voltage V.sub.DD and the source and well of transistor N1 is connected to earth V.sub.SS. The drains of both transistors are also connected to external contact pad 2 where an external component can be connected. The gates of these transistors N1, P1 are connected to the same potential, while the well of transistor P1 is biased at a voltage corresponding to the maximum amplitude value of the voltage signals controlling transistors N1 and P1.

(7) This arrangement thus guarantees that the logic level 1 is equal to V.sub.DD, when supply voltage V.sub.DD is connected to the source of transistor P1. Moreover, this arrangement guarantees that the buffer is non-conductive when the voltage applied across external contact pad 2 is lower than or equal to the potential applied across the gates of transistors N1 and P1. As previously stated, if the voltage applied to the external contact pad 2 is higher than the gate voltage, then the buffer is unlikely to still be non-conductive. It must, however, be understood that the voltage of the external component being connected across external contact pad 2 must never be higher than the voltage applied to the gates of transistors N1 and P1.

(8) This is why this invention also includes means for applying a voltage higher than V.sub.DD to the external contact pad 2 without making the buffer conductive. To achieve this, connection device 1 includes switching means 3 for altering the potential value applied to the gates of transistors N1 and P1 so as to adapt it to the voltage applied across external contact pad 2. This switching means 3 includes selection means 4 and conversion means 5.

(9) Nonetheless, to alter the value of the potential applied to the gates of transistors N1 and P1, it must be possible to generate the different voltages that one wishes to apply. This is why the integrated circuit is provided with means for generating these different internal voltages. This may include various means such as, for example, one or several DC-DC converters. Of course, these voltages may serve other functions in the integrated circuit, such as powering switching means 3.

(10) In a preferred embodiment, transistor P1 is a PMOS transistor and transistor N1 is an NMOS transistor. The circuit is powered by a supply voltage V.sub.DD and includes means for generating a regulated internal voltage V.sub.REG. Thus, to alter the voltage range of external contact pads 2 of the integrated circuit, switching means 3 will alter the potential of the gates of active transistors N1, P1 with one or other of the two voltages V.sub.DD or V.sub.REG. This thus allows several possible voltage ranges in the buffer. Preferably, it is the higher of the two voltages that is selected. Thus, this means that the largest voltage range is always available and thus a larger choice of external circuit voltage to be connected.

(11) Selection means 4 takes the form of a voltage comparator 4 which will compare V.sub.DD and V.sub.REG in order to select the highest voltage. Comparator 4 then delivers, at output, a voltage V.sub.esd of equal value to the highest voltage between V.sub.REG and V.sub.DD. This voltage V.sub.esd is then transmitted to conversion means 5 and to the well of transistor P1 in order to control the buffer. Conversion means 5 is used to alter the voltage level of the input signals IN_LS1 and IN_LS2 to supply transistor control signals COMMAND_N and COMMAND_P applied across the gates of transistors N1, P1 and setting them at voltage V.sub.esd. Of course, voltage V.sub.esd could be selected automatically as a function of the external component voltage applied to external contact pad 2. Thus, voltage comparator 4 immediately selects the voltage which is higher than that of the external component. This then enables the integrated circuit to adapt automatically to the external component voltage and thus prevents the buffer from becoming conductive.

(12) Conversion means 5 takes the form of a voltage level shifter which converts the input control signals from the integrated circuit working at voltage V.sub.REG to adapt their output voltage level to voltage V.sub.esd.

(13) These voltage level shifters, 5 shown in FIG. 2, include an input IN opening into an inverter 7 powered by V.sub.REG and a transistor system. This system is jointed into two symmetrical branches each including three active transistors. Each branch thus includes two P type transistors called T1, T2 in the first branch and T1, T2 in the second branch, and an N type transistor called T3 in the first branch and T3 in the second branch. Each transistor T3, T3 is respectively connected in series with a transistor T2, T2, and the source of transistors T3, T3 is connected to earth V.sub.SS. Transistors T1, T1 are series connected with transistors T2, T2 and powered by V.sub.esd at the source thereof. The gates of transistors T2 and T3 are connected to each other at the output of inverter 7. The gates of transistors T2 and T3 are connected to each other at the input IN of inverter 7. The drains of transistors T2 and T3 are connected to each other at the gate of transistor T1. The drains of transistors T2 and T3 are connected to each other at the gate of transistor T1, these drains also forming the output OUT of the voltage level shifter.

(14) When the circuit is operating, if inverter input IN is at logic level 1, the inverter output is thus at logic level 0. The application of this logic level 0 across the gate of transistors T2 and T3 causes transistor T2 to change to conductive mode and transistor T3 to change to non-conductive mode. Moreover, the application of the inverter input signal across the gate of transistors T2 and T3 causes transistor T2 to change to non-conductive mode and transistor T3 to conductive mode. Because transistor T3 is conductive and the drains of T2 and T3 are connected to the gate of transistor T1, this allows said gate of transistor T1 to be connected to earth V.sub.SS, rendering the latter conductive. Given that transistors T1 and T2 are conductive, voltage V.sub.esd passes through said transistors. Since the drain of transistor T2 is connected to the gate of transistor T1, voltage V.sub.esd is then applied across the gate of transistor T1. Transistor T1 then becomes non-conductive. The output OUT of the voltage level shifter, which is the connection point of the drains of transistors T2 and T3, is then earth V.sub.SS. Conversely, when the inverter input IN is at logic level 0, transistors T1, T2 and T3 become non-conductive whereas transistors T3, T1 and T2 become conductive. This then allows the voltage level shifter output OUT to be at V.sub.esd.

(15) The diagram of FIG. 3 shows two voltage level shifters LS1 and LS2. The first LS1 of these shifters is the one that shifts the control signal voltage levels of said transistors N1 and P1. A signal IN_LS1 for controlling the transistors is applied to the input of shifter LS1. The second LS2 of these shifters is used to set said output buffer in high impedance mode. This mode is characterized in that the logic level of said external contact pad 2 is neither at logic level 1 nor at logic level 0. This state avoids creating interference at the other terminals of the integrated circuit. This shifter LS2 receives at input a control signal IN_LS2 for setting it in high impedance mode

(16) The output signals OUT_LS1 and OUT_LS2, at voltage V.sub.esd are sent across a control circuit 6. Control circuit 6 is responsible for applying control signals COMMAND_N and COMMAND_P to said gates of transistors P1 and N1 in order to render them conductive or non-conductive in high impedance mode.

(17) This control circuit 6 further includes means for applying the control signals to the gates without any overlap. In practice, control circuit 6 first of all makes one of transistors N1 or P1 non-conductive before making the other conductive. This is so that the two transistors are not conductive at the same time.

(18) Evidently, some preferred arrangements may be provided, such as making V.sub.REG higher than V.sub.DD. This arrangement also allows supply voltage V.sub.DD to be reduced while maintaining the possibility of connecting external components whose voltage is higher than V.sub.DD but lower than V.sub.REG.

(19) In another embodiment, the integrated circuit can generate a higher number of internal regulated voltages than two. This multiplicity allows finer adjustment of the voltage applied to transistor N1, P1 in accordance with the external component voltage. Moreover, this allows the buffer a higher number of possible voltage ranges, thereby increasing the flexibility of the integrated circuit.

(20) Further, the selection of the voltage applied to the transistor gates may be made by by a manual selector instead of a voltage detector.

(21) It will be clear that various alterations and/or improvements and/or combinations evident to those skilled in the art may be made to the various embodiments of the invention set out above without departing from the scope of the invention defined by the annexed claims.