Level shifter

Abstract

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Claims

1. A level shifter comprising: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal, wherein the level shifter section includes a differential amplifier circuit and a current mirror circuit, and wherein the threshold voltage changing circuit includes: a constant current source having an input connected to the first power source voltage; a first transistor having a first electrical conductivity type and having a first main electrode connected to an output of the constant current source, a second main electrode connected to a second power source voltage having a voltage lower than the first power source voltage, and a first control electrode connected to a node between an output terminal where the output signal is output and the differential amplifier circuit; and a second transistor having a second electrical conductivity type opposite to that of the first electrical conductivity type and having a third main electrode connected to the differential amplifier circuit, a fourth main electrode connected to the differential amplifier circuit and the output terminal, and a second control electrode connected to a node between the output of the constant current source and the first main electrode.

2. The level shifter of claim 1, wherein the threshold voltage changing circuit is a hysteresis circuit exhibiting hysteresis characteristics with respect to changes in a voltage of the output signal in response to changes in the voltage of the input signal.

3. The level shifter of claim 1, wherein the differential amplifier circuit includes: a third transistor having a fifth main electrode connected to the first power source voltage, a sixth main electrode connected to the second power source voltage, and a third control electrode connected via a resistor to an input terminal to which the input signal is input, a fourth transistor having a seventh main electrode connected to the first power source voltage and an eighth main electrode connected to a fourth control electrode of the fourth transistor and to the output terminal, and a fifth transistor having the first electrical conductivity type and having a ninth main electrode connected to the eighth main electrode and the output terminal and a tenth main electrode connected to the second power source voltage; and the current mirror circuit includes: the fifth transistor, and a sixth transistor having the first electrical conductivity type and having an eleventh main electrode connected to the first power source voltage, a twelfth main electrode connected to the second power source voltage, and a sixth control electrode connected to a fifth control electrode of the fifth transistor.

4. The level shifter of claim 1, wherein: the constant current source and the second transistor are configured by an offset transistor, and the first transistor is configured by a vertical diffused transistor.

5. The level shifter of claim 1, further comprising a clamp section that limits the amplitude of the output signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments will be described in detail based on the following figures, wherein:

(2) FIG. 1 is a circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure;

(3) FIG. 2 is a vertical cross-sectional view illustrating a configuration of each element configuring a portion of a level shifter section and a threshold voltage changing circuit of the level shifter illustrated in FIG. 1;

(4) FIG. 3 is a vertical cross-sectional view corresponding to FIG. 2 illustrating a configuration of a buffer section of the level shifter illustrated in FIG. 1; and

(5) FIG. 4 is a characteristics plot illustrating an output signal in response to an input signal of the level shifter illustrated in FIG. 1.

DETAILED DESCRIPTION

(6) A level shifter according to an exemplary embodiment of the present disclosure will be described below with reference to FIG. 1 to FIG. 4. Note that, in the present exemplary embodiment, elements having the same function or substantially the same function are allocated the same reference numeral and redundant description thereof is omitted.

(7) As illustrated in FIG. 1, a level shifter 1 according to the present exemplary embodiment is driven by a high-voltage first power source voltage V.sub.BB supplied from a vehicle mounted battery. The level shifter 1 is configured of a level shifter section 2 and a buffer section 3. In the level shifter 1, output signals S.sub.OUT1 and S.sub.OUT2 that have been level-shifted from a first power source voltage V.sub.BB to lower voltages are output in accordance with an input signal S.sub.IN having a voltage lower than the first power source voltage V.sub.BB.

(8) The first power source voltage V.sub.BB is, for example, from 8 V to 18 V. The input signal S.sub.IN is, for example, a signal that rises from 0 V (low level) to 6 V (high level) or a signal that falls from 6 V to 0 V. The output signals S.sub.OUT1 and S.sub.OUT2 are, for example, signals that step up from 0 V (low level) to 5 V (high level) or signals that step down from 5 V to 0 V. The output signal S.sub.OUT2 is an inverted signal of the output signal S.sub.OUT1. Here, a second power source voltage V.sub.SS is 0 V.

(9) The level shifter section 2 of the level shifter 1 includes main configuration of a differential amplifier circuit 21, a current mirror circuit 22, and a clamp section 23. Further, the level shifter section 2 includes a threshold voltage changing circuit 24.

(10) The differential amplifier circuit 21 is configured including a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 is configured by a pnp-type bipolar transistor. In the first transistor T1, an emitter electrode serving as a first main electrode is connected to the first power source voltage V.sub.BB via a constant current source IR1, and a collector electrode serving as a second main electrode is connected to the second power source voltage V.sub.SS. A base electrode serving as a first control electrode of the first transistor T1 is connected to an input terminal IN via a resistor (input resistor) R. The input signal S.sub.IN is input to the input terminal IN.

(11) The second transistor T2 is configured by a pnp-type bipolar transistor having the same structure to that of the first transistor T1. In the second transistor T2, an emitter electrode, serving as a third main electrode, is connected to the first power source voltage V.sub.BB via the constant current source IR1. A collector electrode, serving as a fourth main electrode of the second transistor T2, is connected to a base electrode, serving as a second control electrode of the second transistor T2, and to an output terminal OUT of the level shifter section 2, and is also connected to the second power source voltage V.sub.SS via a third transistor T3. An output signal S.sub.OUTM of the level shifter section 2 that has been level-shifted from the first power source voltage V.sub.BB to a lower voltage is output to the output terminal OUT.

(12) The third transistor T3 is configured by an n-channel insulated gate field effect transistor (IGFET) that has n-type conductivity as a first electrical conductivity type. To describe in more detail, in the present exemplary embodiment, the third transistor T3 is configured by a vertical diffused metal oxide semiconductor field effect transistor (VDMOSFET) having a structure with a high withstand voltage. The vertical cross-sectional structure of the third transistor T3 is described later. In the third transistor T3, a drain electrode, serving a fifth main electrode, is connected to the collector electrode of the second transistor T2 and to the output terminal OUT, and a source electrode, serving as a sixth main electrode, is connected to the second power source voltage V.sub.SS.

(13) The current mirror circuit 22 is configured including the third transistor T3 and a fourth transistor T4. The fourth transistor T4 is configured by an n-channel IGFET having the same structure as the third transistor T3. In the fourth transistor T4, a drain electrode, serving as a seventh main electrode, is connected to the first power source voltage V.sub.BB via a constant current source IR2, and a source electrode, serving as an eighth main electrode, is connected to the second power source voltage V.sub.SS. A gate electrode serving as a fourth control electrode of the fourth transistor T4 is connected to a gate electrode serving as a third control electrode of the third transistor T3.

(14) The clamp section 23 is configured by an npn-type bipolar transistor. In this bipolar transistor, a collector electrode, serving as one main electrode, is connected to a third power source voltage V.sub.CC. The third power source voltage V.sub.CC is a low voltage level that has been shifted from first power source voltage V.sub.BB, and is, for example, 5 V. An emitter electrode, serving as another main electrode, and a base electrode, serving as a control electrode, are connected to a node between the output terminal OUT, and the collector electrode of the second transistor T2 and the drain electrode of the third transistor T3. The clamp section 23 limits the amplitude of the output signal S.sub.OUTM, and is, for example, configured to limit the output signal S.sub.OUTM to 5.6V or less, such that the buffer section 3, which is a next-stage circuit, is not applied with an amplitude exceeding this limit.

(15) The threshold voltage changing circuit 24 is provided within the level shifter section 2, and is configured including a constant current source IR3, a fifth transistor T5, and a sixth transistor T6. The threshold voltage changing circuit 24 is configured by a hysteresis circuit that exhibits hysteresis characteristics to changes in the voltage of the output signal S.sub.OUTM in response to changes in the voltage of the input signal S.sub.IN. These hysteresis characteristics are described later. An input of the constant current source IR3 is connected to the first power source voltage V.sub.BB. The constant current source IR3 is configured by the same structure as the other constant current sources IR1 and IR2, and is configured by a p-channel IGFET that has p-type conductivity as a second electrical conductivity type. To describe in more detail, in the present exemplary embodiment, in the present exemplary embodiment, the IGFET is configured by an offset metal oxide semiconductor field effect transistor (an offset MOSFET) having a structure with a high withstand voltage. The vertical cross-section structure of this IGFET is described later.

(16) The fifth transistor T5 is configured by an n-channel IGFET having the same structure as the third transistor T3, and, more specifically, is configured by a VDMOSFET. In the fifth transistor T5, a drain electrode, serving as a ninth main electrode, is connected to an output of the constant current source IR3, and a source electrode, serving as a tenth main electrode, is connected to the second power source voltage V.sub.SS. A gate electrode, serving as a fifth control electrode of the fifth transistor T5, is connected to a node between the output terminal OUT, and the collector electrode of the second transistor T2 and the drain electrode of the third transistor T3.

(17) The sixth transistor T6 is configured by a p-channel IGFET having the same structure as the constant current source IR3, and, more specifically, is configured by an offset MOSFET. In the sixth transistor T6, a source electrode, serving as an eleventh main electrode, is connected to a collector electrode of the second transistor T2, and a drain electrode, serving as a twelfth main electrode, is connected to the drain electrode of the third transistor T3 and to the output terminal OUT. A gate electrode, serving as a sixth control electrode of the sixth transistor T6, is connected to a node between the output of the constant current source IR3 and the drain electrode of the fifth transistor T5.

(18) In the present exemplary embodiment, the buffer section 3 is configured including a first inductor 31 and a second inductor 32, these being two stages electrically connected together in series. The first inductor 31 is configured including a seventh transistor T7 and an eighth transistor T8. To describe in more detail, the seventh transistor T7 is configured by a p-channel IGFET. A source electrode, serving as one main electrode of the seventh transistor T7, is connected to the third power source voltage V.sub.CC, and a drain electrode, serving as another main electrode of the seventh transistor T7, is connected to an output terminal OUT2 of the buffer section 3. A gate electrode, serving as a control electrode of the seventh transistor T7, is connected to the output terminal OUT of the level shifter section 2. The eighth transistor T8 is configured by an n-channel IGFET. A source electrode, serving as one main electrode of the eighth transistor T8, is connected to the second power source voltage V.sub.SS, and a drain electrode, serving as another main electrode of the eighth transistor T8, is connected to the output terminal OUT2. A gate electrode, serving as a control electrode of the eighth transistor T8, is connected to the output terminal OUT. In the first inductor 31, an output signal S.sub.OUT2, which is inverted with respect to the output signal S.sub.OUTM of the level shifter section 2 output to the output terminal OUT, is output from the output terminal OUT2.

(19) The second inductor 32 is configured including a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 is configured by a p-channel IGFET having the same structure as the seventh transistor T7. A source electrode, serving as one main electrode of the ninth transistor T9, is connected to the third power source voltage V.sub.CC, and a drain electrode, serving as another main electrode of the ninth transistor T9, is connected to an output terminal OUT1. A gate electrode, serving as a control electrode of the ninth transistor T9, is connected to the output of the first inductor 31. The tenth transistor T10 is configured by an n-channel IGFET having the same structure as the eighth transistor T8. A source electrode, serving as one main electrode of the tenth transistor T10, is connected to the second power source voltage V.sub.SS, and a drain electrode, serving as another main electrode of the tenth transistor T10, is connected to the output terminal OUT1. A gate electrode, serving as a control electrode of the tenth transistor T10, is connected to the output of the first inductor 31. In the second inductor 32, the output signal S.sub.OUT1, which is inverted with respect to output signal S.sub.OUT2 of the first inductor 31, is output from the output terminal OUT1.

(20) The level shifter 1 according to the present exemplary embodiment is configured as a semiconductor integrated circuit (a semiconductor device). As illustrated in FIG. 2 and FIG. 3, the level shifter 1 is formed with a semiconductor substrate 40 serving as a base. In the present exemplary embodiment, an n-type monocrystalline silicon substrate is employed as the semiconductor substrate 40.

(21) As illustrated in FIG. 2, semiconductor elements of a first transistor T1 to a fourth transistor T4 of the level shifter section 2 and the npn-type bipolar transistor of the clamp section 23 are each formed in an epitaxial growth layer 41 formed on a main face of the semiconductor substrate 40. Each of these semiconductor elements is formed in the epitaxial growth layer 41, within a region whose surroundings are enclosed by element isolating regions 42.

(22) The first transistor T1 is configured including a p-type well region 43 formed in the epitaxial growth layer 41, an n-type base region 45 formed in a main face section of the p-type well region 43, and a p-type semiconductor region 48 formed in a main face section of the n-type base region 45. The p-type well region 43 is employed as a collector electrode. The p-type well region 43 is connected to the second power source voltage V.sub.SS via the p-type semiconductor region 48 that serves as a well contact having a higher impurity concentration than the p-type well region 43. The n-type base region 45 is employed as a base electrode. The n-type base region 45 is connected to one end of a resistor R via an n-type semiconductor region 47 that serves as a base contact having a higher impurity concentration than the n-type base region 45. The p-type semiconductor region 48 is employed as an emitter electrode and is connected to the first power source voltage V.sub.BB via the constant current source IR1 illustrated in FIG. 1. The second transistor T2 is configured by the same vertical cross-section structure as the first transistor T1.

(23) The resistor R is configured by a p-type semiconductor region 48 formed in a main face section of an n-type well region 44. The n-type well region 44 is formed in the epitaxial growth layer 41. One end of the resistor R is connected to the base electrode of the first transistor T1. Another end of the resistor R is connected to the input terminal IN.

(24) The third transistor T3 is configured by a VDMOSFET in the present exemplary embodiment. To describe in more detail, as illustrated in FIG. 2, the third transistor T3 is configured including one main electrode (the sixth main electrode), a channel formation region, another main electrode (the fifth main electrode), a gate insulating film 50, and a gate electrode 51. The one main electrode is configured including an n-type well region 44. The impurity concentration of the n-type well region 44 is set lower than the impurity concentration of the semiconductor substrate 40. At an end portion of the gate electrode 51, the channel formation region is formed in the main face section of a p-type base region 46 formed in the main face section of the n-type well region 44. The p-type base region 46 is connected to a p-type semiconductor region 46P having a higher impurity concentration than the p-type base region 46. The other main electrode is configured by an n-type semiconductor region 47 formed in the main face section of the p-type base region 46, and is connected to the output terminal OUT. The gate electrode 51 is connected to a gate electrode 51 of the fourth transistor T4. The fourth transistor T4 is configured by the same vertical cross-sectional structure as the third transistor T3.

(25) The bipolar transistor of the clamp section 23 is configured including an n-type well region 44, a p-type base region 46 formed in a main face section of the n-type well region 44, and an n-type semiconductor region 47 formed in the main face section of the p-type base region 46. The n-type well region 44 is employed as a collector electrode. The n-type well region 44 is connected to the third power source voltage V.sub.CC via the n-type semiconductor region 47, which serves as a well contact. The p-type base region 46 is employed as a base electrode. The p-type base region 46 is connected to the output terminal OUT via a p-type semiconductor region 48 that serves as a base contact. The n-type semiconductor region 47 is employed as an emitter electrode and is connected to the output terminal OUT.

(26) On the other hand, as illustrated in FIG. 3, the seventh transistor T7 constructing the first inductor 31 of the buffer section 3 is formed in a main face section of an n-type well region 44 within a region whose surroundings are enclosed by element isolating regions 42. The seventh transistor T7 is configured including the n-type well region 44 serving as a channel formation region, a pair of p-type semiconductor regions 48 serving as one main electrode and another main electrode, a gate insulating film 50, and a gate electrode 51. The p-type semiconductor region 48 that serves as the one main electrode is connected to the third power source voltage V.sub.CC. The p-type semiconductor region 48 that serves as the other main electrode is connected to the output terminal OUT2 and the gate electrode 51 of the next stage second inductor 32. The eighth transistor T8 constructing the first inductor 31 is formed in a main face section of a p-type well region 43 within a region whose surroundings are enclosed by element isolating regions 42. The eighth transistor T8 is configured including a p-type well region 43 serving as a channel formation region, a pair of n-type semiconductor regions 47 serving as one main electrode and another main electrode, a gate insulating film 50, and a gate electrode 51. The n-type semiconductor region 47 that serves as the one main electrode is connected to the second power source voltage V.sub.SS. The n-type semiconductor region 47 that serves as the other main electrode is connected to the output terminal OUT2 and to the gate electrode 51 of the next stage second inductor 32.

(27) The ninth transistor T9 constructing the second inductor 32 is configured by the same structure as the seventh transistor T7. The tenth transistor T10 constructing the second inductor 32 is configured by the same structure as the eighth transistor T8. The other main electrodes of the ninth transistor T9 and the tenth transistor T10 are each connected to the output terminal OUT1.

(28) The fifth transistor T5 configuring the threshold voltage changing circuit 24 illustrated in FIG. 1 is configured by a VDMOSFET having the same vertical cross-sectional structure as the third transistor T3 illustrated in FIG. 2. Description of fifth transistor T5 is omitted since the structure is the same as the third transistor T3.

(29) The sixth transistor T6 constructing the threshold voltage changing circuit 24 is configured by an offset MOSFET like that illustrated in FIG. 2. The sixth transistor T6 is formed in within a region whose surroundings are enclosed by element isolating regions 42, and is formed on a main face section of an n-type well region 44. The sixth transistor T6 is configured including the n-type well region 44 serving as a channel formation region, a pair of p-type semiconductor regions 48 serving as one main electrode (the eleventh main electrode) and another main electrode (the twelfth main electrode), a gate insulating film 50, and a gate electrode 51. The other main electrode is a p-type semiconductor region 48 disposed in a position offset from the gate electrode 51, and a p-type semiconductor region 49 having a lower impurity concentration than the impurity concentration of the p-type semiconductor region 48 is formed below the gate electrode 51 on the channel formation region side of this p-type semiconductor region 48.

(30) Furthermore, the constant current source IR3 constructing the threshold voltage changing circuit 24 is configured by an offset MOSFET having the same vertical cross-section structure as the sixth transistor T6. Here, the constant current sources IR1 and IR2 of the level shifter section 2 illustrated in FIG. 1 are each configured by offset MOSFETs having the same vertical cross-section structures as the constant current source IR3.

(31) As illustrated in FIG. 1, the level shifter 1 according to the present exemplary embodiment is configured including the level shifter section 2. The level shifter section 2 is driven by the first power source voltage V.sub.BB, and switches the output signal S.sub.OUTM, which has been level-shifted from the first power source voltage V.sub.BB to a voltage lower than the first power source voltage V.sub.BB, in accordance with switching of the input signal S.sub.IN having a voltage lower than the first power source voltage V.sub.BB.

(32) Here, the level shifter 1 includes the threshold voltage changing circuit 24 in addition to the level shifter section 2. In accordance with the switching direction of the input signal S.sub.IN, the threshold voltage changing circuit 24 changes the threshold voltage of the input signal S.sub.IN for switching the output signal S.sub.OUTM.

(33) FIG. 4 illustrates the output signal S.sub.OUTM in response to the input signal S.sub.IN performed in the threshold voltage changing circuit 24. The horizontal axis is voltage (V) of the input signal S.sub.IN. The vertical axis is the voltage (V) of the output signal S.sub.OUTM. A first threshold voltage of 3 V is set by the threshold voltage changing circuit 24 for a case in which the input signal S.sub.IN input to the input terminal IN of the level shifter section 2 is switching from 0 V to 6 V. This switches the output signal from 0 V to 5 V in a case in which the input signal S.sub.IN reaches the first threshold voltage. On the other hand, a second threshold voltage of 2.8 V, which is lower than the first threshold voltage, is set by the threshold voltage changing circuit 24 for a case in which the input signal S.sub.IN input to the input terminal IN is switching from 6 V to 0 V. This switches the output signal from 5 V to 0 V in a case in which the input signal S.sub.IN reaches the second threshold voltage.

(34) Thus, in the threshold voltage changing circuit 24, since a permissible range (the first threshold voltage-the second threshold voltage) proportionate to the noise generated in the input signal S.sub.IN can be generated for the threshold voltage, switching of the output signal S.sub.OUTM within the permissible range may be prevented. In the above example, the permissible range is set to 0.2 V, and the output signal S.sub.OUTM does not switch even if noise is generated in the input signal S.sub.IN as long the noise is within this range. Accordingly, in the level shifter 1 according to the present exemplary embodiment, noise tolerance may be improved and malfunctions may be prevented.

(35) As illustrated in FIG. 4, in the level shifter 1 according to the present exemplary embodiment, the threshold voltage changing circuit 24 is a hysteresis circuit that exhibiting hysteresis characteristics with respect to changes in the voltage of the output signal S.sub.OUTM in response to changes in the voltage of the input signal S.sub.IN. Namely, the threshold voltage changing circuit 24 may be implemented simply by using a hysteresis circuit.

(36) Furthermore, as illustrated in FIG. 1, in the level shifter 1 according to the present exemplary embodiment, the threshold voltage changing circuit 24 is configured including the constant current source IR3, the fifth transistor T5, and the sixth transistor T6. In the constant current source IR3, the input is connected to the first power source voltage V.sub.BB. In the fifth transistor T5, the ninth main electrode is connected to the output of the constant current source IR3, the tenth main electrode is connected to the second power source voltage V.sub.SS, and the fifth control electrode is connected to a node between the output terminal OUT, and the fourth main electrode the second transistor T2 and the fifth main electrode of the third transistor T3. The fifth transistor T5 is configured with n-channel conductivity. In the sixth transistor T6, the eleventh main electrode is connected to the fourth main electrode of the second transistor T2, the twelfth main electrode is connected to the fifth main electrode of the third transistor T3 and the output terminal OUT, and the sixth control electrode is connected to a node between the output of the constant current source IR3 and the ninth main electrode of the fifth transistor T5. The sixth transistor T6 is configured with p-channel conductivity. Thus, in the threshold voltage changing circuit 24, the permissible range of the threshold voltage (the voltage difference between the first threshold voltage and the second threshold voltage) is set by the ON-state resistance characteristics of the fifth transistor T5 and the sixth transistor T6. Accordingly, the level shifter 1 according to the present exemplary embodiment may enable variability in the permissible range to be lessened, and may improve switching precision of the output signal S.sub.OUTM.

(37) Further, in the level shifter 1 according to the present exemplary embodiment, the constant current source IR3 and the sixth transistor T6 are configured by offset transistors (offset MOSFETs), and the fifth transistor T5 is configured by a vertical diffused transistor (a VDMOSFET). These are both transistors with high withstand voltages. This enables level shifting from a high voltage power source (the first power source voltage V.sub.BB) of a vehicle mounted battery installed in a vehicle such as an automobile to a low voltage (the third power source voltage V.sub.CC) usable by an ECU or the like.

(38) Furthermore, the level shifter 1 according to the present exemplary embodiment includes the clamp section 23 at a stage prior to the output terminal OUT of the level shifter section 2. The clamp section 23 limits the amplitude of the output signal S.sub.OUTM. For example, the clamp section 23 limits the output signal S.sub.OUTM to 5.6 V or less. This may prevent damage and breakdown of the next-stage circuits (the buffer section 3) of the level shifter section 2, and may implement high reliability of the level shifter 1.

(39) Further, in the level shifter 1 according to the present exemplary embodiment, the constant current source IR3 and the sixth transistor T6 of the threshold voltage changing circuit 24 are each configured by the same structures as the constant current sources IR1 and IR2 of the level shifter section 2. Likewise, the fifth transistor T5 of the threshold voltage changing circuit 24 is configured by the same structure as the third transistor T3 and the fourth transistor T4 of the level shifter section 2. Thus, the threshold voltage changing circuit 24 is configured using transistors already being used in the level shifter section 2 without needing new transistors, enabling the threshold voltage changing circuit 24 to be configured simply.

(40) The present disclosure is not limited to the exemplary embodiment above and can be modified within a range not departing from the spirit thereof. For example, in the level shifter 1, the present disclosure may employ lateral diffused MOSFETs (LDMOSFETs) having lateral diffused structures as the transistors that construct the level shifter section 2 and the threshold voltage changing circuit 24. Furthermore, the circuit configuration of the buffer section above is not limited to the exemplary embodiment described above. For example, in the first inductor 31 of the buffer section 3, the eighth transistor T8 may be employed as a resistor.