Semiconductor device

Abstract

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Claims

1. A semiconductor device comprising: a bipolar transistor including an emitter layer extending with a width, a bump electrically connected to the emitter layer, and a mounting substrate that supports a metal wiring line electrically connected to the bump, the metal wiring line being arranged, with respect to the emitter layer, such that a center of the metal wiring line is positioned in plan view at a position that is separated from a center of the emitter layer in a longitudinal direction in which the emitter layer extends, wherein the bump is disposed between the mounting substrate and the emitter layer in a direction normal to a surface of the mounting substrate facing the bump, and the metal wiring line is directly and electrically connected to the bump.

2. A semiconductor device according to claim 1, wherein the bipolar transistor further includes an emitter wiring line electrically connected to the emitter layer, and an insulating film covering the emitter wiring line and having an opening through which the emitter wiring line is exposed, and the bump is on the insulating film so as to bury the opening and is electrically connected to the emitter layer via the emitter wiring line.

3. A semiconductor device according to claim 2, wherein the emitter wiring line covers the entirety of the emitter layer in plan view.

4. A semiconductor device according to claim 1, wherein the bump is arranged, with respect to the emitter layer, such that a center of the bump is positioned in plan view at a position that is separated from a center of the emitter layer in a longitudinal direction in which the emitter layer extends.

5. The semiconductor device according to claim 1, wherein the bipolar transistor is a heterojunction bipolar transistor.

6. The semiconductor device according to claim 1, wherein the bump includes a pillar bump.

7. A semiconductor device according to claim 1, further comprising an emitter electrode on the emitter layer, a wiring line electrically connected to the emitter layer via the emitter electrode, a topmost wiring line electrically connected to the emitter layer via the emitter electrode and wiring line, an insulating film covering the topmost wiring line and having an opening through which the topmost wiring line is exposed, the opening being arranged so as to overlap at least a portion of the emitter layer in plan view, and a rewiring line formed on the insulating film so as to bury the opening and electrically connected to the emitter layer via the topmost wiring line.

8. The semiconductor device according to claim 7, wherein the wiring line is electrically connected to the topmost wiring line and below the topmost wiring line, wherein a main material of the rewiring line is different from that of the wiring line.

9. The semiconductor device according to claim 7, wherein the rewiring line is arranged so as to cover the emitter layer in plan view.

10. The semiconductor device according to claim 7, wherein the bump is formed on a part of the rewiring line and electrically connected to the rewiring line.

11. The semiconductor device according to claim 7, wherein the bipolar transistor is a heterojunction bipolar transistor.

12. The semiconductor device according to claim 10, wherein the bump includes a pillar bump.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a plan view of a semiconductor device according to embodiment 1 of the present disclosure.

(2) FIG. 2 is a sectional view taken along sectional line II-II depicted in FIG. 1 in the same embodiment.

(3) FIG. 3 is a sectional view taken along sectional line III-III depicted in FIG. 1 in the same embodiment.

(4) FIG. 4 is a sectional view taken along sectional line IV-IV depicted in FIG. 1 in the same embodiment.

(5) FIG. 5 is a graph illustrating the relationship between the arrangement of a pillar bump with respect to a bipolar transistor, and thermal stress.

(6) FIG. 6 is a first plan view schematically illustrating the arrangement relationship between an emitter layer and a third opening in the same embodiment.

(7) FIG. 7 is a second plan view schematically illustrating the arrangement relationship between the emitter layer and the third opening in the same embodiment.

(8) FIG. 8 is a third plan view schematically illustrating the arrangement relationship between the emitter layer and the third opening in the same embodiment.

(9) FIG. 9 is a fourth plan view schematically illustrating the arrangement relationship between the emitter layer and the third opening in the same embodiment.

(10) FIG. 10 is a plan view of a semiconductor device according to a modification of the same embodiment.

(11) FIG. 11 is a sectional view taken along sectional line XI-XI depicted in FIG. 10 in the same embodiment.

(12) FIG. 12 is a sectional view illustrating a step in a process of manufacturing the semiconductor device in the same embodiment.

(13) FIG. 13 is a sectional view illustrating a step performed after the step illustrated in FIG. 12 in the same embodiment.

(14) FIG. 14 is a sectional view illustrating a step performed after the step illustrated in FIG. 13 in the same embodiment.

(15) FIG. 15 is a sectional view illustrating a step performed after the step illustrated in FIG. 14 in the same embodiment.

(16) FIG. 16 is a sectional view illustrating a step performed after the step illustrated in FIG. 15 in the same embodiment.

(17) FIG. 17 is a sectional view illustrating a step performed after the step illustrated in FIG. 16 in the same embodiment.

(18) FIG. 18 is a sectional view illustrating a step performed after the step illustrated in FIG. 17 in the same embodiment.

(19) FIG. 19 is a sectional view illustrating a step performed after the step illustrated in FIG. 18 in the same embodiment.

(20) FIG. 20 is a sectional view illustrating a step performed after the step illustrated in FIG. 19 in the same embodiment.

(21) FIG. 21 is a sectional view illustrating a step performed after the step illustrated in FIG. 20 in the same embodiment.

(22) FIG. 22 is a sectional view illustrating a step performed after the step illustrated in FIG. 21 in the same embodiment.

(23) FIG. 23 is a sectional view illustrating a step performed after the step illustrated in FIG. 22 in the same embodiment.

(24) FIG. 24 is a sectional view of a semiconductor device according to embodiment 2 of the present disclosure.

(25) FIG. 25 is a sectional view of a semiconductor device according to embodiment 3 of the present disclosure.

(26) FIG. 26 is a sectional view of a semiconductor device according to embodiment 4 of the present disclosure.

(27) FIG. 27 is a plan view of a semiconductor device of the related art.

(28) FIG. 28 is a sectional view taken along sectional line XXVIII-XXVIII depicted in FIG. 27.

(29) FIG. 29 is a sectional view taken along sectional line XXIX-XXIX depicted in FIG. 27.

DETAILED DESCRIPTION

Embodiment 1

(30) Here, a first example of a semiconductor device that includes a heterojunction bipolar transistor will be described.

(31) As illustrated in FIGS. 1, 2, 3 and 4, in a semiconductor device that includes a bipolar transistor BT, a sub-collector layer 2 (n-type GaAs, Si concentration 5×10.sup.18 cm.sup.−3, film thickness: 0.6 μm) is formed so as to contact the surface of a semi-insulating GaAs substrate 1. A collector layer 3 (n-type GaAs, Si concentration: 5×10.sup.15 cm.sup.−3, film thickness: 1.0 μm) is formed so as to contact the sub-collector layer 2. A base layer 4 (p-type GaAs, C concentration 4×10.sup.19 cm.sup.−3, film thickness: 100 nm) is formed so as to contact the collector layer 3.

(32) A mesa-shaped emitter layer 5 is formed so as to contact the base layer 4. The emitter layer 5 has a structure obtained by stacking, in order from the base layer 4 side, an n-type In.sub.xGa.sub.1-xP layer (In composition ratio x=0.5, Si concentration: 3×10.sup.17 cm.sup.−3, film thickness: 30 nm), an n-type GaAs layer (Si concentration: 3×10.sup.17 cm.sup.−3, film thickness: 90 nm), an n-type GaAs contact layer (Si concentration: 1×10.sup.19 cm.sup.−3, film thickness: 50 nm) and an n-type In.sub.xGa.sub.1-xAs contact layer (In composition ratio x=0.5, Si concentration: 1×10.sup.19 cm.sup.−3, film thickness: 50 nm).

(33) An emitter electrode 6 is formed so as to contact the emitter layer 5. A collector electrode 8 is formed so as to contact the sub-collector layer 2. A base electrode 7 is formed so as to contact the base layer 4. The emitter electrode 6 is formed of a WSi film (Si molar ratio: 0.3, film thickness: 0.3 μm). The base electrode 7 is formed by stacking a Ti film (film thickness: 50 nm), a Pt film (film thickness: 50 nm) and a Au film (film thickness: 200 nm). The collector electrode 8 is formed by stacking a AuGe film (film thickness: 60 nm), a Ni film (film thickness: 10 nm) and a Au film (film thickness: 200 nm).

(34) A first insulating film 9 (SiN, film thickness: 50 nm) is formed so as to cover the emitter electrode 6, the base electrode 7 and the collector electrode 8. A first opening 10, through which the emitter electrode 6 etc. are exposed, is formed in the first insulating film 9. A first wiring line 11a that is electrically connected to the emitter electrode 6, a first wiring line 11b that is electrically connected to the base electrode 7 and a first wiring line 11c that is electrically connected to the collector electrode 8 via the first opening 10 are formed so as to contact the first insulating film 9. The first wiring lines 11a, 11b and 11c are formed of a metal film (Au, film thickness: 1 μm), for example.

(35) A second insulating film 12 (SiN, film thickness: 100 nm) is formed so as to cover the first wiring lines 11a, 11b and 11c. A second opening 13, through which the first wiring line 11a is exposed, is formed in the second insulating film 12. A second wiring line 14 (Au, film thickness: 4 μm), which is electrically connected to the first wiring line 11a via the second opening 13, is formed so as to contact the second insulating film 12. As illustrated in FIG. 1, the second wiring line 14 is formed so as to cover the entirety of the bipolar transistor including the collector layer 3, the base layer 4 and the emitter layer 5.

(36) A passivation film 15 (SiN, film thickness: 500 nm) is formed so as to cover the second wiring line 14. A third opening 16, through which the second wiring line 14 is exposed, is formed in a prescribed region of the passivation film 15. A pillar bump 20 is formed so as to bury the third opening 16 and so as to contact the part of the passivation film 15 located along the edge of the opening of the third opening 16. As illustrated in FIGS. 3 and 4, the pillar bump 20 has a multilayer structure consisting of underbump metal (UBM) 17 (Ti, film thickness: 150 nm), a metal post 18 (Cu, film thickness: 50 μm) and solder 19 (Sn, film thickness: 30 μm). A barrier metal layer, which is for preventing inter-diffusion of Ni and the like, may be formed between the metal post 18 and the solder 19.

(37) Next, the arrangement relationship between the pillar bump 20, the third opening 16 and the bipolar transistor (emitter layer 5) will be described in detail.

(38) As illustrated in FIG. 1, the emitter layer 5 forms a rectangular emitter. Taking the longitudinal direction of the emitter layer 5 to be an X direction and a direction perpendicular to the longitudinal direction to be a Y direction, the length (width) of the emitter layer 5 in the Y direction is set to be 4 μm and the length of the emitter layer 5 in the X direction (longitudinal direction) is set to be 28 μm. A length PX of the pillar bump 20 in the X direction is set to be 75 μm and a length PY of the pillar bump 20 in the Y direction is set to be around 75 to 500 μm. A length KX of the third opening 16 in the X direction is set to be 55 μm. In addition, as illustrated in FIG. 3, the third opening 16 is arranged with respect to the emitter layer 5 such that an end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 and the edge of the opening of the third opening 16 are substantially aligned with each other.

(39) In the semiconductor device that includes the bipolar transistor described above, the third opening 16, through which the pillar bump 20 and the second wiring line 14, which is electrically connected to the emitter layer 5, contact each other, is arranged at a position that is shifted in the longitudinal direction of the emitter layer 5 away from a position where the third opening 16 would be directly above the emitter layer 5. As a result, thermal stress acting on the bipolar transistor can be relieved. This will be explained below.

(40) The inventors recognized that thermal stress is caused by a difference between the rate of thermal expansion of the emitter layer 5 etc. (GaAs layers) and the rate of thermal expansion of the pillar bump 20. A graph obtained by evaluating the relationship between thermal stress and the arrangement of the pillar bump 20 (third opening 16) with respect to the bipolar transistor BT by using a simulation is illustrated in FIG. 5. The horizontal axis represents the position in the longitudinal direction of the emitter layer with the center of the emitter layer (center in longitudinal direction and width direction) serving as the origin. The vertical axis represents thermal stress in the emitter layer. The length of the emitter layer is set to be 30 μm. Furthermore, the ratio of an overlapping area, in plan view, between the emitter layer and the third opening with respect to the area of the emitter layer in plan view is called an overlapping ratio.

(41) As illustrated in FIG. 5, first, it is clear that the thermal stress has a substantially constant distribution inside the region of the emitter layer in the case of an overlapping ratio of 100% as in the case of the semiconductor device of the related art illustrated in FIG. 27 etc., which serves as a comparative example. From this state, when the overlapping ratio is decreased by shifting the third opening (pillar bump) in the X direction (positive), it is clear that the thermal stress in the emitter layer tends to gradually decrease from the part of the emitter layer on the side where the third opening is located (part A) toward the part of the emitter layer located on the side opposite the side where the third opening is located (part B).

(42) That is, it is clear that the thermal stress tends to gradually decrease in the emitter layer in the X direction (negative) as the overlapping ratio is made smaller. In addition, it is clear that the thermal stress in part A of the emitter layer also decreases and the thermal stress decreases by around 12% compared with the case of the comparative example when the overlapping ratio is around 7%.

(43) According to an evaluation performed by the inventors, it was determined that, even when the emitter layer and the third opening overlap in plan view, thermal stress at the end portion of the emitter layer can be reduced when the overlapping ratio is lower than ½ (50%) and that the thermal stress can be more effectively reduced when the overlapping ratio is lower than ¼ (25%). That is, it was determined that, in order to reduce thermal stress, it is sufficient that the area over which the emitter layer and the third opening overlap in plan view be small and it is not necessary to adopt a structure in which the emitter layer and the third opening do not overlap at all in plan view.

(44) This is thought to be because thermal stress in the emitter layer 5 etc. can be relieved by forming a region in which the pillar bump 20 is not disposed directly above the emitter layer 5, and, even if the pillar bump 20 is disposed directly above the emitter layer 5, the thermal stress in the emitter layer 5 etc. can be relieved by forming a region in which the emitter layer 5 etc. are covered by the passivation film 15, which is interposed between the pillar bump 20 and the emitter layer 5.

(45) In addition, it is clear that the thermal stress is reduced by around 22% from that in the case of the comparative example when the overlapping ratio is 0%. According to the evaluation performed by the inventors, in the case where the overlapping ratio is 0%, it was determined that stress in the emitter layer can be reduced so long as the end portion of the emitter layer is positioned in a region where the pillar bump and a passivation layer overlap in plan view. That is, it was determined that, in order to reduce thermal stress, it is not necessary to adopt a structure in which the emitter layer and pillar bump do not overlap at all in plan view and that thermal stress can be reduced by interposing the passivation film 15 between the emitter layer 5 and the pillar bump 20.

(46) That is, it is considered that thermal stress in the emitter layer 5 etc. can be relieved by interposing a passivation film in the region in which the emitter layer 5 etc. and the pillar bump 20 overlap in plan view.

(47) Although thermal stress can be reduced by shifting the third opening (pillar bump) away from the emitter layer 5 in the X direction (positive), the thermal resistance when heat generated in the collector layer 3 etc. directly below the emitter layer 5 is conducted to the pillar bump 20 increases due to the distance from the emitter layer 5 etc. to the pillar bump becoming larger. Accordingly, thermal resistance will be examined.

(48) The thermal resistance when heat generated in the collector layer 3 etc. directly below the emitter layer 5 is conducted to the pillar bump 20 becomes markedly larger in an arrangement where the emitter layer and the pillar bump do not overlap in plan view. For example, when the distance between the end portion of the emitter layer in the longitudinal direction and the edge of the third opening is 18 μm, the thermal resistance begins to markedly increase to around 2.6 times that in the related art. In addition, when the distance becomes longer than 18 μm, the thermal resistance rapidly increases in proportion to the increase in distance or greater than in proportion to the increase in distance.

(49) On the other hand, in the case where the overlapping ratio is lower than ½ (50%), the distance from the collector layer 3 etc. directly below the emitter layer 5 to the edge of the third opening 16 of the pillar bump 20 is comparatively short and therefore an increase in the thermal resistance therebetween is avoided. For example, when the overlapping ratio between the emitter layer and the third opening is around 7%, the thermal resistance remains around 1.5 times that in the related art and comparatively gently increases.

(50) In addition, in embodiment 1, the second wiring line 14 is depicted as the wiring line to which the pillar bump 20 is electrically connected and this second wiring line 14 has a film thickness of 4 μm and therefore there is a benefit in that the thermal resistance is partially reduced in this region and the overall thermal resistance is reduced compared with using the 1 μm thick first wiring line 11a as the wiring line to which the pillar bump 20 is electrically connected.

(51) The inventors obtained the following information as a result of investigating the two parameters of thermal stress and thermal resistance. First, an arrangement in which the overlapping ratio between the emitter layer 5 and the third opening 16 is ½ (50%), as illustrated in FIG. 6, is referred to as arrangement A and an arrangement in which the overlapping ratio is ¼ (25%), as illustrated in FIG. 7, is referred to as arrangement B. In addition, an arrangement in which the overlapping ratio is 0 and the end portion of the emitter layer in the longitudinal direction of the emitter layer is aligned with the edge of the opening of the third opening, as illustrated in FIG. 8, is referred to as arrangement C. An arrangement in which the overlapping ratio is 0 and the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is located in a region in which the pillar bump 20 and the passivation film 15 overlap in plan view, as illustrated in FIG. 9, is referred to as arrangement D.

(52) The inventors found that it is preferable to dispose the third opening 16 with respect to the emitter layer 5 at a position between arrangement A and arrangement D in order to relieve thermal stress while suppressing an increase in thermal resistance and that it is preferable to dispose the third opening 16 with respect to the emitter layer 5 at a position between arrangement B and arrangement D in order to more effectively reduce thermal stress.

(53) The bipolar transistor illustrated in FIGS. 1 to 4 described above corresponds to arrangement C. In addition, a bipolar transistor having an overlapping ratio of 7% is illustrated in FIGS. 10 and 11. The bipolar transistor illustrated in FIGS. 10 and 11 is the same as the bipolar transistor illustrated in FIGS. 1 to 4 except for the different overlapping ratio and the same parts are denoted by the same symbols and description thereof is not repeated.

(54) In the bipolar transistor described above, by relieving thermal stress in the emitter layer 5 etc., deterioration of the current gain of the bipolar transistor in a short period of time can be prevented when evaluating long-term reliability by applying current to the bipolar transistor at a high temperature, and the reliability of a semiconductor device that includes the bipolar transistor can be improved.

(55) In addition, as a result of the third opening 16 being arranged at a position that is shifted away from a position where the third opening 16 would be directly above the emitter layer 5 in the longitudinal direction of the emitter layer 5, the area occupied by the bipolar transistor is increased compared with the case of the comparative example. In the semiconductor device described above, the increase in the area occupied by the bipolar transistor can be suppressed to the absolute minimum by specifying the area in which to arrange the third opening 16 with respect to the emitter layer 5.

(56) Next, an example of a method of manufacturing the semiconductor device illustrated in FIG. 1 etc. will be described as a method of manufacturing a semiconductor device that includes a bipolar transistor.

(57) First, prescribed layers that will form the sub-collector layer, the collector layer, the base layer, the emitter layer and so forth are formed on the surface of a semi-insulating GaAs substrate by using an epitaxial growth method such as a metal organic chemical vapor deposition (MOCVD) method.

(58) As illustrated in FIG. 12, an n-type GaAs layer 2a (Si concentration 5×10.sup.18 cm.sup.−3, film thickness: 0.6 μm), which will become the sub-collector layer, is formed on the semi-insulating GaAs substrate 1. An n-type GaAs layer 3a (Si concentration: 5×10.sup.16 cm.sup.−3, film thickness: 1.0 μm), which will become the collector layer, is formed so as to contact the n-type GaAs layer 2a. A p-type GaAs layer 4a (C concentration: 4×10.sup.19 cm.sup.−3, film thickness: 50 nm), which will become the base layer, is formed so as to contact the n-type GaAs layer 3a.

(59) Next, an epitaxial layer 5a, which will become the emitter layer, is formed so as to contact the p-type GaAs layer 4a. The epitaxial layer 5a is obtained by stacking in order an n-type In.sub.xGa.sub.1-xP layer (In composition ratio x=0.5, Si concentration 3×10.sup.17 cm.sup.−3, film thickness: 30 nm), an n-type GaAs layer (Si concentration: 3×10.sup.17 cm.sup.−3, film thickness: 90 nm), an n-type GaAs contact layer (Si concentration 1×10.sup.19 cm.sup.−3, film thickness: 50 nm) and an n-type In.sub.xGa.sub.1-xAs contact layer (In composition ratio x=0.5, Si concentration: 1×10.sup.19 cm.sup.−3, film thickness: 50 nm).

(60) Next, a tungsten silicide (WSi) film (Si molar ratio: 0.3, film thickness: 0.3 μm) is deposited over the entire surface of the epitaxial layer 5a by using a high-frequency sputtering method. After that, the emitter electrode 6 is formed as illustrated in FIG. 13 by performing prescribed photolithography processing and dry etching processing using a prescribed gas.

(61) Next, the emitter layer 5 is patterned into a desired shape, as illustrated in FIG. 14, by performing prescribed photolithography processing and wet etching processing using a prescribed chemical. Next, the base electrode 7 is formed so as to contact the p-type GaAs layer 4a. After that, the base layer 4 and the collector layer 3 are formed, as illustrated in FIG. 15, by performing prescribed photolithography processing and wet etching processing using a prescribed chemical.

(62) Next, the collector electrode 8 (refer to FIG. 2) is formed so as to contact the sub-collector layer 2. Then, the sub-collector layer 2 is patterned into a desired shape by performing prescribed photolithography processing and wet etching processing using a prescribed chemical.

(63) After that, the first insulating film 9 (refer to FIG. 16), which is composed of a silicon nitride film for example, is formed so as to cover the emitter electrode 6 etc. Next, the first opening 10, through which the emitter electrode 6 is exposed, and an opening, through which the base electrode 7 is exposed, are formed in the first insulating film 9, as illustrated in FIG. 16, by performing prescribed photolithography processing and prescribed dry etching processing.

(64) After that, a metal film (not illustrated), which will become the first wiring lines, is formed so as to bury the first opening 10 and so forth. Next, the first wiring line 11a that is electrically connected to the emitter electrode 6, the first wiring line 11b that is electrically connected to the base electrode 7, and so forth are formed, as illustrated in FIG. 17, by performing prescribed photolithography processing and prescribed etching processing.

(65) After that, the second insulating film 12 (refer to FIG. 18), which is composed of a silicon nitride film for example, is formed so as to cover the first wiring lines 11a, 11b etc. Next, the second opening 13, through which the first wiring line 11a is exposed, is formed in the second insulating film 12, as illustrated in FIG. 18, by performing prescribed photolithography processing and prescribed dry etching processing.

(66) After that, a metal film (not illustrated), which will become the second wiring line, is formed so as to bury the second opening 13. Next, the second wiring line 14 that is electrically connected to the first wiring line 11a is formed, as illustrated in FIG. 19, by performing prescribed photolithography processing and prescribed etching processing. The second wiring line 14 is formed so as to cover the entirety of the bipolar transistor including the emitter layer, as illustrated in FIG. 1.

(67) Next, a passivation film (not illustrated), which is composed of a silicon nitride film for example, is formed so as to cover the second wiring line 14. After that, the third opening 16, through which the second wiring line 14 is exposed, is formed as illustrated in FIG. 20 by performing prescribed lithography processing and prescribed etching processing. In addition, as illustrated in FIGS. 20 and 1, the third opening 16 is formed with respect to the emitter layer 5 such that an end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 and the edge of the opening of the third opening 16 are substantially aligned with each other.

(68) Next, as illustrated in FIG. 21, a titanium (Ti) film 17a, which will become the UBM, is formed. After that, as illustrated in FIG. 22, the metal post 18, which is composed of a copper (Cu) film and the solder 19 are stacked in a prescribed region so as to contact the titanium film 17a. Next, the pillar bump 20, which has a multilayer structure consisting of the UBM 17, the metal post 18 and the solder 19, is formed as illustrated in FIG. 23 by removing the exposed titanium film 17a. As illustrated in FIG. 1, the pillar bump 20 is formed so as to bury the third opening 16 and so as to cover the passivation film 15 along the edge of the opening of the third opening 16. Thus, the principal part of the semiconductor device including the bipolar transistor BT is formed.

(69) In the method of manufacturing a semiconductor device described above, the overlapping ratio, which represents overlapping of the emitter layer 5 and the third opening 16 in plan view, is 0 and the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged so as to be substantially aligned with the edge of the opening of the third opening 16 (arrangement C). Thus, as has been described above, thermal stress can be effectively relieved while suppressing an increase in thermal resistance and the reliability of a semiconductor device that includes a bipolar transistor can be improved. In addition, the area occupied by the bipolar transistor can be reduced to the absolute minimum.

Embodiment 2

(70) Next, a semiconductor device in which a rewiring line is formed will be described as a second example of a semiconductor device that includes a heterojunction bipolar transistor.

(71) As illustrated in FIG. 24, a third insulating film 21 (film thickness: 10 μm) composed of a polyimide film or the like is formed so as to cover the passivation film 15. The third opening 16, through which the second wiring line 14 is exposed, is formed in the third insulating film 21 and the passivation film 15. The third opening 16 is arranged with respect to the emitter layer 5 such that the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 and the edge of the opening of the third opening 16 are substantially aligned with each other (arrangement C).

(72) A third wiring line 23 (film thickness: 5 μm), which serves as a rewiring line and is composed of a copper (Cu) film, is formed so as to contact the second wiring line 14 exposed at the bottom of the third opening 16 and so as to contact the part of the third insulating film 21 located along the edge of the opening of the third opening 16. In addition, a fourth insulating film 22 (film thickness: 3 μm) is formed that contacts the third insulating film 21, through which the third wiring line 23 is exposed and that is composed of a polyimide film. The pillar bump 20 is formed so as to contact the third wiring line 23 and so as to contact the fourth insulating film 22.

(73) The rest of the configuration is the same as that of the semiconductor device described in embodiment 1 and illustrated in FIGS. 1 to 4, and therefore parts that are the same are denoted by the same symbols and, unless necessary, description thereof is not repeated.

(74) In the semiconductor device described above, the overlapping ratio between the emitter layer 5 and the third opening 16 is 0 and the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged so as to be aligned with the edge of the opening of the third opening 16 (arrangement C). Thus, thermal stress can be effectively relieved while suppressing an increase in thermal resistance as described in embodiment 1.

(75) Furthermore, in addition to the passivation film 15, the third insulating film 21 and the fourth insulating film 22 are also interposed between second wiring line 14 and the pillar bump 20 in the bipolar transistor in which the third wiring line is formed as a rewiring line. Thus, thermal stress can be more effectively relieved and degradation of the lifetime (current gain) can be avoided when evaluating the long-term reliability by applying current at a high-temperature.

(76) In addition, forming the second wiring line 14 so as to cover the entirety of the emitter layer 5 can also contribute to reducing the thermal resistance.

(77) Furthermore, by forming the third wiring line 23 after forming the passivation film 15, the degree of freedom in arranging, for example, a pad electrically connected to the third wiring line 23 can be increased. That is, a bump can be disposed on another element such as a resistance or capacitance element and therefore the chip size can be made smaller. In addition, if the film thickness of the rewiring line is made sufficiently large, it is possible to form a low-loss spiral inductor having a high Q value and the performance of a monolithic microwave integrated circuit (MMIC) can be improved.

(78) Furthermore, in the semiconductor device described above, as an example, arrangement C was described in which the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged as to be aligned with the edge of the opening of the third opening 16. The arrangement relationship between the emitter layer 5 and the third opening 16 is not limited to arrangement C and it is sufficient that the third opening 16 be arranged at a position between arrangement A and arrangement D with respect to the emitter layer 5 in order to relieve thermal stress while suppressing an increase in the thermal resistance and it is sufficient that the third opening be arranged at a position between arrangement B and arrangement D with respect to the emitter layer 5 in order to more effectively reduce thermal stress.

Embodiment 3

(79) Next, a modification of embodiment 2 will be described as a third example of a semiconductor device that includes a heterojunction bipolar transistor.

(80) As illustrated in FIG. 25, the third insulating film 21 (film thickness: 10 μm) composed of a polyimide film or the like is formed so as to cover the passivation film 15. The third opening 16, through which the second wiring line 14 (film thickness: 5 μm) composed of a copper (Cu) film is exposed, is formed in the third insulating film 21 and the passivation film 15.

(81) The third wiring line 23, which serves as a rewiring line, is formed so as to contact the second wiring line 14 exposed at the bottom of the third opening 16 and so as to contact the part of the third insulating film 21 located along the edge of the opening of the third opening 16. The third wiring line 23 is electrically connected to the emitter layer 5 over a short distance via a part of the second wiring line 14 and a part of the first wiring line 11a that are located directly above the emitter layer 5, and via the emitter electrode 6.

(82) Furthermore, the fourth insulating film 22 (film thickness: 3 μm), which is composed of a polyimide film for example, is formed so as to contact the third insulating film 21. A fourth opening 24, through which the third wiring line 23 is exposed, is formed in the fourth insulating film 22. The pillar bump 20 is formed so as to contact the third wiring line and so as to contact the fourth insulating film 22. The fourth opening 24 is arranged with respect to the emitter layer such that the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 and the edge of the opening of the fourth opening 24 are substantially aligned with each other.

(83) The rest of the configuration is the same as that of the semiconductor device described in embodiment 1 and illustrated in FIGS. 1 to 4, and therefore parts that are the same are denoted by the same symbols and, unless necessary, description thereof is not repeated.

(84) In the semiconductor device described above, the overlapping ratio between the emitter layer 5 and the fourth opening 24 is 0 and the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged so as to be aligned with the edge of the opening of the fourth opening 24 (arrangement C). Thus, thermal stress can be effectively relieved while suppressing an increase in thermal resistance as described in embodiment 1.

(85) Furthermore, in addition to the passivation film 15, the third insulating film 21 and the fourth insulating film 22 are also interposed between second wiring line 14 and the pillar bump 20 in the bipolar transistor in which the third wiring line is formed as a rewiring line. Thus, thermal stress can be more effectively relieved and degradation of the lifetime (current gain) can be avoided when evaluating the long-term reliability by applying current at a high-temperature.

(86) In addition, compared to the case of embodiment 2, the third insulating film 21 having a film thickness of 10 μm is newly interposed between the plane where the pillar bump 20 contacts the third wiring line 23, and the emitter layer 5. Thus, the thermal stress can be more effectively relieved compared with the case of embodiment 2.

(87) In addition, forming the second wiring line 14 so as to cover the entirety of the emitter layer 5 can also contribute to reducing the thermal resistance.

(88) Furthermore, by forming the third wiring line 23 after forming the passivation film 15, the degree of freedom in arranging, for example, a pad electrically connected to the third wiring line 23 can be increased, and, in particular, the chip size can be reduced since a pad can be disposed on a resistance or capacitance element. In addition, an inductor having a high Q value can be formed by making the thickness of the rewiring layer large.

(89) Furthermore, in the semiconductor device described above, as an example, arrangement C was described in which the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged to as to be aligned with the edge of the opening of the fourth opening 24. The arrangement relationship between the emitter layer 5 and the fourth opening 24 is not limited to arrangement C and it is sufficient that the fourth opening 24 be arranged at a position between arrangement A and arrangement D with respect to the emitter layer 5 in order to relieve thermal stress while suppressing an increase in the thermal resistance and it is sufficient that the fourth opening be arranged at a position between arrangement B and arrangement D with respect to the emitter layer 5 in order to more effectively reduce thermal stress.

Embodiment 4

(90) Next, a semiconductor device, in which a substrate on which a bipolar transistor has been formed, is mounted on a mounting substrate will be described.

(91) As illustrated in FIG. 26, the pillar bump 20, which is electrically connected to the emitter layer 5, is connected to a mounting substrate 25. For example, an alumina substrate, a ceramic substrate or a PCB can be used as the mounting substrate 25. A thin-film metal wiring line 26, to which the pillar bump is connected, is arranged on a surface of the mounting substrate 25. The bipolar transistor including the emitter layer is the same as the bipolar transistor illustrated in FIG. 1 etc.

(92) In the semiconductor device in which the bipolar transistor is mounted on the mounting substrate 25, it is assumed that thermal stress caused by a difference between the rate of thermal expansion of the emitter layer 5 etc. and the rate of thermal expansion of the mounting substrate 25 is generated in the emitter layer 5 etc. via the pillar bump 20.

(93) In the semiconductor device including the mounting substrate described above, the overlapping ratio between the emitter layer 5 and the third opening 16 is 0 and the end portion of the emitter layer 5 in the longitudinal direction of the emitter layer 5 is arranged so as to be aligned with the edge of the opening of the third opening 16 (arrangement C). Thus, thermal stress caused by a difference between the rate of thermal expansion of the emitter layer 5 etc. and the rate of thermal expansion of the mounting substrate 25 can be effectively relieved while suppressing an increase in thermal resistance as described in embodiment 1.

(94) In the semiconductor device described above, although, as an example, arrangement C was described in which the end portion of the emitter layer 5 in the longitudinal direction is arranged as to be aligned with the edge of the opening of the third opening 16, it is sufficient that the third opening 16 be arranged at a position between arrangement A and arrangement D with respect to the emitter layer 5 in order to relieve thermal stress while suppressing an increase in the thermal resistance and it is sufficient that the third opening 16 be arranged at a position between arrangement B and arrangement D with respect to the emitter layer 5 in order to more effectively reduce thermal stress.

(95) Furthermore, in the above-described embodiments, although a semiconductor device that includes a single bipolar transistor was described as an example, the present disclosure may also be applied to a semiconductor device in which a plurality of bipolar transistors are formed on a semi-insulating GaAs substrate. In addition, although a pillar bump was described as an example of a bump, other than a pillar bump, for example, a solder bump or a stud bump may be used.

(96) Furthermore, in the bipolar transistors of the embodiments described above, a case in which the emitter layer 5 is formed of an InGaP layer and the base layer 4 is formed of a GaAs layer was described as an example. The combination of materials for the emitter layer and the base layer (emitter layer/base layer) is not limited to InGaP layer/GaAs layer, and, for example, the present disclosure may be also applied to heterojunction bipolar transistors that use materials such as AlGaAs layer/GaAs layer, InP layer/InGaAs layer, InGaP layer/GaAsSb layer, InGaP layer/InGaAsN layer, Si layer/SiGe layer and AlGaN layer/GaN layer.

(97) In addition, in the embodiments described above, a case in which the planar shape of the emitter layer 5 is rectangular was described as an example, but the planar shape of the emitter layer may instead be circular, elliptical, hexagonal or octagonal, for example. Furthermore, in the embodiments described above, a case was described in which the third opening 16 is shifted toward one side in the longitudinal direction of the emitter layer 5, but the third opening 16 may be instead shifted toward the opposite side.

(98) The presently disclosed embodiments are illustrative examples and embodiments of the present disclosure are not limited to these illustrative examples. The scope of the present disclosure is not defined by the above description but rather by the scope of the claims and it is intended that equivalents to the scope of the claims and all modifications within the scope of the claims be included within the scope of the present disclosure.

INDUSTRIAL APPLICABILITY

(99) The present disclosure is effectively used in semiconductor devices that include a bipolar transistor.