POWER SEMICONDUCTOR CIRCUIT

Abstract

A power semiconductor circuit includes a power semiconductor device for switching a load, and a comparator which is directly or indirectly connected to the power semiconductor device at a connection point for the load by means of a first input and to which a predefined or predefinable reference voltage can be fed at a second input, the power semiconductor device being activatable by means of an output of the comparator.

Claims

1. A power semiconductor circuit comprising a power semiconductor device for switching a load comprising discrete and/or parasitic inductors, wherein, when the load is disconnected by means of the power semiconductor device, transient overvoltages result, characterised by a comparator which is directly or indirectly connected to a connection point of the load to the power semiconductor device by means of a first input and to which a predefined or predefinable reference voltage can be fed at a second input, the power semiconductor device being activatable by means of an output of the comparator.

2. The power semiconductor circuit according to claim 1, wherein a voltage divider is arranged upstream of the comparator.

3. The power semiconductor circuit according to claim 1, wherein the reference voltage can be set by means of a reference voltage circuit, at which an operating voltage is applied during operation and which, in parallel branches, has in each case a series circuit comprising an electronic switching element and a reference resistor, wherein all switching elements comprised by the reference voltage circuit can be controlled individually.

4. The power semiconductor circuit according to claim 3, wherein all reference resistors comprised by the reference voltage circuit are different.

5. A method for operating a power semiconductor circuit according to claim 1, wherein a clamping voltage is set by means of a predefinable reference voltage in accordance with the particular operating situation of the power semiconductor device.

6. The method according to claim 5, wherein the clamping voltage level is set in accordance with the particular temperature of the power semiconductor device.

Description

IN THE DRAWING

[0014] FIG. 1 shows a power semiconductor circuit with a known active clamping circuit,

[0015] FIG. 2 shows a power semiconductor circuit with a power semiconductor device and a circuit part for protecting the power semiconductor against transient overvoltages, and

[0016] FIG. 3 shows a reference voltage circuit usable together with a power semiconductor circuit according to FIG. 2.

[0017] Modern power semiconductor devices, in particular power MOSFETs, are used especially in switching applications, for example in DC/DC converters, in what is known as PWM operation.

[0018] FIG. 1 shows a circuit with a power semiconductor device 10, wherein the power semiconductor device 10 is designed to switch a connected load 12 which comprises parasitic inductors (L.sub.par) and discrete inductors (L). In PWM operation the power semiconductor device 10 is controlled by means of a signal source 14, which outputs a pulse-width modulated signal (PWM signal; U.sub.PWM). On account of the control by means of a signal source 14 of this kind, the power semiconductor device 10 is operated selectively in the fully switched-on and fully switched-off state.

[0019] The further descriptionwithout foregoing further generalityshall be continued on the basis of a signal source 14 which outputs a pulse-width modulated signal (U.sub.PWM) functioning as control signal. The signal source 14 is generally a device which outputs a clocked control signal. This shall be considered always to be the case hereinafter.

[0020] The pulse-width modulated signalor generally a control signal generated by the signal source 14is fed to a driver circuit 16. This comprises two complementary semiconductor switches, specifically a first driver switch 18 that is conductive during the positive pulse of the control signal and a second driver switch 20 that is conductive during the negative pulse of the control signal, and in each case a current-limiting resistor arranged downstream or upstream in the current flow direction respectively. The first driver switch 18 and the second driver switch 20 are connected to the gate terminal of the power semiconductor device 10 via said resistors. The first driver switch 18 for example is embodied as a npn transistor and the second driver switch 20 as a pnp transistor.

[0021] During the positive pulse of the control signal, the potential of a positive driver voltage +U.sub.TR applied at the first driver switch 18 is applied at the gate terminal of the power semiconductor device 10. The positive driver voltage +U.sub.TR is set such that the power semiconductor device 10 is connected through an account of the positive driver voltage +U.sub.TR. The drain-source path of the power semiconductor device 10 is thus conductive during the positive pulse of the control signal, and the connected load 12 is activated.

[0022] During the negative pulse of the control signal, the first driver switch 18 blocks, whereas the second driver switch 20 is conductive, such that a negative driver voltage U.sub.TR applied at the second driver switch 20 is applied at the gate terminal of the power semiconductor 10. The negative driver voltage is negative compared to the positive driver voltage +U.sub.TR and is set such that the power semiconductor device 10 blocks on account of the negative driver voltage U.sub.TR. The drain-source path of the power semiconductor device 10 is consequently non-conductive during the negative pulse of the control signal, and the load 12 is deactivated accordingly. On account of the parasitic and/or discrete inductors of the load 12, these initially drive on further the current interrupted by means of the power semiconductor device 10, at least temporarily, and this results in a voltage peak at the drain terminal of the power semiconductor device 10 and in an overvoltage over the drain-source path of the power semiconductor device 10.

[0023] This overvoltage is applied only very briefly, specifically only as long as the inductors of the load 12 drive the interrupted current on account of the electrical energy stored there. The duration of the overvoltage situation is usually less than a millisecond (>1 ms). The overvoltage is referred to accordingly hereinafter as a transient overvoltage U.sub.trans. The transient overvoltage U.sub.trans nevertheless can lead to the destruction or accelerated degeneration of the power semiconductor device, in spite of the short duration. Thus, it is sought to avoid transient overvoltages U.sub.trans of this kind. In the prior art, what is known as an active clamping circuit is known in this regard, and the circuit shown in FIG. 1 comprises an active clamping circuit of this kind, in which a Zener diode 22 and a diode 24 are connected between the drain terminal of the power semiconductor device 10 and the gate terminal of the power semiconductor device 10. In the shown embodiment the active clamping circuit comprises a Zener diode path having a plurality of Zener diodes 22 connected in series.

[0024] In the case of a transient overvoltage U.sub.trans above the breakdown voltage of the Zener diode or each Zener diode 22, this Zener diode or the Zener diode path is conductive. This leads, over the current path with the diode 24, to an increase of the gate potential. The power semiconductor device 10 is thus at least partially conductive in linear operation, and the energy stored in the inductors of the load 12 can drain via the power semiconductor device 10. At the same time, the driver circuit 16 is controlled over a path electrically parallel to the diode 24, such that the first driver switch 18 connects through, whereas the second driver switch 20 blocks. As the transient overvoltage U.sub.trans subsides, the control of the driver circuit 16 ends, such that the first driver switch 18 blocks and the second driver switch 20 connects through. The potential at the gate terminal of the power semiconductor device 10, said potential being increased on account of the transient overvoltage U.sub.trans, is then dissipated via the second driver switch 20. Lastly, the temporary activation of the power semiconductor 10 in linear operation thus ends and the circuit with the load 12 is interrupted and the load 12 is deactivated. Some of the energy stored in the inductors of the load 12 is also dissipated over the path of the control of the power semiconductor 10 and the driver circuit 16.

[0025] Problems encountered in a power semiconductor circuit of this kind in the active clamping circuit comprised thereby are in particular the comparatively high tolerances, caused by manufacture, temperature and/or age, of the Zener diode 22 or the Zener diodes 22 in respect of the various breakdown voltages thereof. The breakdown voltage of an individual Zener diode 22 orin the case of a Zener diode paththe breakdown voltage of the series connection of the Zener diodes 22 comprised thereby determines the detectable transient overvoltage U.sub.trans. A transient overvoltage U.sub.trans beneath this breakdown voltage is not identified, and the electrical energy associated therewith, accordingly, is not dissipated in the previously described way. It is therefore desirable to define the breakdown voltage particularly precisely. This precise definition is made difficult, however, on account of the above-mentioned tolerances. The design must consequently be based under consideration of the aforesaid tolerances and therefore typically requires large reserves. On account of such reserves, an active clamping circuit of the kind shown in FIG. 1 will potentially be effective without requiring the operating situation of the power semiconductor device 10.

[0026] FIG. 2 shows an embodiment of a circuit comprising a power semiconductor device 10 (power semiconductor circuit 30) in accordance with the approach presented here. The power semiconductor circuit 30 comprisesexactly as in FIG. 1a signal source 14 for emitting a control signal and a driver circuit 16 comprising a first and a second driver switch 18, 20. The power semiconductor device 10 is also used here again for the clocked switching of a load 12 comprising parasitic inductors L.sub.par and discrete inductors L. The clocked activation of the power semiconductor device 10 is implemented here as well, exactly as in the prior art according to FIG. 1, by means of a control signal emitted by a signal source 14, in particular by means of a pulse-width modulated control signal.

[0027] The special feature lies in the fact that the transient overvoltage U.sub.trans occurring when the power semiconductor device 10 is switched off is compared by means of a comparator 32 with a predefined or predefined reference voltage U.sub.Ref. In the embodiment shown in FIG. 2 the transient overvoltage U.sub.trans is divided proportionally by means of a voltage divider 34 (which in essence is optional) comprising two ohmic resistors (R1, R2). One of the resistors (R1) of the voltage divider 34 then advantageously at the same time causes a current limitation, and the part of the transient overvoltage U.sub.trans dropping over the other resistor (R2) is compared by means of the comparator 32 with the reference voltage U.sub.Ref.

[0028] The reference voltage U.sub.Ref is applied between the source terminal of the power semiconductor device 10 and the inverting input of the comparator 32. The non-inverting input of the comparator 32 is connected indirectly, specifically via part of the voltage divider 34, to the drain input of the power semiconductor device 10, and over this path the comparator 32 detects a possible transient overvoltage U.sub.trans and compares it with the reference voltage U.sub.Ref.

[0029] Should the transient overvoltage U.sub.trans reach the set value of the reference voltage U.sub.Ref or exceed it (U.sub.transU.sub.Ref), by means of the output of the comparator 32, on the one hand over the current path with the diode 24, the gate potential of the power semiconductor device 10 is raised, such that said power semiconductor device 10 passes into linear operation and is partially conductive, and on the other hand the driver circuit 16 is controlled. As described above in conjunction with FIG. 1, the energy stored in the inductors of the load 12 can drain away via the partially conductive power semiconductor device 10. The simultaneous temporary activation of the driver circuit 16 has the effect likewise already described above in conjunction with FIG. 1, specifically that the increased potential at the gate terminal of the power semiconductor device 10, said potential being increased as a result of the transient overvoltage U.sub.trans, does not disappear again directly on account of the otherwise connected-through second driver circuit 20 and the negative driver voltage U.sub.TR applied thereto. Thus, an at least temporary linear operation of the power semiconductor device 10 is possible during the period for which the transient overvoltage U.sub.trans is present.

[0030] The use of a predefined or predefined reference voltage U.sub.Ref allows the level of the transient overvoltage U.sub.trans that is to be detected to be set in an exact manner. The above-mentioned tolerances are therefore irrelevant for the setting of the switching or response threshold of the active clamping circuit proposed here. A fundamentally optional Zener diode 36 is used to protect the comparator 32.

[0031] The illustration in FIG. 3 shows a circuit functioning as a reference voltage circuit 40 for delivering an adjustable reference voltage U.sub.Ref. During operation, an operating voltage U.sub.B is applied at the reference voltage circuit 40, and the reference voltage U.sub.Ref is derived from said operating voltage. The reference voltage circuit 40 is a voltage divider and comprises, on one side of the voltage divider, a resistor network having at least two parallel branches/paths. In each branch/path the reference voltage circuit 40 comprises a series circuit having an electronic switching element 42 and a reference resistor 44. For example, MOSFETs are suitable electronic switching elements 42. Each switching element 42 can be controlled individually, for example by means of a control circuit (not shown here). The control of a switching element 42 causes the path in question to be activated and therefore causes the ohmic resistor of the totality of parallel paths to change, thus resulting in a change to the ratios of the resistance values of the two sides of the voltage divider. The totality of parallel paths forms one side of the voltage divider. The reference voltage U.sub.Ref set in the form of the activation of individual or multiple switching elements 42 can be tapped at a centre tap of the voltage divider. The other side of the voltage divider forms a resistor or a resistor network. The operating voltage U.sub.B divides proportionally, in the manner known per se, between the two sides of the voltage divider. The greater is the total resistance of the parallel paths, the closer the reference voltage U.sub.Ref that can be tapped at the reference voltage circuit 40 approximates the operating voltage U.sub.B, such that an increasingly higher reference voltage U.sub.Ref results. The lower is the total resistance of the parallel paths, the lower is the reference voltage U.sub.Ref that can be tapped at the reference voltage circuit 40. With a favourable selection of the resistance values of the reference resistors 44 in the individual parallel paths, up to 2.sup.n reference voltage levels can be set with a reference voltage circuit 40 of this kind, wherein n stands for the number of parallel paths. In the illustration in FIG. 3, a reference voltage circuit 40 having three parallel paths is shown.

[0032] Although the invention has been illustrated and described in greater detail by the exemplary embodiment, the invention is not limited by the disclosed example(s), and other variations can be derived herefrom by a person skilled in the art without departing from the scope of protection of the invention.

[0033] Individual important aspects of the description presented here can thus be briefly summarised as follows: What is described is a power semiconductor circuit 30 comprising a power semiconductor device 10 for switching a load 12, and a comparator 32 which is directly or indirectly connected to a connection point of the load 12 to the power semiconductor device 10 by means of a first input and to which a predefined or predefinable reference voltage U.sub.Ref can be fed at a second input, the power semiconductor device 10 being activatable by means of an output of the comparator 32.

LIST OF REFERENCE SIGNS

[0034] 10 power semiconductor device

[0035] 12 load

[0036] 14 signal source

[0037] 16 driver circuit

[0038] 20 (first) driver switch

[0039] 22 (second) driver switch

[0040] 24 Zener diode

[0041] 24 diode

[0042] 26, 82 (free)

[0043] 30 power semiconductor circuit

[0044] 32 comparator

[0045] 34 voltage divider

[0046] 36 Zener diode

[0047] 38 (free)

[0048] 40 reference voltage circuit

[0049] 42 switching element

[0050] 44 reference resistor