Multiplying DAC of pipelined ADC

Abstract

This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.

Claims

1. A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier; a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; and a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; wherein one of the second reference voltage and the third reference voltage is substantially ground.

2. The MDAC of claim 1, wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage.

3. The MDAC of claim 2, wherein the common-mode voltage of the differential input signal is a first voltage, the common-mode voltage of the second reference voltage and the third reference voltage is a second voltage, and a difference between the first reference voltage and the DC voltage of the first or second input terminal of the operational amplifiers in the amplification phase is substantially equal to (N1)/N times the difference between the first voltage and the second voltage, and N is a positive integer.

4. The MDAC of claim 3, wherein N is equal to 2.sup.P, and P is the integer part of the number of bits of the pipelined ADC.

5. The MDAC of claim 1 further comprising: a fifth capacitor having a ninth end and a tenth end, wherein the ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase; and a sixth capacitor having an eleventh end and a twelfth end, wherein the eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase.

6. The MDAC of claim 5, wherein the capacitance value of the second capacitor is X times the capacitance value of the first capacitor, the capacitance value of the fifth capacitor is Y times the capacitance value of the first capacitor, and the sum of X and Y is substantially one.

7. The MDAC of claim 6, wherein the difference between the second reference voltage and the third reference voltage is a first voltage difference, and when the first voltage difference is substantially R times an allowed maximum peak-to-peak value of the differential input signal, X is equal to R, R being a positive number.

8. The MDAC of claim 5, wherein the difference between the second reference voltage and the third reference voltage is not substantially equal to half of an allowed maximum peak-to-peak value of the differential input signal.

9. A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; and a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage.

10. The MDAC of claim 9, wherein the common-mode voltage of the differential input signal is a first voltage, the common-mode voltage of the second reference voltage and the third reference voltage is a second voltage, and a difference between the first reference voltage and the DC voltage of the first or second input terminal of the operational amplifiers in the amplification phase is substantially equal to (N1)/N times the difference between the first voltage and the second voltage, and N is a positive integer.

11. The MDAC of claim 10, wherein N is equal to 2.sup.P, and P is the integer part of the number of bits of the pipelined ADC.

12. A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier; a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; a fifth capacitor having a ninth end and a tenth end, wherein the ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase; and a sixth capacitor having an eleventh end and a twelfth end, wherein the eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase.

13. The MDAC of claim 12, wherein the capacitance value of the second capacitor is X times the capacitance value of the first capacitor, the capacitance value of the fifth capacitor is Y times the capacitance value of the first capacitor, and the sum of X and Y is substantially one.

14. The MDAC of claim 13, wherein the difference between the second reference voltage and the third reference voltage is a first voltage difference, and when the first voltage difference is substantially R times an allowed maximum peak-to-peak value of the differential input signal, X is equal to R, R being a positive number.

15. The MDAC of claim 12, wherein the difference between the second reference voltage and the third reference voltage is not substantially equal to half of an allowed maximum peak-to-peak value of the differential input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 illustrates a conventional pipelined analog-to-digital converter.

[0012] FIG. 2 illustrates a functional block diagram of one of the operational stages of FIG. 1.

[0013] FIG. 3 illustrates a conventional circuit diagram for generating the reference voltage V.sub.REF+ and the reference voltage V.sub.REF.

[0014] FIG. 4 illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to an embodiment of the present invention.

[0015] FIG. 5A illustrates a circuit diagram of the pipelined ADC of FIG. 4 operating in the sampling phase.

[0016] FIG. 5B illustrates a circuit diagram of the pipelined ADC of FIG. 4 operating in the amplification phase.

[0017] FIG. 6 illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention.

[0018] FIG. 7 illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention.

[0019] FIG. 8 illustrates a circuit diagram of one operational stage of a 2.5-bit pipelined ADC according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be explained accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said indirect means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events.

[0021] The disclosure herein includes an MDAC of a pipelined ADC. On account of that some or all elements of the MDAC could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure and this omission nowhere dissatisfies the specification and enablement requirements. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification.

[0022] FIG. 4 is a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to an embodiment of the present invention. The differential input signal V.sub.in (including the signals V.sub.in.sup.+ and V.sub.in.sup.) can be the output of a previous stage of the pipelined ADC (e.g., a programmable gain amplifier (PGA)) or the output of a previous operational stage that the current operational stage follows. The operational stage 400 includes a sub ADC 410, a decoder 420, and an MDAC 430. The operation principles of the sub ADC 410 and the decoder 420 are respectively the same as or similar to those of the conventional sub ADC 112 and decoder 114 and thus omitted for brevity. The MDAC 430 includes an operational amplifier 432, capacitors C0a, C1a, C0b, C1b, switches S0a to S4a, and switches S0b to S4b. The capacitance values of the capacitors C0a, C1a, C0b, and C1b are substantially the same. The MDAC 430 operates alternately in the sampling phase and the amplification phase. In the sampling phase, the switches S0a, S1a, S2a, S0b, S1b, S2b are turned on, and the remaining switches are turned off (FIG. 5A). In the amplification phase, the switches S3a, S4a, S3b, S4b are turned on, and the remaining switches are turned off (FIG. 5B). As shown in FIG. 5B, the DC voltage of the input terminals of the operational amplifier 432 in the amplification phase are V.sub.X.

[0023] One end of the capacitor C0a (or C0b) is coupled to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S through the switch S2a (or S2b) in the sampling phase, and is coupled to an input terminal of the operational amplifier 432 but not to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S in the amplification phase; the other end of the capacitor C0a (or C0b) receives the input signal V.sub.in.sup.+ (or V.sub.in.sup.) through the switch S0a (or S0b) in the sampling phase, and is coupled to the non-inverting output (or inverting output) of the operational amplifier 432 through the switch S3a (or S3b) in the amplification phase.

[0024] One end of the capacitor C1a (or C1b) is coupled to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S through the switch S2a (or S2b) in the sampling phase, and is coupled to an input terminal of the operational amplifier 432 but not to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S in the amplification phase; the other end of the capacitor C1a (or C1b) receives the input signal V.sub.in.sup.+ (or V.sub.in.sup.) through the switch S1a (or S1b) in the sampling phase, and receives the output voltage of the decoder 420 through the switch S4a (or S4b) in the amplification phase.

[0025] The decoder 420 outputs the reference voltage V.sub.REF+, the reference voltage V.sub.REF, and/or the voltage V.sub.CM.sub._.sub.REF according to the digital signal b. For example, in a certain amplification phase, the decoder 420 outputs the reference voltage V.sub.REF+ to the capacitor C1a through the switch S4a and outputs the reference voltage V.sub.REF to the capacitor C1b through the switch S4b; in another amplification phase, the decoder 420 outputs the voltage V.sub.CM.sub._.sub.REF to the capacitor C1a through the switch S4a and to the capacitor C1b through the switch S4b.

[0026] According to the principle of charge conservation, for all capacitors coupled to one of the input terminals of operational amplifier 432 (i.e., capacitors C0a and C1a or capacitors C0b and C1b), the total charge stored in the sampling phase should ideally be equal to the total charge stored in the amplification phase, which gives the derivation below. Note that the above reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S corresponds to the situation in which the voltage V.sub.CM.sub._.sub.REF is not equal to the voltage V.sub.CM.sub._.sub.PGA, and, in the following equations demonstrating the derivation of the DC voltage V.sub.X, the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S is temporarily replaced by the voltage V.sub.CM.sub._.sub.OPI, which corresponds to the situation in which the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA.

[00001]$\left(V_{\mathrm{CM\_PGA}}-V_{\mathrm{CM\_OPI}}\right).Math.\mathrm{NC}=\left(N-1\right).Math.C\left(V_{\mathrm{CM\_REF}}-V_X\right)+\left(V_{\mathrm{CM\_OPO}}-V_X\right).Math.C$${\mathrm{NV}}_{\mathrm{CM\_PGA}}-{\mathrm{NV}}_{\mathrm{CM\_OPI}}=\left(N-1\right).Math.V_{\mathrm{CM\_REF}}-\left(N-1\right).Math.V_X+V_{\mathrm{CM\_OPO}}-V_X$${\mathrm{NV}}_{\mathrm{CM\_PGA}}-{\mathrm{NV}}_{\mathrm{CM\_OPI}}=\left(N-1\right).Math.V_{\mathrm{CM\_REF}}-{\mathrm{NV}}_X+V_{\mathrm{CM\_OPO}}$$V_X=\frac{\left(N-1\right).Math.V_{\mathrm{CM\_REF}}-{\mathrm{NV}}_{\mathrm{CM\_PGA}}+{\mathrm{NV}}_{\mathrm{CM\_OPI}}+V_{\mathrm{CM\_OPO}}}{N}$

In these equations, C is the capacitance value of the capacitors C0a, C1a, C0b, C1b, V.sub.CM.sub._.sub.PGA is the common-mode voltage of the differential input signal V.sub.in, N is the number of capacitors coupled to one of the input terminals of the operational amplifier 432 (N=2.sup.P, P being the integer part of the number of bits of the pipelined ADC), and V.sub.CM.sub._.sub.OPO is the common-mode voltage of the differential output signal V.sub.out (including the output signals V.sub.out.sup.+ and V.sub.out.sup.).

[0027] When the common-mode voltage of the reference voltages V.sub.REF+ and V.sub.REF is substantially equal to the common-mode voltage of the differential input signal V.sub.in (i.e., when the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA), the voltage V.sub.CM.sub._.sub.OPO is ideally also substantially equal to the voltages V.sub.CM.sub._.sub.REF and V.sub.CM.sub._.sub.PGA, which gives the equations below.

[00002]$V_X=\frac{\left(N-1\right).Math.V_{\mathrm{CM\_REF}}-\left(N-1\right).Math.V_{\mathrm{CM\_PGA}}+{\mathrm{NV}}_{\mathrm{CM\_OPI}}}{N}$$V_X=\frac{{\mathrm{NV}}_{\mathrm{CM\_OPI}}}{N}=V_{\mathrm{CM\_OPI}}$

[0028] It can be observed from the above derivation that when the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA, the DC voltage V.sub.X of the input terminal of the operational amplifier 432 in the amplification phase is substantially equal to the reference voltage V.sub.CM.sub._.sub.OPI.

[0029] When the voltage V.sub.CM.sub._.sub.REF is deliberately controlled to be not equal to the voltage V.sub.CM.sub._.sub.PGA for the purpose of increasing the design flexibility of the MDAC 430, the following equation is obtained (assuming that V.sub.CM.sub._.sub.PGA=V.sub.CM+V.sub.CM.sub._.sub.REF and that the voltage V.sub.CM.sub._.sub.OPO is still substantially equal to V.sub.CM.sub._.sub.PGA):

[00003]$V_X=\frac{-\left(N-1\right)}{N}.Math..Math..Math.V_{\mathrm{CM}}+V_{\mathrm{CM\_OPI}}$

[0030] This equation shows that if a voltage level shift of

[00004]$\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}}$

is applied to the reference voltage V.sub.CM.sub._.sub.OPI, the DC voltage V.sub.X of the input terminal of the operational amplifier 432 in the amplification phase will substantially not be affected even though the voltage V.sub.CM.sub._.sub.REF is altered to be not equal to the voltage V.sub.CM.sub._.sub.PGA; that is, the DC voltage V.sub.X will still be substantially equal to the originally designed reference voltage V.sub.CM.sub._.sub.OPI. In other words, when the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA, the DC voltage V.sub.X of the input terminal of the operational amplifier 432 in the amplification phase is substantially equal to the reference voltage V.sub.CM.sub._.sub.OPI; when, on the other hand, the voltage V.sub.CM.sub._.sub.REF is not equal to the voltage V.sub.CM.sub._.sub.PGA, this invention applies a voltage level shift of

[00005]$\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}}$

to the reference voltage V.sub.CM.sub._.sub.OPI, and, therefore, the shifted reference voltage

[00006]$V_{\mathrm{CM\_OPI}.Math.\mathrm{\_S}}=V_X+\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}}$

will cause the DC voltage V.sub.X of the input terminal of the operational amplifier 432 in the amplification phase is still substantially equal to the original reference voltage V.sub.CM.sub._.sub.OPI. The above discussion explains that in the embodiment of FIG. 4, the DC voltage V.sub.X of the input terminal of the operational amplifier 432 in the amplification phase is not equal to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S. By creating a voltage difference of

[00007]$\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}}$

between the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S and the DC voltage V.sub.X, the operational amplifier 432 is less affected by the fact that the voltage V.sub.CM.sub._.sub.REF is not equal to the voltage V.sub.CM.sub._.sub.PGA.

[0031] With the circuit design of FIG. 4, the common-mode voltage V.sub.CM.sub._.sub.REF of the reference voltage V.sub.REF+ and the reference voltage V.sub.REF can be arbitrary, rather than having to be substantially equal to the common-mode voltage V.sub.CM.sub._.sub.PGA of the differential input signal V.sub.in. As a result, in some embodiments, the reference voltage V.sub.REF can be shifted to ground. For example, the reference voltage V.sub.REF+, the common-mode voltage V.sub.CM.sub._.sub.REF, and the reference voltage V.sub.REF can be shifted from 0.75VDD, 0.5VDD, and 0.25VDD to 0.5VDD, 0.25VDD, and 0, respectively, and the difference between the voltage V.sub.REF+ and the common-mode voltage V.sub.CM.sub._.sub.REF and the difference between the reference voltage V.sub.REF and the common-mode voltage V.sub.CM.sub._.sub.REF remain substantially unchanged (i.e., 0.25 VDD). Setting the reference voltage V.sub.REF to ground has the following advantages: (1) a unity gain buffer is saved to effectively reduce the circuit area; (2) ground provides a greater driving capability than any electric potential other than ground.

[0032] FIG. 6 is a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention. The operational stage 600 includes a sub ADC 610, a decoder 620, and an MDAC. The MDAC is the circuit besides the sub ADC 610 and the decoder 620. The operations of the sub ADC 610 and the decoder 620 are the same as or similar to those of the conventional sub ADC 112 and decoder 114, respectively, and are thus omitted for brevity. The MDAC includes an operational amplifier 632, capacitors C0a, C1a, C1a, C0b, C1b, C1b, switches S0a to S4a, S1a, S4a, and switches S0b to S4b, S1b, and S4b. The capacitance values of the capacitor C0a and the capacitor C0b are substantially the same. The MDAC operates alternately in the sampling phase and the amplification phase. In the sampling phase, the switches S0a, S1a, S1a, S2a, S0b, S1b, S1b, S2b are turned on, and the remaining switches are turned off. In the amplification phase, the switches S3a, S4a, S4a, S3b, S4b, S4b are turned on, and the remaining switches are turned off.

[0033] The connections and operations of the capacitors C0a, C0b, C1a, C1b are similar to the capacitors C0a, C0b, C1a, C1b of FIG. 4, respectively. In this embodiment, however, the reference voltage V.sub.CM.sub._.sub.OPI is substantially equal to the DC voltage V.sub.X of the input terminal of the operational amplifier 632 in the amplification phase because the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA (i.e., the voltage V.sub.CM.sub._.sub.REF is not shifted).

[0034] One end of the capacitor C1a (or C1b) is coupled to the reference voltage V.sub.CM.sub._.sub.OPI through the switch S2a (or S2b) in the sampling phase, and is coupled to an input terminal of the operational amplifier 632 but not to the reference voltage V.sub.CM.sub._.sub.OPI in the amplification phase; the other end of the capacitor C1a (or C1b) receives the input signal V.sub.in.sup.+ (or V.sub.in.sup.) through the switch S1a (or S1b) in the sampling phase, and receives the common-mode voltage V.sub.CM.sub._.sub.REF of the reference voltage V.sub.REF+ and the reference voltage V.sub.REF through the switch S4a (or S4b) in the amplification phase.

[0035] In this embodiment, the reference voltage V.sub.REF+ and the reference voltage V.sub.REF do not necessarily satisfy V.sub.REF+V.sub.REF=0.5V.sub.pp.sub._.sub.max (V.sub.pp.sub._.sub.max is the allowed maximum peak-to-peak value of the differential input signal V.sub.in), but the common-mode voltage V.sub.CM.sub._.sub.REF of the reference voltage V.sub.REF+ and the reference voltage V.sub.REF is still substantially equal to the common-mode voltage V.sub.CM.sub._.sub.PGA of the differential input signal V.sub.in. For example, if the differential input signal V.sub.in is limited between VDD and ground (i.e., V.sub.pp.sub._.sub.max=VDD0=VDD), then the difference between the voltages V.sub.REF+ and V.sub.REF can be designed to be equal to V.sub.pp.sub._.sub.max=VDD (e.g., V.sub.REF+=VDD and V.sub.REF=0), and V.sub.CM.sub._.sub.REF is still substantially equal to V.sub.CM.sub._.sub.PGA=0.5VDD. In this embodiment, since the common-mode voltage V.sub.CM.sub._.sub.REF of the reference voltage V.sub.REF+ and the reference voltage V.sub.REF is still substantially equal to the common-mode voltage V.sub.CM.sub._.sub.PGA of the differential input signal V.sub.in, the reference voltage V.sub.CM.sub._.sub.OPI is substantially equal to the DC voltage V.sub.X of the input terminal of the operational amplifier 632 in the amplification phase.

[0036] In response to the changes in the reference voltage V.sub.REF+ and the reference voltage V.sub.REF, the capacitance values of the capacitors C1a, C1a, C1b, and C1b need to be adjusted accordingly. The sum of the capacitance values of the capacitors C1a (or C1b) and C1a (or C1b) is substantially equal to the capacitance value of the capacitor C0a (or C0b). The ratio of the capacitance value of the capacitor C1a to that of the capacitor C1a (or C1b to C1b) is related to (V.sub.REF+V.sub.REF)/V.sub.pp.sub._.sub.max. More specifically, if the capacitance value of the capacitor C0a (or C0b) is C, the capacitance value of the capacitor C1a (or C1b) is XC (0<X<1), and the capacitance value of the capacitor C1a (or C1b) is YC (0<Y<1), then X+Y is substantially equal to 1, and X=0.5V.sub.pp.sub._.sub.max/(V.sub.REF+V.sub.REF). That is, when (V.sub.REF+V.sub.REF) is R times V.sub.pp.sub._.sub.max, X=R. In one example, when V.sub.pp.sub._.sub.max=VDD0=VDD, V.sub.REF+=VDD, and V.sub.REF=0 (V.sub.CM.sub._.sub.REF=(VDD+0)/2=0.5VDD=V.sub.CM.sub._.sub.PGA), R=(VDD0)/VDD=1, X=R=0.5, and Y=1X=0.5. In another example, when V.sub.pp.sub._.sub.max=VDD0=VDD, V.sub.REF+=0.9VDD, and V.sub.REF=0.1VDD (V.sub.CM.sub._.sub.REF=(0.9VDD+0.1VDD)/2=0.5VDD=V.sub.CM.sub._.sub.PGA), R=(0.9VDD0.1VDD)/VDD=0.8, X=R=0.625, and Y=1X=0.325.

[0037] With the circuit design of FIG. 6, the difference between the reference voltage V.sub.REF+ and the reference voltage V.sub.REF can be arbitrary, rather than having to be substantially equal to 0.5 times the allowed maximum peak-to-peak value V.sub.pp.sub._.sub.max of the differential input signal V.sub.in. Therefore, in some embodiments, the reference voltage V.sub.REF can be scaled to ground.

[0038] In summary, in order to increase the design flexibility of the MDAC or the pipelined ADC employing same, the present invention proposes the embodiments of FIG. 4 and FIG. 6 that respectively enable shift and scaling of the reference voltage (V.sub.REF+ and V.sub.REF) for the MDAC. When one of the reference voltages is shifted or scaled to ground, a unity gain buffer can be omitted to thereby effectively reduce the circuit area.

[0039] The foregoing voltage level shift and scaling operations can be implemented at the same time, and FIG. 7 shows the embodied circuit. The circuit and operation of the operational stage 700 are similar to the operational stage 600, except that the reference voltage V.sub.CM.sub._.sub.OPI to which the capacitor in FIG. 6 couples in the sampling phase is substantially equal to the DC voltage V.sub.X of the input terminal of the operational amplifier 632 in the amplification phase, whereas the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S to which the capacitor in FIG. 7 couples in the sampling phase is not equal to the DC voltage V.sub.X of the input terminal of the operational amplifier 632 in the amplification phase. The reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S can be designed as

[00008]$V_{\mathrm{CM\_OPI}.Math.\mathrm{\_S}}=V_X+\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}},$

where V.sub.CM=V.sub.CM.sub._.sub.PGAV.sub.CM.sub._.sub.REF.

[0040] FIG. 8 is a circuit diagram of one operational stage of a 2.5-bit pipelined ADC according to another embodiment of the present invention. The operational stage 800 includes a sub ADC 810, a decoder 820, and an MDAC. The MDAC is the circuit besides the sub ADC 810 and the decoder 820. The operations of the sub ADC 810 and decoder 820 are the same as or similar to those of the conventional sub ADC 112 and decoder 114, respectively, and are thus omitted for brevity. The MDAC operates alternately in the sampling phase and the amplification phase. FIG. 8 depicts only a part of the MDAC, that is, the partial circuit coupled to one of the input terminals of the operational amplifier 832. Those skilled in the art can understand the circuitry of the rest of the MDAC of FIG. 8 based on the disclosures of FIG. 6 to FIG. 8. Based on the disclosures of FIG. 6 to FIG. 8, those skilled in the art can also understand the circuit and operation details when the present invention is applied to a higher-order pipelined ADC.

[0041] In comparison with the operational stages 600 and 700, the operational stage 800 further includes capacitors C2a, C2a, C3a, C3a, and capacitors C2b, C2b, C3b, C3b (not shown). The capacitors C2b, C2b, C3b, C3b are coupled to the other input terminal of the operational amplifier 832. The capacitors C1a to C3a (or C1b to C3b, not shown) receive the input signal V.sub.in.sup.+ (or V.sub.in.sup., not shown) through the switch group S1A (or S1B, not shown), and receive the output voltage(s) of the decoder 820 through the switch group S4A (or S4B, not shown). The capacitor C1a to C3a (or C1b to C3b, not shown) receives the input signal V.sub.in.sup.+ (or V.sub.in.sup., not shown) through the switch group S1A (or S1B, not shown), and coupled to the common-mode voltage V.sub.CM.sub._.sub.REF of the reference voltage V.sub.REF+ and the reference voltage V.sub.REF through the switch group S4A (or S4B, not shown). The capacitors C1a to C3a and C1a to C3a (or C1b to C3b and C1b to C3b, not shown) are coupled to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S through the switch S2a (or S2b, not shown). The three switches in each of the switch groups S1A, S1A, S4A, S4A (or S1B, S1B, S4B, S4B, not shown) are simultaneously turned on or off, and the switching operations of the switch groups S1A, S1A, S4A, S4A (or S1B, S1B, S4B, S4B, not shown) are the same as those of the switches S1a, S1a, S4a, S4a (or S1b, S1b, S4b, S4b) of FIG. 6 and FIG. 7, respectively, and thus omitted for brevity.

[0042] If the capacitance value of the capacitor C0a is C, the capacitance value of the capacitor C1a is XC (0<X<1), and the capacitance value of the capacitor C1a is YC (0<Y<1), then X+Y is substantially equal to 1, and X=0.5V.sub.pp.sub._.sub.max/(V.sub.REF+V.sub.REF). The same applies to the capacitor pairs (C2a, C2a) and (C3a, C3a). When the voltage V.sub.CM.sub._.sub.REF is substantially equal to the voltage V.sub.CM.sub._.sub.PGA, the DC voltage V.sub.X of the input terminal of the operational amplifier 832 in the amplification phase is substantially equal to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S. When the voltage V.sub.CM.sub._.sub.REF is not equal to the voltage V.sub.CM.sub._.sub.PGA, the DC voltage V.sub.X of the input terminal of the operational amplifier 832 in the amplification phase is not equal to the reference voltage V.sub.CM.sub._.sub.OPI.sub._.sub.S, that is,

[00009]$V_{\mathrm{CM\_OPI}.Math.\mathrm{\_S}}=V_X+\frac{N-1}{N}.Math..Math..Math.V_{\mathrm{CM}},$

where V.sub.CM=V.sub.CM.sub._.sub.PGAV.sub.CM.sub._.sub.REF and N=4 for a 2.5-bit pipelined ADC. In one embodiment, the reference voltage V.sub.REF may be ground.

[0043] Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method invention through the disclosure of the device invention, repeated and redundant description is thus omitted. Furthermore, the shape, size, and ratio of any element in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention. In addition, although the foregoing embodiments are exemplified by a 1.5-bit or 2.5-bit pipelined ADC, the present invention is not limited thereto. Those skilled in the art can apply the present invention to other pipelined ADCs of different bits according to the disclosure of the present invention.

[0044] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.