OVERCURRENT PROTECTION CIRCUIT AND POWER AMPLIFIER INCLUDING OVERCURRENT PROTECTION CIRCUIT

Abstract

An overcurrent protection circuit includes a variable voltage source configured to generate a first voltage which that in response to a variable current; an amplifier comprising a first input terminal to which the first voltage is applied; and a limit current source connected to a second input terminal of the amplifier and configured to generate a limit current corresponding to the first voltage.

Claims

1. An overcurrent protection circuit comprising: a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier comprising a first input terminal to which the first voltage is applied; and a limit current source connected to a second input terminal of the amplifier and configured to generate a limit current corresponding to the first voltage.

2. The overcurrent protection circuit of claim 1, wherein the variable voltage source comprises: a first transistor and a second transistor connected to each other in a current mirror structure; a variable current source connected between a first terminal of the first transistor and a ground and configured to generate the variable current; and a first resistor connected between a first terminal of the second transistor and the ground.

3. The overcurrent protection circuit of claim 2, wherein a voltage of the first terminal of the second transistor is the first voltage.

4. The overcurrent protection circuit of claim 1, wherein the limit current source is further connected to an output terminal of the amplifier, and a voltage of the output terminal of the amplifier is a second voltage that varies in response to the variable current.

5. The overcurrent protection circuit of claim 4, wherein the limit current source comprises: a first transistor comprising a control terminal to which the second voltage is applied, and a first terminal connected to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor comprising a control terminal to which the second voltage is applied, and a first terminal that outputs the limit current.

6. The overcurrent protection circuit of claim 4, wherein the limit current source comprises: a first transistor comprising a control terminal to which the second voltage is applied; a second transistor comprising a first terminal connected to a first terminal of the first transistor, and a second terminal connected to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor comprising a control terminal to which the second voltage is applied; and a fourth transistor comprising a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.

7. The overcurrent protection circuit of claim 4, wherein the limit current varies in response to the first voltage and the second voltage.

8. The overcurrent protection circuit of claim 1, wherein the limit current is generated to be supplied to a bias circuit configured to bias a power transistor.

9. The overcurrent protection circuit of claim 1, wherein the amplifier is an operational amplifier, the first input terminal of the amplifier is an inverting terminal of the operational amplifier, and the second input terminal of the amplifier is a non-inverting terminal of the operational amplifier.

10. A power amplifier comprising: a power transistor configured to amplify an input radio-frequency (RF) signal; a bias circuit configured to supply a bias current to the power transistor; and an overcurrent protection circuit configured to supply a limit current to the bias circuit to prevent an overcurrent from flowing in the power transistor, wherein the overcurrent protection circuit comprises: a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier comprising a first input terminal to which the first voltage is applied; and a limit current source connected to a second input terminal of the amplifier and configured to generate the limit current so that the limit current corresponds to the first voltage.

11. The power amplifier of claim 10, wherein the variable voltage source comprises: a variable current source configured to generate the variable current; and a current mirror configured to generate a first current based on the variable current, generate the first voltage based on the first current so that the first voltage varies in response to the variable current.

12. The power amplifier of claim 10, wherein the limit current source is further connected to an output terminal of the amplifier, and a voltage of the output terminal of the amplifier is a second voltage that varies in response to the variable current.

13. The power amplifier of claim 12, wherein the limit current source comprises: a first transistor comprising a control terminal to which the second voltage is applied, and a first terminal connected to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor comprising a control terminal to which the second voltage is applied, and a first terminal that outputs the limit current.

14. The power amplifier of claim 12, wherein the limit current source comprises: a first transistor comprising a control terminal to which the second voltage is applied; a second transistor comprising a first terminal connected to a first terminal of the first transistor, and a second terminal connected to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor comprising a control terminal to which the second voltage is applied; and a fourth transistor comprising a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.

15. The power amplifier of claim 12, wherein the limit current varies in response to the first voltage and the second voltage.

16. An overcurrent protection circuit comprising: a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier comprising a first input terminal to which the first voltage is applied; and a limit current source configured to generate a limit current corresponding to the first voltage, and apply a voltage corresponding to the limit current to a second input terminal of the amplifier.

17. The overcurrent protection circuit of claim 16, wherein the variable voltage source comprises: a first transistor and a second transistor connected to each other in a current mirror structure; a variable current source connected between a first terminal of the first transistor and a ground and configured to generate the variable current; and a first resistor connected between a first terminal of the second transistor and the ground.

18. The overcurrent protection circuit of claim 17, wherein a voltage of the first terminal of the second transistor is the first voltage.

19. The overcurrent protection circuit of claim 16, wherein the limit current source comprises: a first transistor comprising a control terminal connected to an output terminal of the amplifier, and a first terminal providing the voltage corresponding to the limit current to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor comprising a control terminal connected to the output terminal of the amplifier, and a first terminal that outputs the limit current.

20. The overcurrent protection circuit of claim 16, wherein the limit current source comprises: a first transistor comprising a control terminal connected to an output terminal of the amplifier; a second transistor comprising a first terminal connected to a first terminal of the first transistor, and a second terminal providing the voltage corresponding to the limit current to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor comprising a control terminal connected to the output terminal of the amplifier; and a fourth transistor comprising a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a view illustrating a power amplifier according to one embodiment.

[0030] FIG. 2 is a view illustrating an example of a bias circuit of the power amplifier of FIG. 1 according to one embodiment.

[0031] FIG. 3 is a view illustrating an overcurrent protection circuit of the power amplifier of FIG. 1 according to one embodiment.

[0032] FIG. 4 is a circuit diagram illustrating an internal configuration of the overcurrent protection circuit of FIG. 3 according to one embodiment.

[0033] FIG. 5 is a view illustrating an example of a transistor M4 of the circuit diagram of FIG. 4 according to one embodiment.

[0034] FIG. 6 is a graph illustrating a relationship between a voltage V.sub.C and a limit current I.sub.LIM for the transistor M4 of FIG. 5 according to one embodiment.

[0035] FIG. 7 is a view illustrating a limit current source of the overcurrent protection circuit of FIG. 4 according to another embodiment.

[0036] Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

[0037] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

[0038] The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

[0039] Throughout the specification, when an element, such as a layer, region, or substrate, is described as being on, connected to, or coupled to another element, it may be directly on, connected to, or coupled to the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being directly on, directly connected to, or directly coupled to another element, there can be no other elements intervening therebetween.

[0040] As used herein, the term and/or includes any one and any combination of any two or more of the associated listed items.

[0041] Although terms such as first, second, and third may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

[0042] Spatially relative terms such as above, upper, below, and lower may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being above or upper relative to another element will then be below or lower relative to the other element. Thus, the term above encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated by 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

[0043] The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms comprises, includes, and has specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

[0044] Through the specification, the RF signal may have a format according to any known wireless and wired protocols including Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G or higher, but is not limited thereto.

[0045] FIG. 1 is a view illustrating a power amplifier according to one embodiment.

[0046] As illustrated in FIG. 1, a power amplifier 1000 according to one embodiment includes an input matching network 100, a power transistor 200, an output matching network 300, a bias circuit 400, a reference current generating circuit 500, and an overcurrent protection circuit 600.

[0047] The input matching network 100 is connected to an input terminal (a base B) of the power transistor 200 and performs impedance matching between an input RF (radio-frequency) signal RF.sub.IN and the power transistor 200. The output matching network 300 is connected to an output terminal (a collector C) of the power transistor 200 and performs impedance matching between an output RF signal RF.sub.OUT and a next stage (that is, a next stage of the power amplifier). The input matching network 100 and the output matching network 300 may be implemented by a combination of one or more components selected from resistors, inductors, and capacitors.

[0048] The power transistor 200 amplifies the power of the RF signal RF.sub.IN input to the input terminal (the base B) and then outputs the amplified power to the output terminal (the collector C). That is, an RF signal RF.sub.IN to be amplified is input to the base B of the power transistor 200, and the collector C of the power transistor 200 outputs an amplified RF signal RF.sub.OUT. An emitter E of the power transistor 200 may be connected to a ground, and even though it is not illustrated in FIG. 1, a resistor may be additionally connected between the emitter E of the power transistor 200 and the ground. The collector C of the power transistor 200 is connected to a power source voltage V.sub.CC and the power transistor 200 operates by the power source voltage V.sub.CC. In FIG. 1, a current flowing through the output terminal (that is, the collector C) of the power transistor 200 is denoted by I.sub.CC. The current I.sub.CC is an output current of the power amplifier 1000. The collector C of the power transistor 200 may be connected to the power source voltage V.sub.CC through an inductor (not illustrated in FIG. 1) that serves as an RF choke.

[0049] In an abnormal state, in some cases, the current I.sub.CC excessively increases. Examples of an abnormal state may be a case when a load impedance of the power transistor 200 significantly fluctuates, and a case when a battery providing the power source voltage V.sub.CC is unstable. When the current I.sub.CC excessively increases, the power transistor 200 may be damaged or destroyed. Hereinafter, when the current I.sub.CC excessively increases, it is referred to as an abnormal state, and when the current I.sub.CC does not excessively increase, it is referred to as a normal state. In order to prevent the abnormal state, the overcurrent protection circuit 600 according to one embodiment supplies a limit current I.sub.LIM to the bias circuit 400 to protect the power transistor 200 from an overcurrent.

[0050] The power transistor 200 may be implemented by various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Furthermore, in FIG. 1, the power transistor 200 is denoted as an N-type, but may be replaced with a P-type.

[0051] A coupling capacitor C.sub.C is connected to the input terminal (the base B) of the power transistor 200. The coupling capacitor C.sub.C performs a function of removing (blocking) a direct current (DC) component from the RF signal RF.sub.IN.

[0052] The bias circuit 400 is supplied with a reference current I.sub.REF from the reference current generating circuit 500, and is supplied with a limit current I.sub.LIM from the overcurrent protection circuit 600. The bias circuit 400 generates a bias current I.sub.BIAS needed by the power transistor 200 using the reference current I.sub.REF and the limit current I.sub.LIM. The bias current I.sub.BIAS is supplied to the input terminal (the base B) of the power transistor 200 and a bias level (a bias point) of the power transistor 200 is set by the bias current I.sub.BIAS. According to one embodiment, a maximum value of the bias current I.sub.BIAS is limited by the limit current I.sub.LIM, as will be described in more detail below.

[0053] The reference current generating circuit 500 generates a reference current I.sub.REF and supplies the reference current to the bias circuit 400. As one example, the reference current generating circuit 500 generates different reference currents I.sub.REF according to a power mode of the power amplifier 1000. When the power mode is a high power mode, the reference current generating circuit 500 generates a reference current I.sub.REF HPM. When the power mode is a low power mode, the reference current generating circuit 500 generates a reference current I.sub.REF_LPM. A magnitude of the reference current I.sub.REF HPM may be larger than a magnitude of the reference current I.sub.REF_LPM. In any event, the method of generating the reference current I.sub.REF by the reference current generating circuit 500 is known to those skilled in the art, and accordingly a detailed description thereof will be omitted.

[0054] The overcurrent protection circuit 600 according to one embodiment generates the limit current I.sub.LIM and supplies the generated limit current I.sub.LIM to the bias circuit 400. As one example, the overcurrent protection circuit 600 may generate different limit currents I.sub.LIM depending on the normal state or the abnormal state of the power amplifier 1000. In the normal state, the overcurrent protection circuit 600 generates a normal limit current I.sub.LIM_NS in accordance with the bias circuit 400. That is, in the normal state, the overcurrent protection circuit 600 generates a normal limit current I.sub.LIM_NS that is proportional to a need of the bias circuit 400. Furthermore, in the abnormal state, the overcurrent protection circuit 600 generates a limit current I.sub.LIM that does not exceed an abnormal limit current I.sub.LIM_ABS. That is, in the abnormal state, the overcurrent protection circuit 600 may generate a limit current I.sub.LIM that does not exceed the abnormal limit current I.sub.LIM_ABS regardless of the need of the bias circuit 400. In other words, the limit current I.sub.LIM does not exceed the abnormal limit current I.sub.LIM_ABS. Accordingly, a maximum range of the bias current I.sub.BIAS of the bias circuit 400 is limited and the power amplifier 1000 is protected from an overcurrent.

[0055] FIG. 2 is a view illustrating an example of a bias circuit of the power amplifier of FIG. 1 according to one embodiment.

[0056] As illustrated in FIG. 2, the bias circuit 400 includes a transistor T1, a transistor T2, a transistor T3, and a resistor R1.

[0057] The transistors T1 to T3 may be implemented by various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Furthermore, in FIG. 2, the transistors T1 to T3 are denoted as an N-type, but may be replaced with a P-type.

[0058] A base and a collector of the transistor T1 are connected to each other in a diode-connected structure, and the collector of the transistor T1 is connected to a current source I.sub.REF via the resistor R1. The transistor T1 sinks a current 12 from the current source I.sub.REF. The reference current generating circuit 500 supplies the reference current I.sub.REF to the bias circuit 400 so that in FIG. 2, the reference current generating circuit 500 is denoted as the current source I.sub.REF.

[0059] A base and a collector of the transistor T2 are connected to each other in a diode-connected structure, and the collector of the transistor T2 is connected to an emitter of the transistor T1. An emitter of the transistor T2 is connected to the ground.

[0060] A collector of the transistor T3 is connected to a current sourceI.sub.LIM and a base of the transistor T3 is connected to the base of the transistor T1. Furthermore, an emitter of the transistor T3 is connected to the input terminal (the base B) of the power transistor 200 and supplies the bias current I.sub.BIAS to the power transistor 200. The overcurrent protection circuit 600 supplies the limit current I.sub.LIM to the bias circuit 400 so that in FIG. 2, the overcurrent protection circuit 600 is denoted as the current source I.sub.LIM.

[0061] The reference current I.sub.REF is divided into a current 11 and the current 12, and the current 11 is input to the base of the transistor T3. Accordingly, the bias current I.sub.BIAS is equal to a sum of the limit current I.sub.LIM and the current 11. The bias current I.sub.BIAS is the base current of the power transistor 200, so that the bias current I.sub.BIAS and the current I.sub.CC have a relationship defined by the following Equation 1.

[00001]$\begin{array}{cc}{I}_{\mathrm{BIAS}}=\frac{I_{\mathrm{CC}}}{?}& \left(1\right)\end{array}$

[0062] In Equation 1, ? is a common-emitter current gain of the power transistor 200.

[0063] As described above, in the abnormal state, the value of the current I.sub.CC increases. Referring to Equation 1, as the value of the current I.sub.CC increases, a value of the bias current I.sub.BIAS also increases. Therefore, the increase of the limit current I.sub.LIM is needed. In this case, the overcurrent protection circuit 600 according to one embodiment is designed so that the limit current I.sub.LIM does not exceed the abnormal limit current I.sub.LIM_ABS. The overcurrent protection circuit 600 that performs the above-described operation will be described in more detail below.

[0064] FIG. 3 is a view illustrating an overcurrent protection circuit of the power amplifier of FIG. 1 according to one embodiment.

[0065] As illustrated in FIG. 3, the overcurrent protection circuit 600 according to one embodiment includes a variable voltage source 610, an amplifier 620, and a limit current source 630.

[0066] The variable voltage source 610 generates and outputs a voltage V.sub.A that fluctuates in response to an internal variable current source I.sub.VAR (see FIG. 4).

[0067] The amplifier 620 receives the voltage V.sub.A output from the variable voltage source 610 through an inverting terminal (?). That is, the voltage V.sub.A is applied to the inverting terminal (?) of the amplifier 620. A voltage V.sub.B is output from the limit current source 630 and is applied to a non-inverting terminal (+) of the amplifier 620. The amplifier 620 outputs a voltage V.sub.OUT from an output terminal of the amplifier 620, and the voltage V.sub.OUT is applied to the limit current source 630. The amplifier 620 may be an operational amplifier (OP AMP). The voltage V.sub.B may be set to be equal to the voltage V.sub.A by the operation of the amplifier 620. Furthermore, by the operation of the amplifier 620, the voltage V.sub.OUT may be set so that the voltage V.sub.A and the voltage V.sub.B become the same voltage. The voltage V.sub.A is variable so that the voltage V.sub.OUT is also variable, i.e., it fluctuates.

[0068] The limit current source 630 generates the limit current I.sub.LIM in response to the voltage V.sub.OUT applied from the amplifier 620 and the voltage V.sub.B applied to the amplifier 620. The limit current I.sub.LIM generated in the limit current source 630 is supplied (applied) to the bias circuit 400.

[0069] FIG. 4 is a circuit diagram illustrating an internal configuration of the overcurrent protection circuit of FIG. 3 according to one embodiment.

[0070] As illustrated in FIG. 4, the variable voltage source 610 according to one embodiment includes a transistor M1, a transistor M2, a variable current source I.sub.VAR, and a resistor R3. Furthermore, the limit current source 630 according to one embodiment includes a transistor M3, a transistor M4, and a resistor R4.

[0071] In FIG. 4, the transistor M1, the transistor M2, the transistor M3, and the transistor M4 may be various transistors such as a field-effect transistor (FET) and a bipolar transistor. Furthermore, in FIG. 4, the transistor M1, the transistor M2, the transistor M3, and the transistor M4 are denoted as P-types, but may also be N-types. In the following description, for the sake of convenience, the transistor M1, the transistor M2, the transistor M3, and the transistor M4 are assumed to be FETs, but may be replaced with another type of transistor. A gate (control terminal) of the transistor serves as a control terminal so that the term 'control terminal is used therefor. A source of the transistor is one terminal of the transistor so that the term first terminal or second terminal may be used therefore. Furthermore, a drain of the transistor is another terminal of the transistor so that the term second terminal or first terminal may be used therefor.

[0072] The source of the transistor M1 is connected to a power source voltage V.sub.DD and a gate (control terminal) and a drain of the transistor M1 are connected to each other. One end of the variable current source I.sub.VAR is connected to the drain of the transistor M1 and the other end of the variable current source I.sub.VAR is connected to the ground. A gate (control terminal) of the transistor M2 is connected to the gate (control terminal) of the transistor M1, and a source of the transistor M2 is connected to the power source voltage V.sub.DD. The resistor R3 is connected between a drain of the transistor M2 and the ground. The transistor M1 and the transistor M2 are connected to each other in a current mirror structure. In FIG. 4, a voltage at a junction between the drain of the transistor M2 and the resistor R3 is denoted as a voltage V.sub.A. The power source voltage V.sub.DD is output from a regulator circuit, for example, a low-dropout (LDO) regulator circuit.

[0073] The variable current source I.sub.VAR according to one embodiment generates and outputs a variable current I.sub.VAR. As an example, the variable current source I.sub.VAR may generate a variable current I.sub.VAR having different current values depending on a power mode of the power amplifier 1000. When the power mode is a high power mode, the variable current source I.sub.VAR may generate a current I.sub.VAR_HPM. When the power mode is a low power mode, the variable current source I.sub.VAR may generate a current I.sub.VAR_LPM. A magnitude of the current I.sub.VAR_HPM may be larger than a magnitude of the current I.sub.VAR_LPM.

[0074] Since the variable current source I.sub.VAR has a variable current value, a voltage V.sub.A value is also variable (fluctuates). The transistor M1 and the transistor M2 have a current mirror structure so that a drain current I.sub.D2 of the transistor M2 is proportional to a size ratio of the transistor M1 and the transistor M2 (a ratio of a channel width and a channel length). That is, the drain current I.sub.D2 of the transistor M2 has a relationship defined by the following Equation 2.

I.sub.D2=K1?I.sub.VAR(2)

[0075] In Equation 2, K1 refers to a size ratio of the transistor M1 and the transistor M2. As an example, when a size of the transistor M1 is equal to a size of the transistor M2, K1 is 1. When K is 1, the drain current I.sub.D2 of the transistor M2 is equal to the current I.sub.VAR generated by the variable current source I.sub.VAR.

[0076] The voltage V.sub.A is defined by the following Equation 3.

V.sub.A=R3?I.sub.D2=R3.Math.K1.Math.I.sub.VAR(3)

[0077] Referring to Equation 3, the voltage V.sub.A may vary (fluctuate) according to a value of the variable current I.sub.VAR. The voltage V.sub.B is set to be equal to the voltage V.sub.A by the amplifier 620. Furthermore, by the operation of the amplifier 620, the voltage V.sub.OUT may be set so that the voltage V.sub.A and the voltage V.sub.B become the same voltage. Accordingly, the voltage V.sub.OUT may also vary (fluctuate) according to the value of the variable current I.sub.VAR.

[0078] Referring to FIG. 4, the gate (control terminal) of the transistor M3 and the gate (control terminal) of the transistor M4 are connected to the output terminal of the amplifier 620. That is, the voltage V.sub.OUT is applied to the gate (control terminal) of the transistor M3 and the gate (control terminal) of the transistor M4. A source of the transistor M3 and a source of the transistor M4 are connected to a power source voltage V.sub.BAT. As an example, the power source voltage V.sub.BAT may be a battery voltage. A drain of the transistor M3 is connected to the non-inverting terminal (+) of the amplifier 620. The resistor R4 is connected between the non-inverting terminal (+) (that is, the drain of the transistor M3) of the amplifier 620 and the ground. A drain current I.sub.D3 of the transistor M3 is defined by the following Equation 4.

[00002]$\begin{array}{cc}{I}_{D3}=\frac{V_B}{R4}=\frac{R3}{R4}.Math.K1.Math.I_{\mathrm{VAR}}& \left(4\right)\end{array}$

[0079] The voltage V.sub.B in Equation 4 is equal to the voltage V.sub.A, so that the voltage V.sub.B in Equation 4 may be replaced by Equation 3 for the voltage V.sub.A.

[0080] In FIG. 4, a drain current of the transistor M4 is the above-described limit current I.sub.LIM. That is, a drain of the transistor M4 may supply the limit current I.sub.LIM to the bias circuit 400. The gate (control terminal) of the transistor M3 and the gate (control terminal) of the transistor M4 are connected to each other and to the output terminal of the amplifier 620. Accordingly, when the transistor M3 and the transistor M4 operate in a saturation region, the transistor M3 and the transistor M4 operate as a current mirror. Accordingly, the limit current I.sub.LIM is defined by the following Equation 5.

I.sub.LIM=K2?I.sub.D3(5)

[0081] In Equation 5, K2 refers to a size ratio of the transistor M3 and the transistor M4. As one example, when the size of the transistor M4 is 20 times larger than the size of the transistor M3, K2 is 20.

[0082] In Equation 5, instead of the drain current I.sub.D3 of the transistor M3, when Equation 4 is applied, the limit current I.sub.LIM is defined by the following Equation 6.

[00003]$\begin{array}{cc}{I}_{\mathrm{LIM}}=\frac{R3}{R4}.Math.K1.Math.K2.Math.I_{\mathrm{VAR}}& \left(6\right)\end{array}$

[0083] In Equation 6, values of K1 and K2 and values of resistances R3 and R4 may be set in advance according to a design of the power amplifier 1000. The limit current I.sub.LIM may have different values depending on the value of the variable current I.sub.VAR. As described above, the variable current I.sub.VAR has different values depending on the power mode of the power amplifier 1000 so that value of the limit current I.sub.LIM also has different values depending on the power mode.

[0084] Referring to Equation 6, the value of the limit current I.sub.LIM is affected by the values of the resistances R3 and R4. In the overcurrent protection circuit 600 according to one embodiment, the resistors R3 and R3 are manufactured by the same process so that the limit current I.sub.LIM may be less affected by deviations in the values of the resistors.

[0085] In the limit current source 630, the transistor M3 may be designed to operate in the saturation region at all times. In contrast, the transistor M4 may operate in different modes depending on a drain voltage V.sub.C of the transistor M4. The drain voltage V.sub.C of the transistor M4 may be a collector voltage of the transistor T3 in FIG. 2. Accordingly, the transistor M4 may operate in different modes depending on a normal state and an abnormal state of the power amplifier 1000.

[0086] As one example, in the normal state, the transistor M4 operates in a triode region, and in the abnormal state, the transistor M4 operates in the saturation region. When the transistor M4 operates in the triode region, the value of the limit current I.sub.LIM may vary in response to the drain voltage V.sub.C of the transistor M4. When the transistor M4 operates in the saturation region, the value of the limit current I.sub.LIM has a value defined by Equation 6. In the abnormal state, the value of the current I.sub.CC increases. In this case, the transistor M4 of the overcurrent protection circuit 600 operates in the saturation region and the value of the limit current I.sub.LIM may have a value defined by Equation 6. That is, the above described abnormal limit current I.sub.LIM_ABS may be designed to have a value defined by Equation 6. By doing this, the overcurrent protection circuit 600 may prevent the damage due to the overcurrent of the power transistor 200.

[0087] According to Equation 3, the voltage V.sub.OUT, which is the output voltage of the output terminal of the amplifier 620, may vary (fluctuate) according to a value of the variable current source I.sub.VAR. The voltage V.sub.OUT is a gate (control terminal) voltage of the transistor M4 so that a headroom of the transistor M4 may expand. That is, in the overcurrent protection circuit 600 according to one embodiment, the gate (control terminal) voltage of the transistor M4 is not fixed, but may vary so that the headroom of the transistor M4 may expand. The headroom refers to a range of a drain-source voltage (Vds) of a transistor to allow the transistor to operate in the saturation region. This will be described below with reference to FIGS. 5 and 6.

[0088] FIG. 5 is a view illustrating an example of a transistor M4 of the circuit diagram of FIG. 4 according to one embodiment. Furthermore, FIG. 6 is a graph illustrating a relationship between a voltage V.sub.C and a limit current I.sub.LIM for the transistor M4 of FIG. 5 according to one embodiment.

[0089] In FIG. 5, it is assumed that the power source voltage V.sub.BAT is 3 V and a gate (control terminal) voltage V.sub.G4 of the transistor M4 between 1 V and 2 V. That is, the value of the variable current I.sub.VAR fluctuates so that as one example, the gate (control terminal) voltage V.sub.G4 (that is, the voltage V.sub.OUT) of the transistor M4 may vary between 1 V and 2 V. In FIG. 6, S610 represents a relationship between the voltage V.sub.C and the limit current I.sub.LIM when the gate (control terminal) voltage V.sub.G4 is 1 V and S620 represents a relationship between the voltage V.sub.C and the limit current I.sub.LIM when the gate (control terminal) voltage V.sub.G4 is 2 V.

[0090] When the gate (control terminal) voltage V.sub.G4 of the transistor M4 is 1 V, if the voltage V.sub.C is equal to or lower than 2 V, the transistor M4 operates in the saturation region. That is, when the voltage V.sub.C has a range of 0 V to 2 V, the transistor M4 operates in the saturation region.

[0091] When the gate (control terminal) voltage V.sub.G4 of the transistor M4 is 2 V, if the voltage V.sub.C is equal to or lower than 3 V, the transistor M4 operates in the saturation region. That is, when the voltage V.sub.C has a range of 0 V to 3 V, the transistor M4 operates in the saturation region. In other words, when the gate (control terminal) voltage V.sub.G4 increases from 1 V to 2 V, a range of the drain-source voltage at which the transistor M4 operates in the saturation region expands. Accordingly, in one embodiment, the headroom of the transistor M4 expands.

[0092] Referring to FIG. 6, a range of the voltage V.sub.C at which the transistor M4 operates in the saturation region in S620 expands by ?V from a range of the voltage V.sub.C at which the transistor M4 operates in the saturation region n S610. That is, in the overcurrent protection circuit 600 according to one embodiment, the gate (control terminal) voltage of the transistor M4 is not fixed, but may fluctuate so that the headroom of the transistor M4 may expand. As described above, the headroom of the transistor M4 expands so that the overcurrent protection circuit 600 according to one embodiment may supply a stable limit current I.sub.LIM to the bias circuit 400. That is, according to one embodiment, the headroom of the transistor M4 used to generate the limit current expands to stably limit the output current of the power amplifier.

[0093] FIG. 7 is a view illustrating a limit current source of the overcurrent protection circuit of FIG. 4 according to another embodiment.

[0094] As illustrated in FIG. 7, a limit current source 630 according to another embodiment is similar to the limit current source 630 of FIG. 4 except that in the limit current source 630 of FIG. 7, a transistor M5 and a transistor M6 are added.

[0095] A source of the transistor M5 is connected to the drain of the transistor M3 so that a drain of the transistor M5 may be connected to the non-inverting terminal (+) of the amplifier 620. A source of the transistor M6 is connected to the drain of the transistor M4 and a limit current I.sub.LIM is output from the drain of the transistor M6. A gate (control terminal) of the transistor M5 and a gate (control terminal) of the transistor M6 are connected to each other, and a power source voltage V.sub.DD1 is applied to the gate (control terminal) of the transistor M5 and the gate (control terminal) of the transistor M6 as a bias voltage.

[0096] That is, the transistor M5 is connected to the transistor M3 in a cascode structure, and the transistor M6 is connected to the transistor M4 in a cascode structure. Due to this cascode structure, a channel resistance of the limit current source 630 of FIG. 7 may be increased as compared with the limit current source 630 of FIG. 4. When the channel resistance is increased, the limit current I.sub.LIM may be less affected by the change in the voltage V.sub.C. The voltage V.sub.C is the collector voltage of the transistor T3 in FIG. 2 so that the limit current source 630 according to another embodiment may supply a stable limit current I.sub.LIM even when the collector voltage V.sub.C of the transistor T3 changes.

[0097] While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and are not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.