SELF-BIASED AMPLIFIER CIRCUIT AND A METHOD FOR CONTROLLING A SELF-BIASED AMPLIFIER CIRCUIT

Abstract

A self-biased amplifier circuit, comprises: an input, wherein the input comprises input transistors forming inverters; bias transistors, wherein a source of each input transistor is connected to a drain of a bias transistor for providing a bias current to the inverters; an output connected to a first output node and/or a second output node; and pairs of transistor switches connected between the first or the second output node and a respective gate of the bias transistors, wherein the pairs of transistor switches are configured to control the self-biased amplifier circuit to assume an active mode or a standby mode.

Claims

1. A self-biased amplifier circuit, comprising: an input, wherein the input comprises a first and a second input node for receiving a first input signal and a second input signal forming a differential input signal, wherein the input comprises a first p-channel metal-oxide-semiconductor (PMOS) input transistor and a first n-channel metal-oxide-semiconductor (NMOS) input transistor forming two complementary input transistors at the first input node and each configured to receive the first input signal at a gate, and wherein the input comprises a second PMOS input transistor and a second NMOS input transistor forming two complementary input transistors at the second input node and each configured to receive the second input signal at a gate, wherein a drain of the first PMOS input transistor and a drain of the first NMOS input transistor are connected to each other to form an inverter defining a first output node therebetween and wherein a drain of the second PMOS input transistor and a drain of the second NMOS input transistor are connected to each other to form an inverter defining a second output node therebetween; at least one PMOS bias transistor and at least one NMOS bias transistor, wherein a source of each of the first and the second PMOS input transistor is connected to a drain of the at least one PMOS bias transistor and wherein a source of each of the first and the second NMOS input transistor is connected to a drain of the at least one NMOS bias transistor for providing a bias current to the inverters; an output connected to at least one of the first output node and the second output node for providing an output signal; and a first and a second transistor switch, wherein the first transistor switch is connected between the first or the second output node and a gate of the at least one PMOS bias transistor, and wherein the second transistor switch is connected between the first or the second output node and a gate of the at least one NMOS bias transistor, wherein the first and the second transistor switches are configured to control the self-biased amplifier circuit to assume an active mode or a standby mode.

2. The self-biased amplifier circuit according to claim 1, wherein the output is connected to the first output node and the second output node for outputting a differential output signal.

3. The self-biased amplifier circuit according to claim 2, wherein the at least one PMOS bias transistor comprises a first PMOS bias transistor and a second PMOS bias transistor and wherein the at least one NMOS bias transistor comprises a first NMOS bias transistor and a second NMOS bias transistor.

4. The self-biased amplifier circuit according to claim 3, further comprising a third and a fourth transistor switch, wherein the first transistor switch is connected between the second output node and the gate of the first PMOS bias transistor, the second transistor switch is connected between the second output node and the gate of the first NMOS bias transistor, the third transistor switch is connected between the first output node and the gate of the second PMOS bias transistor, and the fourth transistor switch is connected between the first output node and the gate of the second NMOS bias transistor.

5. The self-biased amplifier circuit according to claim 1, wherein each transistor switch comprises two complementary transistors comprising a p-type transistor and an n-type transistor, wherein the p-type transistor is configured to receive a first enable signal and the n-type transistor is configured to receive a second enable signal for controlling the self-biased amplifier circuit to assume an active mode or a standby mode.

6. The self-biased amplifier circuit according to claim 5, wherein drains and sources of both complementary transistors in each transistor switch are connected between two common nodes for forming switches between the two common nodes.

7. The self-biased amplifier circuit according to claim 1, wherein the self-biased amplifier circuit is configured to form a clock buffer configured to convert a sinusoidal wave signal received at the input to an amplified signal at the output.

8. The self-biased amplifier circuit according to claim 1, wherein an on-resistance of the first transistor switch, a gate capacitance of the at least one PMOS bias transistor and a parasitic capacitance at a gate node of the at least one PMOS bias transistor are configured to form a low-pass filter.

9. The self-biased amplifier circuit according to claim 1, further comprising at least one first additional transistor switch connected between a supply voltage and the gate of the at least one PMOS bias transistor and at least one second additional transistor switch connected between ground and the gate of the at least one NMOS bias transistor.

10. A method for controlling a self-biased amplifier circuit, said method comprising: receiving a differential input signal at an input of the self-biased amplifier circuit, wherein the input comprises a first and a second input node for receiving a first input signal and a second input signal forming the differential input signal, wherein the input comprises a first p-channel metal-oxide-semiconductor (PMOS) input transistor and a first n-channel metal-oxide-semiconductor (NMOS) input transistor forming two complementary input transistors at the first input node and each configured to receive the first input signal at a gate, and wherein the input comprises a second PMOS input transistor and a second NMOS input transistor forming two complementary input transistors at the second input node and each configured to receive the second input signal at a gate, wherein a drain of the first PMOS input transistor and a drain of the first NMOS input transistor are connected to each other to form an inverter defining a first output node therebetween and wherein a drain of the second PMOS input transistor and a drain of the second NMOS input transistor are connected to each other to form an inverter defining a second output node therebetween; providing a first bias current to the first PMOS input transistor and the second PMOS input transistor by at least one PMOS bias transistor, wherein a source of each of the first and the second PMOS input transistor is connected to a drain of the at least one PMOS bias transistor for receiving the bias current, and providing a second bias current to the first NMOS input transistor and the second NMOS input transistor by at least one NMOS bias transistor, wherein a source of each of the first and the second NMOS input transistor is connected to a drain of the at least one NMOS bias transistor for receiving a bias current; and providing control signals to a first and second transistor switch, wherein the first transistor switch is connected between the first or the second output node and a gate of the at least PMOS bias transistor, and wherein the second transistor switch is connected between the first or the second output node and a gate of the at least one NMOS bias transistor, wherein the control signals provided to the first and the second transistor switches control the self-biased amplifier circuit to assume an active mode or a standby mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above, as well as additional objects, features, and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0050] FIG. 1 is a schematic view of a self-biased clock buffer according to a first embodiment.

[0051] FIG. 2 is a more detailed schematic view of the self-biased clock buffer of the first embodiment.

[0052] FIG. 3a is a schematic view of the self-biased clock buffer of the first embodiment in an active mode.

[0053] FIG. 3b shows input and output signals of the self-biased clock buffer of the first embodiment in the active mode.

[0054] FIG. 4a is a schematic view of the self-biased clock buffer of the first embodiment in a stand-by mode.

[0055] FIG. 4b shows input and output signals of the self-biased clock buffer of the first embodiment in the stand-by mode.

[0056] FIG. 5 is a schematic view of the self-biased clock buffer of the first embodiment considering on-resistance of transistor switches.

[0057] FIG. 6 shows charts illustrating properties of the self-biased clock buffer in dependence of the on-resistance.

[0058] FIG. 7 is a schematic view of the self-biased clock buffer of a second embodiment.

[0059] FIG. 8 is a flow chart of a method.

DETAILED DESCRIPTION

[0060] Referring now to FIG. 1, a self-biased amplifier circuit 100 according to a first embodiment will be disclosed. The self-biased amplifier circuit 100 comprises an input having a first input node 102 and a second input node 104. The self-biased amplifier circuit 100 may thus be configured to receive a differential input signal comprising a first input signal V.sub.inp and a second input signal V.sub.inn. The self-biased amplifier circuit 100 may further be configured to provide a differential output signal at an output having a first output node 106 and a second output node 108.

[0061] The self-biased amplifier circuit 100 may form a self-biased clock buffer 100 configured to convert a sinusoid wave signal received at the input to an amplified wave signal at the output which may approximate a square wave. In the following, the self-biased amplifier circuit 100 will be discussed in relation to forming a self-biased clock buffer 100. However, it should be realized that the self-biased amplifier circuit may be used in other applications, taking a different input signal to provide a different output signal.

[0062] The self-biased clock buffer 100 comprises a first p-channel metal-oxide-semiconductor (PMOS) input transistor 110 and a first n-channel metal-oxide-semiconductor (NMOS) input transistor 112 forming two complementary input transistors at the first input node 102. The first PMOS input transistor 110 is configured to receive the first input signal V.sub.inp at a gate. Also, the first NMOS input transistor 112 is configured to receive the first input signal V.sub.inp at a gate. A drain of the first PMOS input transistor 110 and a drain of the first NMOS input transistor 112 are connected to each other to form an inverter defining the first output node 106 therebetween.

[0063] The self-biased clock buffer 100 further comprises a second PMOS input transistor 114 and a second NMOS input transistor 116 forming two complementary input transistors at the second input node 104. The second PMOS input transistor 114 is configured to receive the second input signal V.sub.inn at a gate. Also, the second NMOS input transistor 116 is configured to receive the second input signal V.sub.inn at a gate. A drain of the second PMOS input transistor 114 and a drain of the second NMOS input transistor 116 are connected to each other to form an inverter defining the second output node 108 therebetween.

[0064] The self-biased clock buffer 100 further comprises bias transistors such that the input transistors are configured to receive bias currents.

[0065] The self-biased clock buffer 100 comprises a first PMOS bias transistor 118 and a second PMOS bias transistor 120. The first PMOS bias transistor 118 comprises a source connected to a positive supply voltage and a drain connected to a source of the first PMOS input transistor 110. The first PMOS input transistor 110 is thus connected to the first PMOS bias transistor 118 so as to receive a bias current.

[0066] The second PMOS bias transistor 120 comprises a source connected to a positive supply voltage and a drain connected to a source of the second PMOS input transistor 114. The second PMOS input transistor 114 is thus connected to the second PMOS bias transistor 120 so as to receive a bias current.

[0067] Also, the source of the first PMOS input transistor 110 is connected to the source of the second PMOS input transistor 114.

[0068] The self-biased clock buffer 100 further comprises a first NMOS bias transistor 122 and a second NMOS bias transistor 124. The first NMOS bias transistor 122 comprises a source connected to negative supply voltage (or ground) and a drain connected to a source of the first NMOS input transistor 112. The first NMOS input transistor 112 is thus connected to the first NMOS bias transistor 122 so as to receive a bias current.

[0069] The second NMOS bias transistor 124 comprises a source connected to negative supply voltage or ground and a drain connected to a source of the second NMOS input transistor 116. The second NMOS input transistor 116 is thus connected to the second NMOS bias transistor 124 so as to receive a bias current.

[0070] Also, the source of the first NMOS input transistor 112 is connected to the source of the second NMOS input transistor 116.

[0071] A gate of each of the bias transistors 118, 120, 122, 124 is connected to an internal node within the clock buffer 100 such that the clock buffer 100 is a self-biased clock buffer 100. The self-biased clock buffer 100 comprises a plurality of transistor switches 126, 128, 130, 132, each transistor switch 126, 128, 130, 132 being connected between the first output node 106 or the second output node 108 and a gate of a respective bias transistor 118, 120, 122, 124. The transistor switches 126, 128, 130, 132 are configured to control the self-biased clock buffer 100 to assume an active mode or a standby mode based on control signals enabling or disabling the transistor switches 126, 128, 130, 132.

[0072] The first transistor switch 126 is connected between the second output node 108 and the gate of the first PMOS bias transistor 118. The second transistor switch 128 is connected between the second output node 108 and the gate of the first NMOS bias transistor 122. The third transistor switch 130 is connected between the first output node 106 and the gate of the second PMOS bias transistor 120. The fourth transistor switch 132 is connected between the first output node 106 and the gate of the second NMOS bias transistor 124.

[0073] Each transistor switch 126, 128, 130, 132 may comprise two complementary transistors comprising a p-type transistor and an n-type transistor. For instance, the first transistor switch 126 comprises the p-type transistor 126a and the n-type transistor 126b. The drains and sources of both complementary transistors in each transistor switch are connected between two common nodes for forming switches between the two common nodes.

[0074] The p-type transistor 126a is configured to receive a first enable signal on a gate of the p-type transistor 126a and the n-type transistor 126b is configured to receive a second enable signal for controlling the self-biased clock buffer 100 to assume an active mode or a standby mode.

[0075] Referring now to FIG. 2, the self-biased clock buffer 100 may optionally further comprise additional transistor switches 134, 136, 138, 140. A first additional transistor switch 134 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the gate of the first PMOS bias transistor 118. A second additional transistor switch 136 may be an n-type transistor switch, having a source connected to negative supply voltage and a drain connected to the gate of the first NMOS bias transistor 122. A third additional transistor switch 138 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the gate of the second PMOS bias transistor 120. A fourth additional transistor switch 140 may be an n-type transistor switch, having a source connected to negative supply voltage and a drain connected to the gate of the second NMOS bias transistor 124.

[0076] The additional transistor switches 134, 138 may be connected to receive the second enable signal. This implies that the additional transistor switches 134, 138 may be on, when the transistor switches 126, 128, 130, 132 are off. This may imply that gate voltage of the first and second PMOS bias transistors 118, 120 may be tied to the supply voltage and independent of instantaneous voltage at the first and second output nodes 106, 108. This ensures that no current can flow through the circuit, and a proper power-down operation is achieved.

[0077] The additional transistor switches 136, 140 may be connected to receive the first enable signal. This implies that the additional transistor switches 136, 140 may be on, when the transistor switches 126, 128, 130, 132 are off. This may imply that gate voltage of the first and second NMOS bias transistors 122, 124 may be constant and independent of instantaneous voltage at the first and second output nodes 106, 108.

[0078] As further shown in FIG. 2, the self-biased clock buffer 100 may optionally further comprise additional transistor switches 142, 144, 146, 148.

[0079] A fifth additional transistor switch 142 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the drains of the first and second PMOS bias transistors 118, 120. A sixth additional transistor switch 144 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the drains of the first and second NMOS bias transistors 122, 124. A seventh additional transistor switch 146 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the first output node 106. An eighth additional transistor switch 148 may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the second output node 108.

[0080] The additional transistor switches 142, 144, 146, 148 may be connected to receive the second enable signal. This implies that the additional transistor switches 142, 144, 146, 148 may be on, when the transistor switches 126, 128, 130, 132 are off. The additional transistor switches 142, 144, 146, 148 may prevent floating voltages of nodes of the self-biased clock buffer 100 in the stand-by mode.

[0081] It should be realized that one or more of the additional transistor switches 142, 144, 146, 148 may alternatively be an NMOS transistor. An NMOS additional transistor switch 142, 144, 146, 148 may be connected to receive the first enable signal instead of the second enable signal

[0082] Referring now to FIGS. 3a-3b, the self-biased clock buffer 100 of FIG. 2 is illustrated in an active mode, wherein the transistor switches being turned off are indicated in grey in FIG. 3a. In the active mode, the first enable signal is low (negative supply voltage, VSS) and the second enable signal is high (positive supply voltage, VDD) as indicated in FIG. 3b illustrating signals within the self-biased clock buffer 100.

[0083] In this case, the transistor switches 126, 128, 130, 132 are turned on. The additional transistor switches 134, 136, 138, 140 and 142, 144, 146, 148 are turned off.

[0084] The self-biased clock buffer 100 may receive a differential signal comprising the first input signal V.sub.inp and the second input signal V.sub.inn forming a sinusoidal wave. Then, output signals V.sub.outp and V.sub.outn at the first output node 106 and the second output node 108, respectively, driven by the self-biased clock buffer 100 will then become a trapezoidal wave with relatively steep slopes.

[0085] Thanks to the arrangement of the transistor switches 126, 128, 130, 132 in the self-biased clock buffer 100, only a small current need to pass through the transistor switches 126, 128, 130, 132, since the transistor switches 126, 128, 130, 132 only need to drive gates of the PMOS bias transistors 118, 120 and the NMOS bias transistors 122, 124, respectively.

[0086] The transistor switches 126, 128, 130, 132 may have a small effect on performance of the self-biased clock buffer 100. The self-biased clock buffer 100 may provide a small average current during operation so as to provide a very low power consumption. The self-biased clock buffer 100 may further be configured to insignificantly affect a duty cycle of the clock signal to maintain a 50% duty cycle or very close to 50% duty cycle. Also, the self-biased clock buffer 100 may be configured to provide a very small clock jitter. Also, the self-biased clock buffer 100 may be configured to provide a slew rate of the output waveform such that the output may be close to an ideal square wave.

[0087] Referring now to FIGS. 4a-4b, the self-biased clock buffer 100 of FIG. 2 is illustrated in a standby mode, wherein the transistor switches being turned off are indicated in grey in FIG. 4a. In the standby mode, the first enable signal is high (positive supply voltage, VDD) and the second enable signal is low (negative supply voltage, VSS) as indicated in FIG. 4b illustrating signals within the self-biased clock buffer 100.

[0088] In this case, the transistor switches 126, 128, 130, 132 are turned off. The additional transistor switches 134, 136, 138, 140 and 142, 144, 146, 148 are turned on.

[0089] Internal nodes of the self-biased clock buffer 100 may then be forcedly tied to positive supply voltage or negative supply voltage. This implies that output signals V.sub.outp and V.sub.outn at the first output node 106 and the second output node 108, respectively, are fixed to positive supply voltage independent of the first input signal V.sub.inp and the second input signal V.sub.inn.

[0090] The self-biased clock buffer 100 may tolerate a large on-resistance of the transistor switches 126, 128, 130, 132 without degradation or insignificant degradation of performance. This implies that a size of the transistor switches 126, 128, 130, 132 may be small. Hence, the self-biased amplifier circuit 100 may be compact.

[0091] Referring now to FIG. 5, a representative architecture of the self-biased clock buffer 100 is shown. During operation, the on-resistance R.sub.on of the transistor switch 132 and gate capacitance of the second NMOS bias transistor 124 and parasitic capacitance C.sub.p at gate node of the second NMOS bias transistor 124 constitute a low-pass filter.

[0092] The differential output voltage of the self-biased clock buffer 100 is ideally a square wave, but when frequency is higher than a cut-off frequency of the low-pass filter, the differential output voltage is averaged to half of positive supply voltage for a 50% duty-cycle at the gate node of the second NMOS bias transistor 124.

[0093] This implies that the bias transistors 118, 120, 122, 124 function as a current source because gate voltage at the bias transistors 118, 120, 122, 124 is nearly a DC voltage and independent of an instantaneous voltage at the first output node 106 and the second output node 108.

[0094] Therefore, since gate capacitance of the bias transistors 118, 120, 122, 124 does not need to be charged and discharged, unnecessary power consumption is eliminated.

[0095] Also, response of rising and falling transitions during voltage transitions is fast because a current to drive an output load capacitance is constant regardless of the output voltage. This results in a steeper slope of the waveform output by the self-biased clock buffer 100.

[0096] If an ideal resistor is implemented as the on-resistance R.sub.on in FIG. 5, some internal waveforms change according to the value of the resistance. For example, a gate voltage and a gate leakage current at the second NMOS bias transistor 124 are settled when the on-resistance R.sub.on is large. This is because the cut-off frequency of the low-pass filter comprised by both of the on-resistance R.sub.on and the parasitic capacitance C.sub.p at the gate node of the second NMOS bias transistor 124 becomes low. Moreover, the output voltage is getting steep when the on-resistance R.sub.on is large.

[0097] Referring now to FIG. 6, some simulation results sweeping the on-resistance R.sub.on are shown. As is clear from FIG. 6, a large on-resistance R.sub.on can obtain low current consumption and fast transition times without any jitter degradation. As a conclusion, the on-resistance R.sub.on is allowed to be large.

[0098] This implies that the transistor switches 126, 128, 130, 132 may have a very small size because the large on-resistance is tolerated. The small size of the transistor switches 126, 128, 130, 132 implies that the transistor switches 126, 128, 130, 132 have small parasitic capacitance, such that low power consumption and fast transition time of the self-biased clock buffer 100 may be provided.

[0099] Referring now to FIG. 7, a self-biased clock buffer 200 according to another embodiment will be described.

[0100] It should be realized that while the self-biased clock buffer 100 may be configured to receive a differential input signal and to output a differential output signal at an output having a first output node 106 and a second output node 108, the self-biased clock buffer 100 may instead provide a single-ended output by only providing output from one of the first or the second output node 106, 108. In the embodiment of the self-biased clock buffer 200, a differential input signal comprising a first input signal V.sub.inp and a second input signal V.sub.inn is illustrated and the self-biased clock buffer 200 is further illustrated to provide a single-ended output from the second output node 208. However, it should be realized that the self-biased clock buffer 200 may alternatively be configured to provide a differential output signal.

[0101] As shown in FIG. 7, the self-biased clock buffer 200 comprises a first PMOS input transistor 210 and a first NMOS input transistor 212 forming two complementary input transistors at the first input node 202. The first PMOS input transistor 210 is configured to receive the first input signal V.sub.inp at a gate. Also, the first NMOS input transistor 212 is configured to receive the first input signal V.sub.inp at a gate. A drain of the first PMOS input transistor 210 and a drain of the first NMOS input transistor 212 are connected to each other to form an inverter defining the first output node 206 therebetween.

[0102] The self-biased clock buffer 200 further comprises a second PMOS input transistor 214 and a second NMOS input transistor 216 forming two complementary input transistors at the second input node 204. The second PMOS input transistor 214 is configured to receive the second input signal V.sub.inn at a gate. Also, the second NMOS input transistor 216 is configured to receive the second input signal V.sub.inn at a gate. A drain of the second PMOS input transistor 214 and a drain of the second NMOS input transistor 216 are connected to each other to form an inverter defining the second output node 208 therebetween.

[0103] The self-biased clock buffer 200 further comprises bias transistors such that the input transistors are configured to receive bias currents.

[0104] The self-biased clock buffer 200 comprises a PMOS bias transistor 218. The PMOS bias transistor 218 comprises a source connected to a positive supply voltage and a drain connected to a source of the first PMOS input transistor 210 and a source of the second PMOS input transistor 214. The first PMOS input transistor 210 is thus connected to the PMOS bias transistor 218 so as to receive a bias current. Also, the second PMOS input transistor 214 is thus connected to the PMOS bias transistor 218 so as to receive a bias current.

[0105] Also, the source of the first PMOS input transistor 210 is connected to the source of the second PMOS input transistor 214.

[0106] The self-biased clock buffer 200 further comprises an NMOS bias transistor 222. The NMOS bias transistor 222 comprises a source connected to negative supply voltage (or ground) and a drain connected to a source of the first NMOS input transistor 212 and a source of the second NMOS input transistor 216. The first NMOS input transistor 212 is thus connected to the NMOS bias transistor 222 so as to receive a bias current. Also, the second NMOS input transistor 216 is thus connected to the NMOS bias transistor 222 so as to receive a bias current.

[0107] Also, the source of the first NMOS input transistor 212 is connected to the source of the second NMOS input transistor 216.

[0108] A gate of each of the bias transistors 218, 222 is connected to an internal node within the clock buffer 200 such that the clock buffer 200 is a self-biased clock buffer 200. The self-biased clock buffer 200 comprises a plurality of transistor switches 226, 228, each transistor switch 226, 228 being connected between the first output node 206 or the second output node 208 and a gate of a respective bias transistor 218, 222. The transistor switches 226, 228 are configured to control the self-biased clock buffer 200 to assume an active mode or a standby mode based on control signals enabling or disabling the transistor switches 226, 228.

[0109] As shown in FIG. 7, a first transistor switch 226 is connected between the first output node 206 and the gate of the PMOS bias transistor 218. A second transistor switch 228 is connected between the first output node 206 and the gate of the NMOS bias transistor 222.

[0110] However, it should be realized that at least one of the transistor switches 226, 228 may alternatively be connected to the second output node 208 and that the transistor switches 226, 228 need not be connected to the same output node.

[0111] Each transistor switch 226, 228 may comprise a p-type transistor and an n-type transistor. For instance, the first transistor switch 226 comprises the p-type transistor 226a and the n-type transistor 226b. The drains and sources of both complementary transistors in each transistor switch are connected between two common nodes for forming switches between the two common nodes.

[0112] The p-type transistor 226a is configured to receive a first enable signal on a gate of the p-type transistor 226a and the n-type transistor 226b is configured to receive a second enable signal for controlling the self-biased clock buffer 200 to assume an active mode or a standby mode.

[0113] The self-biased clock buffer 200 may present similar advantageous features as set forth above the self-biased clock buffer 100.

[0114] It should be realized that, even though not shown in FIG. 7, the self-biased clock buffer 200 may, similar to the self-biased clock buffer 100, comprise a first additional transistor switch and a second additional transistor switch. The first additional transistor switch may be a p-type transistor switch, having a source connected to positive supply voltage and a drain connected to the gate of the PMOS bias transistor 218. The second additional transistor switch may be an n-type transistor switch, having a source connected to negative supply voltage and a drain connected to the gate of the NMOS bias transistor 222.

[0115] The first additional transistor switch may be connected to receive the second enable signal and the second additional transistor switch may be connected to receive the first enable signal. This implies that the additional transistor switches may be on, when the transistor switches 226, 228 are off. This may imply that gate voltage of the PMOS bias transistors 218 and the NMOS bias transistor 222 may be tied to the positive supply voltage and negative supply voltage, respectively, and independent of instantaneous voltage at the first output node 206. This ensures that no current can flow through the circuit, and a proper power-down operation is achieved.

[0116] Referring now to FIG. 8, a method for controlling a self-biased amplifier circuit will be described.

[0117] The method comprises: receiving 302 a differential input signal at an input of the self-biased amplifier circuit.

[0118] As described above, the self-biased amplifier circuit comprises an input having a first input node and a second input node. The self-biased amplifier circuit may thus be configured to receive a differential input signal comprising a first input signal V.sub.inp and a second input signal V.sub.inn. The self-biased amplifier circuit may further be configured to provide a differential output signal at an output having a first output node and a second output node.

[0119] The self-biased amplifier circuit comprises a first PMOS input transistor and a first NMOS input transistor forming two complementary input transistors at the first input node. The first PMOS input transistor is configured to receive the first input signal V.sub.inp at a gate. Also, the first NMOS input transistor is configured to receive the first input signal V.sub.inp at a gate. A drain of the first PMOS input transistor and a drain of the first NMOS input transistor are connected to each other to form an inverter defining the first output node therebetween.

[0120] The self-biased amplifier circuit further comprises a second PMOS input transistor and a second NMOS input transistor forming two complementary input transistors at the second input node. The second PMOS input transistor is configured to receive the second input signal V.sub.inn at a gate. Also, the second NMOS input transistor is configured to receive the second input signal V.sub.inn at a gate. A drain of the second PMOS input transistor and a drain of the second NMOS input transistor are connected to each other to form an inverter defining the second output node therebetween.

[0121] The method further comprises providing 304 a first bias current to the first PMOS input transistor and the second PMOS input transistor. The first bias current may be provided by at least one PMOS bias transistor, wherein a source of each of the first and the second PMOS input transistor is connected to a drain of the at least one PMOS bias transistor for receiving the bias current.

[0122] The method further comprises providing 306 a second bias current to the first NMOS input transistor and the second NMOS input transistor by at least one NMOS bias transistor, wherein a source of each of the first and the second NMOS input transistor is connected to a drain of the at least one NMOS bias transistor for receiving the bias current.

[0123] The method further comprises providing 308 control signals to a first and a second transistor switch.

[0124] The first transistor switch is connected between the first or the second output node and a gate of the at least one PMOS bias transistor. The second transistor switch is connected between the first or the second output node and a gate of the at least one NMOS bias transistor. The control signals provided to the first and the second transistor switches control the self-biased amplifier circuit to assume an active mode or a standby mode.

[0125] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.