WAFER SINGULATING METHOD AND LED CHIP AND LIGHT EMITTING MODULE

Abstract

A wafer singulating method includes: providing a wafer product having front and back sides the front side being formed with scribe lines; deep scribing with a laser along the scribe lines on the front side to form a plurality of intersecting trenches; and cleaving the back side along the trenches on the front side. The cleaving of the back side proceeds in different directions each of which is directed to a center of the wafer product from a periphery of the wafer product. The cleaving in each of the directions proceeds along the trenches one after the other from one of the trenches nearest to the periphery of the wafer product and ceases near or at the center.

Claims

1. A wafer singulating method comprising: providing a wafer product having a front side and a back side opposite to each other, the front side of the wafer product having a plurality of scribe lines; deep scribing the wafer product with a laser along the scribe lines from the front side of the wafer product to form a plurality of intersecting trenches on the front side of the wafer product; cleaving the back side of the wafer product along the trenches on the front side of the wafer product; wherein the cleaving proceeds in different directions each of which is directed to a center of the wafer product from a periphery of the wafer product, and the cleaving in each of the directions proceeds along the trenches one after the other from one of the trenches nearest to the periphery of the wafer product and ceases near or at the center of the wafer product.

2. The wafer singulating method as claimed in claim 1, wherein, before the cleaving proceeds along the trenches, the wafer product is cleaved into multiple sub-wafers, and each of the sub-wafers is cleaved from the periphery of the wafer product toward the center of the wafer product.

3. The wafer singulating method as claimed in claim 2, wherein the wafer product is cleaved into the sub-wafers along at least one straight line passing through the center of the wafer product.

4. The wafer singulating method as claimed in claim 1, wherein a ratio of a depth of the trench to a thickness of the wafer product ranges from 1:5 to 1:2.

5. The wafer singulating method as claimed in claim 1, wherein the front side of the wafer product further includes an epitaxial layer that has a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack.

6. The wafer singulating method as claimed in claim 5, wherein the trenches formed by deep scribing the front side of the wafer product extend through the epitaxial layer.

7. The wafer singulating method as claimed in claim 4, wherein the trenches include first and second trenches intersecting each other, the step of cleaving the wafer product includes: cleaving the back side of the wafer product along a first straight line that extends in a first direction and that passes through a geometric center of the wafer product, and a second straight line that extends in a second direction and that passes through the geometric center of the wafer product, so that the wafer product is divided into a first sub-wafer, a second sub-wafer, a third sub-wafer, and a fourth sub-wafer which follow one after the other in a clockwise order; cleaving the back side of the wafer product along the first trenches that are parallel to the first straight line by proceeding from one of the first trenches nearest to a first side of the periphery of the wafer product to the other one of the first trenches nearest to the first straight line so that each of the first sub-wafer and the fourth sub-wafer is diced to allow separation of cleaved parts in the second direction; cleaving the wafer product along the first trenches parallel to the first straight line by proceeding from one of the first trenches nearest to a second side of the periphery of the wafer product to the other one of the first lines nearest to the first straight line so that the second sub-wafer and the third sub-wafer are diced to allow separation of cleaved parts in the second direction, the second side being opposite to the first side along the second direction; cleaving the wafer product along the second trenches parallel to the second straight line by proceeding from one of the second trenches nearest to a third side of the periphery of the wafer product to the other one of the second trenches nearest to the second straight line so that the first sub-wafer and the second sub-wafer are diced to allow separation of cleaved parts in the first direction; and cleaving the wafer product along the second trenches parallel to the second straight line by proceeding from one of the second trenches nearest to a fourth side of the periphery of the wafer product to the other one of the second trenches nearest to the second straight trenches so that the third sub-wafer and the fourth sub-wafer are diced for separation of cleaved parts in the first direction, the third and fourth sides being opposite in the first direction.

8. An LED chip comprising a singulated wafer product having a front side and a back side disposed opposite to each other, and a cleaved side wall extending transversely between said front and back sides; wherein an end of said cleaved side wall proximate to said front side is formed with a recast portion, and an end of said cleaved side wall proximate to said back side being a smooth side wall surface portion.

9. The LED chip as claimed in claim 8, wherein a ratio of a thickness (D0) of said recast portion to a thickness (D) of said cleaved side wall ranges from 1:5-1:2.

10. The LED chip as claimed in claim 8, wherein: said singulated wafer product has a rectangular cross section on a plane perpendicular to a thickness direction of said singulated wafer product; a ratio of a length (L) of said singulated wafer product to a thickness (D) of said cleaved sidewall is no less than 4; and a ratio of a width (W) of said singulated wafer product to said thickness (D) of said cleaved side wall is no less than 4.

11. The LED chip as claimed in claim 8, wherein an angle between said cleaved side wall (CS) and said back side ranges from 85? to 95?.

12. The LED chip as claimed in claim 8, wherein: Said front side of said singulated wafer product further has an epitaxial layer wafer product which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said back side of said singulated wafer product and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.

13. The LED chip as claimed in claim 8, wherein: Said front side of said singulated wafer product further has an epitaxial layer which includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially arranged in a stack; an electrode structure including a first electrode that is formed on said epitaxial layer and that is electrically connected to said first type semiconductor layer, and a second electrode that is formed on said second type semiconductor layer and that is electrically connected to the second type semiconductor layer.

14. A light-emitting module comprising a printed circuit board (PCB), and a light-emitting device disposed on said PCB, said light-emitting device including the LED chip as claimed in claim 8.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment(s) with reference to the accompanying drawings. It is noted that various features may not be drawn to scale.

[0014] FIG. 1a is a block diagram illustrating steps in a conventional wafer singulating method.

[0015] FIG. 1b illustrates a wafer product and a direction of cleaving the wafer product according to the convention wafer singulating method.

[0016] FIG. 2 is a block diagram illustrating steps in an embodiment of a wafer singulating method according to the present disclosure.

[0017] FIG. 3 is a schematic view illustrating a back side cleaving step of the wafer singulating method of the present disclosure.

[0018] FIG. 4 is another schematic view illustrating the cleaving step of the wafer singulating method of the disclosure.

[0019] FIG. 5 is a schematic view illustrating an LED chip of a second embodiment according to the present disclosure, which is produced by the wafer singulating method of the first embodiment.

[0020] FIG. 6 is a fragmentary enlarged view of the LED chip in FIG. 5, illustrating a cleaved side wall of the LED chip.

[0021] FIG. 7 is a schematic view illustrating a conventional LED chip singulated via a conventional wafer singulating method.

[0022] FIG. 8 is a fragmentary enlarged view of the conventional LED chip in FIG. 7.

[0023] FIG. 9 is a schematic cross-sectional view illustrating a variation of the LED chip of the second embodiment.

[0024] FIG. 10 is a schematic cross-sectional view illustrating another variation of the second embodiment.

[0025] FIG. 11 is the same view as FIG. 4 but illustrating a cleaved area and an uncleaved area on two sides of a cleaving force bearing point during the cleaving step of the wafer singulating method.

[0026] FIG. 12 is a fragmentary enlarged view illustrating an obliquely cleaved chip edge profile of a conventional chip singulated via the conventional laser dicing method.

DETAILED DESCRIPTION

[0027] Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.

[0028] It should be noted herein that for clarity of description, spatially relative terms such as top, bottom, upper, lower, on, above, over, downwardly, upwardly and the like may be used throughout the disclosure while making reference to the features as illustrated in the drawings. The features may be oriented differently (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be interpreted accordingly.

[0029] The implementation of the present disclosure will be illustrated below by way of specific examples, and other advantages and effects of the present disclosure can be readily appreciated by those skilled in the art based on the disclosure of the present specification. The present disclosure may also be implemented or applied in different embodiments, and the details of the present specification may also be based on different views and applications, and various modifications or changes may be made without departing from the spirit of the present disclosure.

First Embodiment

[0030] Referring to FIGS. 2 and 3, the first embodiment of the disclosure is a wafer product singulating method that includes steps S100, S200, and S300.

[0031] In the step S100, a wafer product 100 is provided. The wafer product 100 has a front side 110 and a back side 120 opposite to each other. The front side 110 of the wafer product 100 is formed with a plurality of scribe lines (not shown).

[0032] In the step S200, the wafer product 100 is deep scribed with a laser along the scribe lines from the front side 110 of the wafer product 100 to form a plurality of intersecting trenches 101 on the front side 110 of the wafer product 100. In this embodiment, the scribe lines are formed via etching, and the trenches 101 are open grooves formed along the scribe lines via deep scribing. Furthermore, it should be noted that the trenches 101 are formed by deeply scoring the scribe lines to form deep open grooves. In other words, a high powered laser is used to ablate the scribe lines so that a ratio of a depth of the formed trenches 101 to a thickness of the wafer product is greater than 1:5. This is in contrast to laser scribing where a lower powered laser would be used to form the trenches 101 so that the trenches 101 would have a depth to thickness ratio of less than 1:5. In this embodiment, the ratio of the depth of the trenches 101 to the thickness of the wafer product 100 ranges from 1:5 to 1:2.

[0033] In the step S300, the back side 120 of the wafer product 100 is cleaved along the trenches 101 on the front side 110 of the wafer product 100. The cleaving proceeds in different directions each of which is directed to a center of the wafer product from a periphery of the wafer product. The cleaving in each of the directions proceeds along the trenches 101 one after the other from one of the trenches 101 nearest to the periphery of the wafer product and ceases near or at the center of the wafer product.

[0034] Referring further to FIG. 3, the wafer product 100 is placed on a dicing machine with the front side 110 of the wafer product 100 facing down and the back side 120 of the wafer product facing up. The wafer product 100 may be a bare wafer without any functional layers thereon, and may be a silicon wafer, a silicon carbide SiC wafer etc. In other embodiments, the wafer product 100 may already contain functional layers (semiconductor elements such as light-emitting diodes (LEDs), metal oxide semiconductors (MOS) etc.). The scribe lines are formed on the front side 110 of the wafer product 100 in a criss-cross arrangement. In this embodiment, the front side 110 of the wafer product 100 has an epitaxial layer which includes a first type semiconductor layer 1042, an active layer 1043, and a second type semiconductor layer 1044 sequentially arranged in a stack.

[0035] As shown in FIG. 3, the wafer product 100 is deep scribed with a laser beam 300 on the front side 110 of the wafer product 100 to form the plurality of intersecting trenches 101 on the front side 110 of the wafer product 100. In this embodiment, the wafer product 100 is deep scribed with the laser beam 300 along the scribe lines on the front side 110 of the wafer product 100 to form the plurality of intersecting trenches 101 on the front side 110 of the wafer product 100. In this embodiment, the ratio of the depth of the trenches 101 to the thickness of the wafer product 100 ranges from 1:5 to 1:2 which is conducive for subsequent cleaving. For example the depth to thickness ratio may be 1:4, 1:3, or 2:5.

[0036] The trenches 101 on the front side 110 of the wafer product 100 extend through the epitaxial layer 104A. More specifically, when the front side 110 of the wafer product 100 is formed with the epitaxial layer 104A, a depth of the trenches 101 is at least equal to a thickness of the epitaxial layer 104A. That is, the trenches 101 formed by deep scribing the front side 110 of the wafer product 100 at least extend through the entire thickness of the epitaxial layer 104A. The trenches 101 includes first and second trenches (L1, L2) that intersect each other (see FIG. 4). Then, as also shown in FIG. 3, the wafer product 100 is cleaved from the back side 120 of the wafer product 100 using a cutting blade 200, along the trenches 101 located on the front side 110 of wafer product 100. Compared to the conventional singulating method of the prior art, the wafer product singulating method of the present disclosure dispenses with the wafer product back side laser scribing and eliminates the problem of misalignment of back side laser scribe marks, the method also dispenses with the back side laser dicing and thus eliminates the problem of inducing abnormal oblique cleavage surfaces at singulated chip edges.

[0037] In the present embodiment, the step of cleaving is performed differently from the existing art, where the wafer product is cleaved sequentially from one side to the other side (e.g., from left to right). Referring to FIG. 4, in this embodiment, the wafer product 100 is first cleaved by using the cutting blade 200 cutting in a first direction (Y) and a second direction (X) on the back side 120 of the wafer product 100. The cleaving of the wafer product 100 proceeds in different directions: different X directions (see arrows A12, A22, A31, A41) and different Y directions (see arrows A11, A21, A32, A42).

[0038] More specifically, as shown in FIG. 4, the back side 120 of the wafer product 100 is first cleaved with the cutting blade 200 along a first straight line 102 that extends in the first direction (Y) and that passes through a geometric center of the wafer product 100, and a second straight line 103 that extends in the second direction (X) and that passes through the geometric center of the wafer product 100, so that the wafer product is divided into a first sub-wafer product (W1), a second sub-wafer product (W2), a third sub-wafer product (W3), and a fourth sub-wafer product (W4) which follow one after the other in a clockwise order. The first straight line 102 and the second straight line 103 pass through the center of the wafer product 100 and are perpendicular to each other.

[0039] Then, the back side of the wafer product 100 is cleaved along the first trenches (L1) that are parallel to the first straight line 102 by proceeding from one of the first trenches (L1) nearest to a first side of the periphery of the wafer product 100 to the other one of the first trenches (L1) nearest to the first straight line 102 so that each of the first sub-wafer product (W1) and the fourth sub-wafer product (W4) is diced to allow separation of cleaved parts in the second direction (X). More specifically, the wafer product 100 is repeatedly cleaved from one of the first trenches (L1) to a next first trench (L1) in an A11 direction while being cleaved in an A12 direction (see FIG. 4) along each of the first lines (L1). Next, the wafer product 100 is cleaved along the first trenches (L1) parallel to the first straight line 102 by proceeding from one of the first trenches (L1) nearest to a second side of the periphery of the wafer product 100 to the other one of the first trenches (L1) nearest to the first straight line 102 so that the second sub-wafer product (W2) and the third sub-wafer product (W3) are diced to allow separation of cleaved parts in the second direction (X). The second side is opposite to the first side along the second direction (X). More specifically, the wafer 100 is repeatedly cleaved from one of the trenches 101 to the next trenches 101 in an A21 direction while being cleaved in an A22 direction (see FIG. 4) along each of the first trenches (L1). Next, the wafer product 100 is cleaved along the second trenches (L2) parallel to the second straight line 103 by proceeding from one of the second trenches (L2) nearest to a fourth part of the periphery of the wafer product 100 to the other one of the second trenches (L2) nearest to the second straight line 103 so that the third sub-wafer product (W3) and the fourth sub-wafer product (W4) are diced to allow separation of cleaved parts in the first direction (Y). More specifically, the wafer 100 is repeatedly cleaved trench by trench in an A31 direction while progressively moving in an A32 direction (see FIG. 4) along each of the second lines (L2). Then, the wafer product 100 is cleaved along the second trenches (L2) parallel to the second straight line 103 by proceeding from one of the second trenches (L2) nearest to a third side of the periphery of the wafer product 100 to the other one of the second trenches (L2) nearest to the second straight line 103 so that the first sub-wafer product (W1) and the second sub-wafer product (W2) are diced to allow separation of cleaved parts in the first direction (Y). More specifically, the wafer product 100 is repeatedly cleaved in an A41 direction while progressively moving in an A42 direction along each of the second lines (L2). The above cleaving method reduces the risk of creating abnormal obliquely cleaved sidewall surfaces by reducing the length in the step S300, and allows the back side 120 of the wafer product 100 to be accurately cleaved along the trenches 101 on the front side 110 of the wafer product 100. The cleaving proceeds in different directions each of which is directed to a center of the wafer product 100 from a periphery of the wafer product 100. The cleaving in each of the directions proceeds along the trenches 101 one after the other from one of the trenches 101 nearest to the periphery of the wafer product and ceases near or at the center of the wafer product 100. This helps to induce perpendicular cleavage of the wafer product 100 along the laser scribed trenches 101, reduce defects, and improve production yields of singulated chips thereof. By omitting the back side laser scribing and the back side dicing with the cutting blade which are conducted in the conventional singulating method, the wafer product singulating method of the present disclosure reduces processing steps and is more optimized, and production yields may be increased. Additionally, material and equipment used for the back side laser scribing and back side dicing conducted in the conventional method may be spared and the method of the present disclosure is therefore more cost efficient.

[0040] Referring to FIG. 11, in the cleaving step according to the present disclosure, the wafer product 100 is first divided into the first to fourth sub-wafer products W1, W2, W3, and W4, and the cleaving proceeds from one side of the periphery of the wafer product 100 and stops near the center line (i.e., the first straight line 102, and the second straight line 103) that passes through the center of the wafer product 100. When the sub-wafer product W2 is cleaved along one of the first trenches (L1) (see the line depicted by W2), the cleaving force bearing point is along the line W2, and an already cleaved area and an uncleaved area are on two sides of the line W2. Compared to the conventional singulating method which does not produce sub-wafer products, in the singulating method of the present disclosure, each sub-wafer product W1, W2, W3, W4 has its already cleaved area and uncleaved area with reduced lengths on two sides of a force bearing line W2. This reduces wafer product deformation during the cleaving of the wafer product 100 and thus reduces defects and improves yield. It should be noted that the order and sequence of the cleaving is not limited to the sequence described in the disclosure; the sequence of the cleaving proceeding from any one of the first to fourth parts of the periphery along the first straight line 102 or second straight line 103, and may be adjusted according to practical requirements.

Second Embodiment

[0041] The second embodiment provides an LED chip 104 produced by the singulating method of the first embodiment. FIGS. 5 and 6 show photographs taken by a scanning electron microscope (SEM) of an LED chip 104 which includes a singulated wafer product 100. Referring to FIGS. 7 and 8, the conventional chip 10 obtained from the conventional singulating method has a side wall having a recast layer segment 11 near a front side of the conventional chip 10 formed by the front side laser scribing, a diced segment 13 resulting from the back side dicing with the cutting blade near the back side of the conventional chip 10, and a cleaved segment 12 on a middle section between the diced segment 13 and the recast layer segment 11. Due to the obliquely cleaving of the wafer product (chip 10) in the conventional singulating method, the side wall of the conventional chip 10 manifests distinctive misalignment appearance occurring between the above segments 11, 12, 13. In contrast, the wafer singulating method of the present disclosure essentially conducts the laser deep scribing on the front side 110 and the back side dicing with the cutting blade to obtain the LED chips 104. Referring to FIGS. 5 and 6, an LED chip 104 singulated via the wafer singulating method of the present disclosure has a cleaved side wall (CS) with relatively neat cleaved surfaces. The cleaved side wall (CS) extending transversely between the front side 110 and the back side 120. An end of the cleaved side wall (CS) proximate to the front side 110 is formed with a recast portion 105, and an end of the cleaved side wall (CS) proximate to the back side 120 has a smooth side wall surface 106. Apart from the recast portion 105 and the smooth side wall surface portion 106, the cleaved side wall (CS) has no other surface irregularities and abnormally cleaved surfaces. The cleaved side wall (CS) is relatively uniform in appearance. Additionally, in the method of the present disclosure, the wafer product 100 is perpendicularly cleaved along the trenches 101, and the LED chip 104 thus obtained has the back side 120 with a smooth edge and without any knife marks. An angle between the cleaved side wall (CS) and the front and/or back sides 110, 120 ranges from 85? to 95?. In some embodiments, the cleaved side wall (CS) is substantially vertical and the angle between the cleaved side wall (CS) and each of the front or back sides 110, 120 approaches 90?.

[0042] Referring to FIG. 5, the LED chip 104 has a rectangular cross section on a plane perpendicular to a thickness direction of the singulated wafer product 100. The LED chip 104 as shown in FIG. 5 has a length (L), a width (W), and the cleaved side wall (CS) has a thickness (D) The LED chip 104 may have its length (L) equal to its width (W). In other words, the LED chip 104 may have a square cross section. Referring to FIG. 6, in some embodiments, a ratio of a thickness (D0) of the recast portion 105 to a thickness (D) of the cleaved side wall (CS) may range from 1:5 to 1:2. For example, the ratio may be 1:4, 1:3, 2:5. In this embodiment, the ratio of the length (L) or width (W) of the singulated wafer product 100 to the thickness (D) of the cleaved side wall (CS) is no less than 4.

[0043] Referring to FIGS. 5 to 7, comparing the LED chip 104 of the disclosure with the conventional chip 10, the cleaved side wall (CS) of the LED chip 104 is smooth and substantially vertical with the angle between the cleaved side wall (CS) and the back side 120 ranging from 85? to 95?. This ensures the performance stability of the LED chip 104 and improves production yield.

[0044] Referring to FIG. 9, in a variation of the second embodiment, the LED chip 104 includes a wafer product 1041 having the oppositely disposed front and back sides. The front side of the LED chip 104 is a functional side and includes an epitaxial layer 104A formed on the front side that includes a first type semiconductor layer 1042, an active layer 1043, and a second type semiconductor layer 1044, sequentially arranged in a stack. The LED chip 104 further includes an electrode structure including a first electrode 1071 that is formed on the epitaxial layer 104A and that is electrically connected to the first type semiconductor layer 1042, and a second electrode 1072 that is formed on the second type semiconductor layer 1044 and that is electrically connected to the second type semiconductor layer 1044. Referring to FIG. 9, the LED chip 104 further includes an insulating layer 1045 that electrically isolates the electrode structure from other areas of the epitaxial layer 104A, and protects the LED chip 104.

[0045] In some embodiments, the epitaxial layer is made of GaAs. The first type semiconductor layer 1042 is an N-GaAs layer, and the second type semiconductor layer 1044 is a P-GaAs layer. Referring to FIG. 9, the LED chip 104 has vertical side walls.

[0046] Referring to FIG. 10, in another variation of the second embodiment, the front side of the LED chip 104 is a functional side and includes an epitaxial layer 104A formed on the front side 110 of the wafer product layer 1041, and includes a first type semiconductor layer 1042, an active layer 1043, and a second type semiconductor layer 1044 sequentially arranged in a stack. The LED chip 104 has an electrode structure including a first electrode 1071 that is formed on the back side 120 of the wafer product layer 1041 and that is electrically connected to the first type semiconductor layer 1042, and a second electrode 1072 that is formed on the second type semiconductor layer 1044 and that is electrically connected to the second type semiconductor layer 1044. In this variation the LED chip 104 is an LED flip-chip packaged device. The LED chip 104 of the second embodiment has superior side wall characteristics. The cleaved side wall (CS) is substantially vertical, and an angle between the cleaved side wall (CS) and the front and/or back sides is close to 90?. This allows the LED chip 104 to have good external appearance, ensures chip operation stability, and provides good production yield.

Third Embodiment

[0047] In the third embodiment of the disclosure, a light-emitting module includes a printed circuit board (PCB), and a light-emitting device disposed on the PCB. The light-emitting device may be the LED chip 104 of the second embodiment of the present disclosure. Because the LED chips 104 according to the present disclosure are singulated to have few defects and good electrical characteristics, the light-emitting module will also have good electrical characteristics.

[0048] In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to one embodiment, an embodiment, an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects; such does not mean that every one of these features needs to be practiced with the presence of all the other features. In other words, in any described embodiment, when implementation of one or more features or specific details does not affect implementation of another one or more features or specific details, said one or more features may be singled out and practiced alone without said another one or more features or specific details. It should be further noted that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.

[0049] While the disclosure has been described in connection with what is(are) considered the exemplary embodiment(s), it is understood that this disclosure is not limited to the disclosed embodiment(s) but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.