MATERIAL STACK FOR MICROELECTRONIC DEVICE, A MICROELECTRONIC DEVICE THAT INTEGRATES SUCH STACK AND METHOD FOR MANUFACTURING SUCH STACK

Abstract

A material stack, a microelectronic device that integrates the stack, and a method for obtaining the stack. The material stack for microelectronic device includes a substrate, a first undoped crystalline layer on the substrate, the undoped crystalline layer having a thickness superior to 4 nm, and a Si-doped crystalline chalcogenide layer on the undoped crystalline layer, the Si-doped crystalline chalcogenide layer being doped with less than 20 at. %, and preferably less than 12 at. %, of Si. The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e., intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.

Claims

1. A material stack for microelectronic device, comprising: a substrate, a first undoped monocrystalline layer on the substrate, said undoped monocrystalline layer having a thickness superior or equal to 4 nm, and a Si-doped crystalline chalcogenide layer on the first undoped monocrystalline layer, said Si-doped crystalline chalcogenide layer being doped with Si having an atomic concentration ranging from 0.5 at. % to 20 at. % and said Si-doped crystalline chalcogenide layer having a thickness comprised in between 0.5 nm and 20 nm.

2. The material stack according to claim 1L wherein the first undoped monocrystalline layer is based on a material allowing its heterogenous epitaxial growth on the substrate and allowing the heterogenous epitaxial growth of the Si-doped crystalline chalcogenide layer thereon.

3. The material stack according to claim 1, wherein said first undoped monocrystalline layer is an undoped monocrystalline chalcogenide layer.

4. The material stack according to claim 1, wherein the Si-doped chalcogenide layer is monocrystalline.

5. The material stack according to claim 1, wherein the first undoped layer is monocrystalline as deposited on the substrate, and wherein the Si-doped chalcogenide layer is crystalline as deposited on the first undoped monocrystalline layer.

6. The material stack according to claim 1, further comprising: A second undoped crystalline layer over said Si-doped crystalline chalcogenide layer with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being based on a chalcogenide material, and A secondary Si-doped crystalline chalcogenide layer over said second undoped crystalline layer, with said secondary Si-doped crystalline chalcogenide layer being based on the same chalcogenide material than said Si-doped crystalline chalcogenide layer.

7. The material stack according to claim 1, further comprising: a second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being preferably based on a chalcogenide material, and at least one sub-stack over said second undoped crystalline layer, each sub-stack comprising: a secondary Si-doped crystalline chalcogenide layer, and a secondary undoped crystalline layer over said another secondary Si-doped crystalline chalcogenide layer, with each secondary Si-doped crystalline chalcogenide layer being based on the same chalcogenide material than said Si-doped crystalline chalcogenide layer.

8. The material stack according to claim 1, further comprising: a second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being based on a chalcogenide material, and a secondary Si-doped crystalline chalcogenide layer over said second undoped crystalline layer, with said secondary Si-doped crystalline chalcogenide layer being based on a different chalcogenide material than the one of said Si-doped crystalline chalcogenide layer and/or having a different concentration of Si dopants than the one of said Si-doped crystalline chalcogenide layer.

9. The material stack according to claim 1, further comprising: a second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being based on a chalcogenide material, and at least one sub-stack over said second undoped crystalline layer, each sub-stack comprising: a secondary Si-doped crystalline chalcogenide layer, and a secondary undoped crystalline layer over said another secondary Si-doped crystalline chalcogenide layer, with at least one secondary Si-doped crystalline chalcogenide layer being based on a different chalcogenide material than the one of said Si-doped crystalline chalcogenide layer and/or having a different concentration of Si dopants than the one of said Si-doped crystalline chalcogenide layer.

10. The material stack according to claim 1, wherein the substrate comprises a heater, and wherein the first undoped crystalline layer is over the heater.

11. The material stack according to claim 1, wherein said first undoped crystalline layer extending on the substrate has a thickness comprised in between 4 and 20 nm.

12. The material stack according to claim 1, wherein each Si-doped crystalline chalcogenide layer and/or each undoped crystalline chalcogenide layer is based on a material chosen among: Ge.sub.xSb.sub.yTe.sub.z (GST) where x-y-z are chosen to reach a stoichiometric composition allowing a deviation of plus or minus 2 at. % from a targeted stoichiometric composition, GeTe, and Sb.sub.2Te.sub.3.

13. The material stack according to claim 1, wherein each first undoped crystalline layer extending on the substrate is based on at least one material chosen among: Sb.sub.2Te.sub.3, Bi.sub.2Te.sub.3, and Sb.sub.2Se.sub.3.

14. A thermally processed material stack for microelectronic device being a Phase-Change Memory (PCM) device, comprising: a substrate, and a thermally processed Si-doped crystalline chalcogenide layer on the substrate, said thermally processed Si-doped crystalline chalcogenide layer being doped with less than 20 at. %, of Si and said thermally processed Si-doped crystalline chalcogenide layer having a crystal surface parallel to the substrate equal to or greater than 400 nm.sup.2.

15. A method for manufacturing a thermally processed material stack, the method comprising: a step of providing a material stack according to claim 1; and a step of thermal treatment of the provided material stack.

16. The method according to claim 15, wherein said step of thermal treatment is part of an integration process of the material stack in a microelectronic device.

17. The method according to claim 15, wherein said provided material stack comprises a substrate and a multilayer extending on the substrate, said multilayer comprising a plurality of Si-doped crystalline chalcogenide layers and having a thickness comprised in between 5 and 100 nm.

18. The method according to claim 15, wherein the Si-doped crystalline chalcogenide layer is formed by co-sputtering deposition.

19. A microelectronic device being a Phase-Change Memory (PCM) device, comprising at least a material stack according to claim 1, and a top electrode of the microelectronic device on the material stack, wherein a substrate of the concerned material stack comprises a bottom electrode of the microelectronic device.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0040] The aims, objects, as well as the features and advantages of the invention will appear better from the detailed description of an embodiment of the latter which is illustrated by the following appended drawings wherein:

[0041] In the legend of the figure, the Si doping is represented by the annotation :Si (i.e. Ge.sub.2Sb.sub.2Te.sub.5:Si). The undoped crystalline chalcogenide layer acts as a buffer layer and it can also be defined as under-layer (or UL).

[0042] FIG. 1 is a graph showing the result of a XRD omega scan for (009) peak of crystalline Sb.sub.2Te.sub.3 layers with Si doping at 12 at. % (curve with long dashes and dots) and without Si doping (curve with dashes) deposited on native silicon oxide of a silicon wafer substrate.

[0043] FIG. 2 is a graph showing the result of XRD spectra for a multi-layers (ML) based on Ge.sub.2Sb.sub.2Te.sub.5 and Sb.sub.2Te.sub.3 doped with 12 at. % of Si; the ML without UL (curve with long dashes and dots) shows a very poor crystallinity (i.e. with no texture) whereas the ML with UL (curve with dashes) shows a crystallinity (i.e. a texture).

[0044] FIG. 3 is a graph showing the result of a XRD omega scan at 2Theta=25.5? of a ML with Ge.sub.2Sb.sub.2Te.sub.5:Si thickness of 3.6 nm alternate with Sb2Te3 thickness of 2 nm on Sb2Te3 buffer layer (6.3 nm).

[0045] FIG. 4 is a graph showing the result of a XRD omega scan at 2Theta=25.5? of a ML with Ge.sub.2Sb.sub.2Te.sub.5:Si12% with a thickness of 1.8 nm (top curve) or 3.6 nm (bottom curve) alternates with Sb2Te3 (1 nm and 2 nm) on Sb2Te3 buffer (6.3 nm).

[0046] FIG. 5 is a graph showing the result of a XRD omega scan at 2Theta=25.5? of a ML with Ge.sub.2Sb.sub.2Te.sub.5:Si12% with a thickness of 3.6 nm alternates with Sb2Te3 2 nm or 6 nm on Sb2Te3 buffer (6.3 nm).

[0047] FIG. 6 is a TEM image of a ML made by alternation of Ge.sub.2Sb.sub.2Te.sub.5:Si8% (3.6 nm) and Sb.sub.2Te.sub.3 (2.1 nm) over a buffer layer Sb.sub.2Te.sub.3 (6.3 nm). The total ML thickness is about 50 nm.

[0048] FIG. 7 is a TEM image of a ML made by alternation of Sb.sub.2Te.sub.3:Si12% (2.1 nm) Ge.sub.2Sb.sub.2Te.sub.5 (3.6 nm) and over a buffer consisting in a bilayer made of Sb.sub.2Te.sub.3 (6.3 nm) and Ge.sub.2Sb.sub.2Te.sub.5 (3.6 nm). The total ML thickness is around 50 nm.

[0049] FIG. 8 is a TEM image of a ML Sb.sub.2Te.sub.3:Si12% (2.1 nm) Ge.sub.2Sb.sub.2Te.sub.5 (3.6 nm) and over a buffer layer Sb.sub.2Te.sub.3 (6.3 nm). FIG. 8 shows magnification of the crystalline structure.

[0050] FIG. 9 is a graph showing the result of a XRD omega scan at 2Theta=25.5? of a ML with Sb.sub.2Te.sub.3:Si12% with a thickness of 2.1 nm alternates with Ge.sub.2Sb.sub.2Te.sub.5 3.6 nm on Sb.sub.2Te.sub.3 buffer (6.3 nm) as deposited and after annealing at 400? C. for 15 minutes.

[0051] FIG. 10 is a graph showing the result of a XRD 2Theta-Theta scan of a ML with Sb.sub.2Te.sub.3:Si12% with a thickness of 2.1 nm alternates with Ge.sub.2Sb.sub.2Te.sub.5 3.6 nm on Sb.sub.2Te.sub.3 buffer (6.3 nm) as deposited and after annealing at 400? C. for 15 minutes.

[0052] FIG. 11 is a TEM image of a ML with Sb.sub.2Te.sub.3:Si12% with a thickness of 2.1 nm alternated with Ge.sub.2Sb.sub.2Te.sub.5 3.6 nm on Sb.sub.2Te.sub.3 buffer (6.3 nm) after annealing at 400? C. for 15 minutes.

[0053] FIG. 12 is an EDX image of a ML with Sb.sub.2Te.sub.3:Si12% with a thickness of 2.1 nm alternated with Ge.sub.2Sb.sub.2Te.sub.5 3.6 nm on Sb.sub.2Te.sub.3 buffer (6.3 nm) after annealing at 400? C. for 15 minutes. A uniform distribution of all the elements is observed.

[0054] FIG. 13 is a TEM image of a ML made by alternation of Ge.sub.2Sb.sub.2Te.sub.5:Si8% (3.6 nm) and Sb.sub.2Te.sub.3 (2.1 nm) over a buffer layer Sb.sub.2Te.sub.3 (6.3 nm) after annealing at 400? C. for 15 minutes. The arrows indicate the presence of 3-tuple, with the appearing of the new feature.

[0055] FIG. 14 is a TEM image at higher resolution of a ML made by alternation of Ge.sub.2Sb.sub.2Te.sub.5:Si8% (3.6 nm) and Sb.sub.2Te.sub.3 (2.1 nm) over a buffer layer Sb.sub.2Te.sub.3 (6.3 nm) after annealing at 400? C. for 15 minutes. This image shows detail of the new appeared feature.

[0056] FIG. 15 is a TEM image of a GeSb.sub.2Te.sub.4 layer deposited at 225? C. without UL doped with 5 at. % of Si after annealing at 400? C.; The texture of the layer is impossible to achieve.

[0057] FIG. 16 is a first example of a material stack according to the invention in between top and bottom electrodes for a PCM device.

[0058] FIG. 17A is a second example of a material stack according to the invention in between top and bottom electrodes; More particularly, said second example comprises, over the UL, a bilayer where the PCM material is a chalcogenide crystalline layer.

[0059] FIG. 17B is a variant of the second example illustrated on FIG. 17A wherein two or more bilayers can be used and repeated n times.

[0060] FIG. 18A is a third example of a material stack according to the invention in between top and bottom electrodes; More particularly, said third example comprises a crystalline Si-doped PCM layer over the UL, followed by a bilayer consisting in a undoped layer of PCM material and a second crystalline Si-doped PCM layer with different Si content or chalcogenide composition.

[0061] FIG. 18B is a variant of the third example illustrated on FIG. 18A wherein two or more bilayers can be used and repeated n times which are based on the same material as the UL or on different ones.

[0062] The drawings are provided as examples and do not limit the invention. They form schematic principle representations intended to facilitate the understanding of the invention and are not necessarily to the scale of the practical applications. In particular, the thicknesses of the different illustrated layers are not necessarily representative of reality or of realistic shape factors.

DETAILED DESCRIPTION

[0063] Before starting a detailed review of embodiments of the invention, optional features that could possibly be used in combination or alternatively are set out hereinafter.

[0064] As an example of the first aspect of the invention, each undoped crystalline layer may be based on a material allowing its heterogenous epitaxial growth on the substrate and allowing the heterogenous epitaxial growth of the Si-doped crystalline chalcogenide layer thereon.

[0065] As another example of the first aspect of the invention, said first undoped crystalline layer has a crystalline orientation along the (001) planes.

[0066] As another example of the first aspect of the invention, said undoped crystalline layer may have a stoichiometric composition allowing a deviation of plus or minus 2 at. %, preferably 1 at. %, from a targeted stoichiometric composition, preferably from a perfect one.

[0067] As another example of the first aspect of the invention, said undoped crystalline layer may be an undoped crystalline chalcogenide layer, preferably this latter being a chalcogenide material different or same from the one of said Si-doped crystalline chalcogenide layer.

[0068] As another example of the first aspect of the invention, the material stack may further comprise: [0069] a. A second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being preferably based on a chalcogenide material, and [0070] b. A secondary Si-doped crystalline chalcogenide layer over said second undoped crystalline layer, with said secondary Si-doped crystalline chalcogenide layer being based on the same chalcogenide material than said Si-doped crystalline chalcogenide layer.

[0071] As an alternative example of the first aspect of the invention with respect to the preceding one, the material stack may further comprise: [0072] a. a second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being preferably based on a chalcogenide material, and [0073] b. at least one sub-stack over said second undoped crystalline layer, each sub-stack comprising: [0074] i. A secondary Si-doped crystalline chalcogenide layer, and [0075] ii. A secondary undoped crystalline layer over said secondary Si-doped crystalline chalcogenide layer,
with each secondary Si-doped crystalline chalcogenide layer being based on the same chalcogenide material than said Si-doped crystalline chalcogenide layer.

[0076] As an alternative example of the first aspect of the invention with respect to the two preceding ones, the material stack may further comprise: [0077] a. A second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being preferably based on a chalcogenide material, and [0078] b. a secondary Si-doped crystalline chalcogenide layer over said second undoped crystalline layer, with said secondary Si-doped crystalline chalcogenide layer being based on a different chalcogenide material than the one of said Si-doped crystalline chalcogenide layer and/or having a different concentration of Si dopants than the one of said Si-doped crystalline chalcogenide layer.

[0079] As an alternative example of the first aspect of the invention with respect to the three preceding ones, the material stack may further comprise: [0080] a. a second undoped crystalline layer over said Si-doped crystalline chalcogenide layer, with said second undoped crystalline layer having a thickness comprised in between 1 and 20 nm and being preferably based on a chalcogenide material, and [0081] b. at least one sub-stack over said second undoped crystalline layer, each sub-stack comprising: [0082] i. A secondary Si-doped crystalline chalcogenide layer, and [0083] ii. A secondary undoped crystalline layer over said secondary Si-doped crystalline chalcogenide layer,
with at least one secondary Si-doped crystalline chalcogenide layer being based on a different chalcogenide material than the one of said Si-doped crystalline chalcogenide layer and/or having a different concentration of Si dopants than the one of said Si-doped crystalline chalcogenide layer.

[0084] As a further example of the first aspect of the invention and in relation with the three preceding ones, the material stack may further comprise more than one sub-stack. The sub-stacks are preferably subsequently and directly stacked on each other. More particularly, several sub-stacks are stacked on each other until a total thickness of at least 20 nm, preferably 50 nm or more, of the material stack is reached.

[0085] As another example of the first aspect of the invention, said first undoped crystalline layer extending on the substrate may have a thickness comprised in between 4 and 20 nm, preferably in between 4 and 10 nm.

[0086] As another example of the first aspect of the invention, each Si-doped crystalline chalcogenide layer and/or each undoped crystalline chalcogenide layer may be based on a material chosen among: [0087] a. Ge.sub.xSb.sub.yTe.sub.z (GST) where x-y-z are chosen to reach a stoichiometric composition (such as 2-2-5, 1-2-4, 1-4-7; etc.) allowing a deviation of plus or minus 2 at. %, preferably 1 at. %, from a targeted stoichiometric composition, preferably from a perfect one, [0088] b. GeTe, and [0089] c. Sb.sub.2Te.sub.3.

[0090] As another example of the first aspect of the invention, each first undoped crystalline layer extending on the substrate may be based on at least one material chosen among: [0091] a. Sb.sub.2Te.sub.3, [0092] b. Bi.sub.2Te.sub.3, and [0093] c. Sb.sub.2Se.sub.3.

[0094] As another example of the first aspect of the invention, said Si-doped crystalline chalcogenide layer may be doped with Si having an atomic concentration ranging from 0.5 to 20 at. %, and preferably from 2 to 18 at. %, and even more preferably from 2 to 12 at. %.

[0095] As another example of the first aspect of the invention, each Si-doped crystalline chalcogenide layer may have a thickness comprised in between 0,5 and 20 nm, preferably in between 1 and 6 nm.

[0096] As another example of the first aspect of the invention, said Si-doped crystalline chalcogenide layer may extend directly on the first undoped crystalline layer.

[0097] As another example of the first aspect of the invention, the substrate comprises a heater, and the first undoped crystalline layer is over the heater.

[0098] As an example of the second aspect of the invention, said thermally processed Si-doped crystalline chalcogenide layer may have a thickness comprised in between 5 and 100 nm, preferably in between 10 and 100 nm, and even more preferably in between 20 and 80 nm, typically equal to 50 nm.

[0099] As an example of the fourth aspect of the invention, the step of providing a material stack may comprise at least: [0100] a. Providing the substrate, [0101] b. Depositing, on the substrate, a first undoped crystalline layer having a thickness superior to 4 nm, and [0102] c. Depositing, by sputtering or co-sputtering at a temperature comprised in between 150 and 300? C., on the first undoped crystalline layer, a Si-doped crystalline chalcogenide layer doped with less than 20 at. %, and preferably less than 12 at. %, of Si and having a thickness equal to or less than 20 nm.

[0103] More generally, the step of providing a material stack may comprise anyone of the steps of the method for manufacturing a material stack according to the first aspect of the invention.

[0104] As an example of the fourth aspect of the invention, the step of thermal treatment is performed at a temperature comprised in between 200 and 500? C., preferably in between 300 and 400? C.

[0105] As an example of the fourth aspect of the invention, said step of thermal treatment is part of an integration process of the material stack in a microelectronic device.

[0106] As an example of the fourth aspect of the invention, said step of thermal treatment is such that, once thermally processed, said Si-doped crystalline chalcogenide layer has a crystal surface parallel to the substrate equal to or greater than 400 nm.sup.2, preferably equal to or greater than 20 nm?20 nm. The crystal orientation allows a deviation of less than 10? with respect to the substrate.

[0107] As an example of the fourth aspect of the invention, said provided material stack comprises a substrate and a multilayer extending on the substrate, said multilayer comprising a plurality of Si-doped crystalline chalcogenide layers and undoped crystalline chalcogenide layers and having a global thickness comprised in between 5 and 100 nm, preferably in between 10 and 100 nm, and even more preferably in between 20 and 80 nm, typically equal to 50 nm.

[0108] By a parameter equal/greater/less than a given value is meant that this parameter is equal/greater/less than the given value, to plus or minus 20%, or even 10%, close to this value. A parameter comprised in between two given values is meant that this parameter is at least equal to the smallest given value, to plus or minus 20%, or even 10%, near this smallest value, and at most equal to the largest given value, plus or minus 20%, or even 10%, close to this largest value.

[0109] A layer or film based on a material A is understood to mean a film comprising this material A and possibly other materials.

[0110] A crystalline material, or layer, is a solid material, or layer, whose constituents (such as atoms, molecules, or ions) are arranged in a highly ordered microscopic structure, forming a crystal lattice that extends in all directions. A crystalline material, or layer, thus distinguishes from an amorphous material, or layer, and from a polycrystalline material, or layer. All through the present application, word crystalline for specifying a material or a layer may mean formed of crystals having a specific size equal to or greater than 20 nm in x and y directions (parallel to the substrate surface), if needed notably for better distinguishing said crystalline material, or layer, from said polycrystalline material, or layer. Otherwise, the term textured is used to qualify a material exhibiting a crystalline arrangement along a specific direction.

[0111] A monocrystalline material, or layer, is a material, or layer, at least 90% of the structure of which is oriented in the same direction. In the context of the present invention, the first undoped layer is monocrystalline. In the following, the terms monocrystalline and crystalline are used synonymously when referring to this first undoped layer and possibly to the Si-doped chalcogenide layer.

[0112] Epitaxy is a well-known phenomenon of material growth. It is common in minerals which often exhibit special orientation relationships of their lattices. Heteroepitaxy or heterogenous epitaxy is a special case of heterogeneous nucleation in which a distinct crystallographic relationship exists between the orientations of the material of the under layer and the material which is deposited on it. Thus, heteroepitaxy refers to the heterogeneous epitaxial growth of a deposit on an (under)layer of a different material and the formation of bonds at the surfaces between the two materials. A specific type of heteroepitaxy is the Van der Waals epitaxy that refers to the growth mechanism in which the layers are bond together via van der Waals-type weak interactions. This results in far small lattice-mismatch distortion in the grown film even if it has a different lattice constant. In the following, we will refer to heteroepitaxy for the van der Waals type growth.

[0113] By a chalcogenide layer is meant a layer made of a material based on chemical elements in group 16 of the periodic table, and more particularly based on at least one of the following chemical elements: sulfur (S), selenium (Se) and tellurium (Te).

[0114] When a sub-stack or a layer is extending or stacked directly onto another sub-stack or layer, it means that there is no intermediate layer or sub-stack therebetween.

[0115] The detailed description below is concerned by a material stack 10 for a Phase-Change Memory (PCM) device 1 as illustrative embodiment only, since the material stack 10 according to the first aspect of the invention may alternatively be dedicated to different kinds of microelectronic devices 1 as well, and notably to photonics or RF switches microelectronic devices.

[0116] We discuss below the set of conditions for growing a crystalline chalcogenide phase-change material doped with silicon.

[0117] The silicon doping is a source of disorder in the crystalline PCM, as highlighted above, so that the adding of a doping to a chalcogenide material such as Sb.sub.2Te.sub.3 layer could likely perturb its crystalline arrangement, giving rise to a polycristalline material with short range order (below 10 nm), as known from literature and confirmed by the inventor's experiment illustrated on FIG. 1 showing that Si doping induces high disorder during deposition, leading to the loss of the high texture along the 001 direction.

[0118] A big challenge is to make these layers keeping their crystalline arrangement after a BEOL thermal budget (i.e. at 400? C.).

[0119] For achieving this purpose, and by reference to FIGS. 16 to 18B, the use of a first undoped crystalline layer 12, as a buffer layer or equivalently as an under-layer (UL), is provided. Said first undoped crystalline layer 12 has a thickness of few nm (4 nm) and may be based on a chalcogenide material, such as (but not limited to) Sb.sub.2Te.sub.3, which shows crystalline arrangement along (001) planes. The deposition of the first undoped crystalline layer 12 may be done at a deposition temperature in the range 150? C.?T?300? C. This is a typical range for PVD (physical vapor deposition) process, but the first undoped crystalline layer 12 (also called hereafter under-layer or UL) can be deposited with whatever other technique, with the condition to achieve a stoichiometry and crystalline arrangement. For instance, CVD (chemical vapor deposition), ALD (atomic layer deposition), IBD (ion beam deposition), PLD (pulsed laser deposition), MBE (molecular-beam epitaxy), etc. are possible deposition techniques.

[0120] A minimal crystalline arrangement degree is greatly preferred to ensure the growth of a Si-doped crystalline chalcogenide layer 13 on the under-layer 12.

[0121] Others chalcogenide materials can be used for the under-layer 12 such as Bi.sub.2Te.sub.3, Sb.sub.2Se.sub.3, etc.

[0122] On the top of the under-layer 12, it is possible to deposit a chalcogenide layer which has the same crystalline orientation as the under-layer. The crystalline orientation of the under-layer 12 is preferably along the (001) planes. The introduction of a dopant in the grown chalcogenide layer, could affect the right growth of the chalcogenide layer, therefore a set of specific precautions should be adopted.

[0123] It is possible to dope with silicon (Si) most of the chalcogenide materials used for PCM fabrication, such as (but not limited to) Ge.sub.xSb.sub.yTe.sub.z (where x-y-z are favorably chosen to reach stoichiometric compositions such as 2-2-5, 1-2-4, 1-4-7 etc.), GeTe, Sb.sub.2Te.sub.3, etc.

[0124] The deposition of the Si-doped crystalline chalcogenide layer 13 has to be done at a temperature at which the layer material is deposited under its crystalline form that is at a temperature approximately equal to 225? C., typically at a deposition temperature comprised in between 150 and 300? C.

[0125] The crystalline arrangement of the Si-doped crystalline chalcogenide layer 13 does not depend on the material of the substrate 11 on which the deposition is done, as long as the under-layer 12 can accommodate the ordered crystalline orientation. The presence of the under-layer 12 is mandatory to obtain the Si-doped crystalline chalcogenide layer 13 which has a satisfying crystalline arrangement.

[0126] Note here that, in case of PCM fabrication, the deposition of said under-layer 12 and said Si-doped crystalline chalcogenide layer 13 is generally done on a substrate 11 having a heterogeneous surface composed by metals such as TiN, W, TaN, etc. and dielectrics such as SiO.sub.2, SiN, SiC, etc. The largest area on which said under-layer 12 and said Si-doped crystalline chalcogenide layer 13 are deposited may thus be based on an amorphous dielectric material such as SiN or SiO.sub.2.

[0127] The Si-doped crystalline chalcogenide layer 13 thus deposited has a high crystalline arrangement close to the one of the under-layer 12.

[0128] It could be that, moving far from the under-layer 12 along the z direction (perpendicular to the plan of main extension of each layer of the material stack 10), the Si-doped crystalline chalcogenide layer 13 will stay crystalline but with a more and more degraded crystalline arrangement, or even a polycrystalline arrangement, if the thickness of the layer 13 is grown to be superior to 20 nm.

[0129] In order to increase the thickness along which the crystalline arrangement is propagated, and with references to FIG. 17A, it is further possible to deposit a second undoped crystalline layer 14 over said Si-doped crystalline chalcogenide layer 13, and then deposit, on top of layer 14, a secondary Si-doped crystalline chalcogenide layer 13 based on the same material than the one of said Si-doped crystalline chalcogenide layer 13 and having the same concentration of Si dopants.

[0130] As illustrated on FIG. 17B, in order to further increase the thickness along which the crystalline arrangement is propagated, it is also possible to repeat n times depositions of pair(s) of secondary layers 13 and 14 on top of said second undoped crystalline layer 14, if needed before depositing a last secondary Si-doped crystalline chalcogenide layer 13 to form the top layer of the material stack 10. For instance, it is thus possible to repeat such deposits until a total thickness of 100 nm or more of the material stack 10 is reached.

[0131] Said second undoped crystalline layer 14 may have a thickness comprised in between 1 and 20 nm, in order to be textured in a same direction as the under-layer 12. Otherwise, said second undoped crystalline layer 14 is preferably based on a chalcogenide material. For instance, the chalcogenide material of the second undoped crystalline chalcogenide layer 14 may be different from, or the same than, the one of said Si-doped crystalline chalcogenide layer 13. This type of structure, shown on FIGS. 17A and 17B, will be called in the following multi-layer (or ML), in particular by opposition to the embodiment shown on FIG. 16.

[0132] As an alternative to the bi-layer embodiment shown on FIG. 17A, and with references to FIG. 18A, it is possible to deposit, on the second undoped crystalline layer 14, a secondary Si-doped crystalline chalcogenide layer 15 (instead of the one referred to by numeral reference 13 on FIG. 17A), with the chalcogenide material of the secondary Si-doped crystalline chalcogenide layer 15 being different from the one of said Si-doped crystalline chalcogenide layer 13 deposited on the UL 12 and/or having a different concentration of Si dopants than the one of said Si-doped crystalline chalcogenide layer 13.

[0133] As an alternative to the ML as shown on FIG. 17B, and with references to FIG. 18B, it is further possible to alternate secondary undoped crystalline layers 14 (that could range, dependently on the chosen layer, from 1 nm up to 20 nm) and secondary Si-doped crystalline chalcogenide layer(s) 15, 16, 17, etc. (that could range, dependently on the chosen layer, from 0.5 nm up to 20 nm) for achieving a ML textured in a same direction as the under-layer 12 and with: [0134] the chalcogenide material of each of the secondary Si-doped crystalline chalcogenide layers 16, 17, etc. being different from, or the same than, the one of said secondary Si-doped crystalline chalcogenide layer 15 or said Si-doped crystalline chalcogenide layer 13 deposited on the UL 12, and/or [0135] at least one of the secondary Si-doped crystalline chalcogenide layers 16, 17, etc. having a concentration of Si dopants different: [0136] from each other, or [0137] from said secondary Si-doped crystalline chalcogenide layer 15, or [0138] from said Si-doped crystalline chalcogenide layer 13 deposited on the UL 12.

[0139] The higher the thickness of the undoped Si-doped crystalline chalcogenide layer(s) 14, etc., the higher is the control of the crystalline arrangement in the material stack 10 with larger total thickness (i.e. thickness along which the crystalline arrangement is propagated).

[0140] This possibility of growing a stack 10 as shown on FIG. 16 or a multi-layer as shown on FIGS. 17A and 17B with crystalline arrangement has been demonstrated by the inventors in a cosputtering deposition chamber with a process temperature of 210? C., where the used under-layer 12 has a thickness of approximately 6 nm and was made of Sb.sub.2Te.sub.3 showing a crystalline orientation along the (001) planes.

[0141] More particularly, as per the embodiment shown on FIG. 16, the growing of the under-layer 12 with crystalline arrangement has been done by cosputtering of Sb.sub.2Te.sub.3 and Te target(s) to obtain a sufficiently, or even perfectly, stoichiometric film, and the Si-doped crystalline chalcogenide layer 13 was based on either Sb.sub.2Te.sub.3 or Ge.sub.2Sb.sub.2Te.sub.5 (GST) and obtained by the co-sputtering of the chalcogenide target with a Si target.

[0142] In order to enhance the crystalline arrangement of the Si-doped crystalline chalcogenide layers and of the undoped crystalline layers, we may deposit: firstly, the under-layer 12 on the substrate 11 and then we may alternate Ge.sub.2Sb.sub.2Te.sub.5 and Sb.sub.2Te.sub.3, by doping with Si the first deposited one among these two chalcogenide materials.

[0143] The Si doping was obtained by the cosputtering of the stoichiometric chalcogenide material with a silicon target. The Si doping range may be modulated by changing the applied power on the silicon target. The single layer thickness may be varied from approximately 1 nm up to approximately 6 nm according to the studied structure.

[0144] The demonstration of the possibility to obtain a textured ML doped with Si, is shown in the XRD (X-ray Powder Diffraction) spectra as illustrated on FIG. 2, in which the ML without under-layer (curve with long dashes and dots) shows a poor crystallinity while the one with under-layer 12 (curve with dashes) shows very intense peaks: it certifies the high degree of crystallinity of the ML (i.e. crystalline arrangement is preserved despite the Si doping). The quality of the crystallinity was also confirmed by TEM images (See FIGS. 6, 7 and 8).

[0145] The Si doping range that can allow obtaining textured materials is comprised in between 0.5 and 20 at. % of Si.

[0146] More particularly, in the above-mentioned experiment, the upper limit for a Si-doped chalcogenide layer 13 based on Ge.sub.2Sb.sub.2Te.sub.5 is about 15 at. % of Si.

[0147] One way to investigate if the Si-doped chalcogenide layers are textured is the XRD measurement, and more particularly an omega scan at 2Theta angle position of the main peak (equal to 25.5?) for this kind of composition. FIG. 3 shows the impact of the Si doping on such ML structure composed by an under-layer 12 of Sb.sub.2Te.sub.3 textured along the (001) planes and alternating layers of Ge.sub.2Sb.sub.2Te.sub.5 (doped with different at. % of Si) with a thickness of approximately 3.6 nm and Sb.sub.2Te.sub.3 (undoped) with a thickness of approximately 2.1 nm, and a total thickness of about 50 nm (total thickness of the deposited multilayer). We observe that the height of the peak decreases as the atomic percentage of Si dopants increases. This flattening of the omega scans, notably above 12 at. % of Si and below 18 at. % of Si, leads to the upper bound limit for the Si doping in this configuration at about 15 at. % of Si.

[0148] FIG. 4 shows the impact of the thickness of the material stack 10 as illustrated on FIG. 17A: if the Si-doped Ge.sub.2Sb.sub.2Te.sub.5 layer 13 is thinner (for instance 1.8 nm instead of 3.6 nm), the crystalline arrangement degree is higher (the peak of the curve with dots of FIG. 4 is more intense). The under-layer 12 and more generally at least one of the undoped layer(s) 12, 14, and 14 as illustrated on FIGS. 16, 17A, 17B, 18A and 18B has also an important role. For instance, if we increase the thickness(es) of at least one of the undoped layers 12, 14 and 14, still alternating it with the same Si-doped crystalline chalcogenide layer 13 (based for instance on Ge.sub.2Sb.sub.2Te.sub.5), it will increase the global crystalline arrangement degree of the ML structure. This is illustrated by the graph of FIG. 5 wherein the less intense peak (curve with dashes) has been obtained for a second undoped crystalline layer 14 of Sb.sub.2Te.sub.3 of a thickness equal to 2 nm and the more intense peak (curve with long dashes and dots) has been obtained for a second undoped crystalline layer 14 of Sb.sub.2Te.sub.3 of a thickness equal to 6 nm, both structures deposited on a under-layer 12 of Sb2Te3 equal to 6.3 nm and a layer 13 of GST:Si of 3.6 nm.

[0149] The TEM image of FIG. 6 shows, for a multilayer made of undoped Sb.sub.2Te.sub.3 layers 14, 14 and Ge.sub.2Sb.sub.2Te.sub.5:Si8% (i.e. Ge.sub.2Sb.sub.2Te.sub.5 doped with 8 at. % of Si) layers 13, 13, how the multilayer is crystalline with high orientation over the total thickness of 50 nm of the multilayer.

[0150] In the case of Sb.sub.2Te.sub.3 as based material for the Si-doped chalcogenide layer(s) 13, 13 the upper limit of Si doping is about 20 at. % of Si. The same proof than for GST can be provided. The TEM images of FIG. 7 and FIG. 8 show the highly textured as-deposited multilayer obtained by the alternated deposition of undoped Ge.sub.2Sb.sub.2Te.sub.5 14, 14 with a thickness of approximately 3.6 nm and Si-doped Sb.sub.2Te.sub.3:Si12% layer(s) 13, 13 with a thickness of approximately 2.1 nm on an under-layer layer 12 at least partially based on Sb.sub.2Te.sub.3. In this particular case, the second undoped crystalline layer 14 is deposited before the Si-doped chalcogenide layer 13, but it maintains the same crystalline orientation as the UL 12. This configuration represents a possible variant of the stacking. Otherwise, the example shown on FIG. 7 allows illustrating that the UL 12 is not necessarily made of a single layer but can also take the form of a multilayer. Indeed, according to the example shown on FIG. 7, the underlayer is a bilayer made of a first layer based on Sb.sub.2Te.sub.3 extending on the substrate 11 and of a second layer based on Ge.sub.2Sb.sub.2Te.sub.5 extending on the first layer. It should be noted that, in the case of an under-layer 12 taking the form of a bilayer, the second layer is preferably of a thickness less than or equal to half the thickness of the underlying layer.

[0151] From inventor's experience, further thermally treating the multilayer at 400? C. for 15 minutes, thus achieving a thermally processed material stack according to the second aspect of the invention, does not degrade the crystalline arrangement as can be seen by the XRD omega scan shown on FIG. 9 of a multilayer with Si-doped Sb.sub.2Te.sub.3:Si12% layer(s) 13, 13 with a thickness of approximately 2.1 nm and undoped Ge.sub.2Sb.sub.2Te.sub.5 layers 14, 14 with a thickness of approximately 3.6 nm over an under-layer 12 of Sb.sub.2Te.sub.3 with a thickness of approximately 6.3 nm; indeed, where the curve with dashes is obtained by XRD omega scan of the material stack 10 as deposited, that is before any thermal treatment, and the curve with long dashes and dots is obtained by XRD omega scan of the material stack 10 after thermal treatment, the curves are not significantly different from each other.

[0152] The XRD 2Theta-Theta scan as illustrated on FIG. 10 shows how the material stack 10 rearranges: this phenomenon induces the enhancement and the shift of certain XRD peaks.

[0153] In the TEM image of FIG. 11, it can be noticed that the multilayer keeps the crystalline arrangement along the z direction, and we can recognize the alternation of atomic blocks separated by Van Der Waals (VdW) gaps.

[0154] As illustrated on FIG. 12, the EDX images of the material stack 10 after thermal treatment, that is the EDX images of the thermally processed material stack according to the second aspect of the invention, show that the composition of the thermally treated stack is uniform along its thickness losing the multi-layer structure. Also, the silicon is uniformly distributed, without the appearing of any precipitation, which means that the Si dopants accommodate in the crystalline chalcogenide layers 13, 13, 14, and 14.

[0155] It was also noticed that the doping of Ge.sub.2Sb.sub.2Te.sub.5 material with 8 at. % of Si for manufacturing the Si-doped crystalline chalcogenide layer(s) 13, 13, gives rise to the appearing of a new feature as shown for instance on FIGS. 13 and 14. The TEM images illustrated on FIGS. 13 and 14 show the presence of new atomic arrangement with 3-tuple which is not characteristics of any Ge.sub.xSb.sub.yTe.sub.z crystalline block. This new feature can probably be induced by the creation of SiTe bonds and so the arrangement of Si atoms between Te planes, confirming the perfect incorporation of Si in the crystalline structure of the Si-doped chalcogenide layer(s) 13, 13.

[0156] As a comparison with respect to what previously shown, in FIG. 15 is shown the TEM image of a GST124 layer doped with Si deposited on a SiN substrate 11, without under-layer and after annealing at 400? C. The GST124 layer does not show any crystalline arrangement (not even in a direction different from the z one), but only a polycrystalline structure.

[0157] The invention is not limited to the embodiments previously described and extends to all the embodiments covered by the claims.