Signal modulation circuit for solid state electronic device and circuit incorporating the same

Abstract

A circuit includes a first and a second solid state electronic device arranged in a bridge-leg configuration, each selectively operable as a control switch and synchronous switch and each selectively operable in an ON state and OFF state. A driver circuit is operably connected with at least the first solid state electronic device for controlling operation of at least the first solid state electronic device. A signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device and includes an input operably connected with the driver circuit, an output operably connected with the first solid state electronic device, and a variable resistance circuit operably connected between the input and the output and operably connected with the driver circuit. A resistance of the variable resistance circuit is adjustable by the driver circuit to prevent spurious operation of the first solid state electronic device.

Claims

1. A circuit comprising: a first solid state electronic device and a second solid state electronic device arranged in a bridge-leg configuration, the first solid state electronic device and the second solid state electronic device being each selectively operable as a control switch and a synchronous switch and each selectively operable in an ON state and an OFF state; a driver circuit operably connected with at least the first solid state electronic device for controlling operation of at least the first solid state electronic device; and a signal modulation circuit operably connected with or between the driver circuit and the first solid state electronic device, the signal modulation circuit comprising: an input operably connected with the driver circuit; an output operably connected with the first solid state electronic device; and a variable resistance circuit operably connected between the input and the output and operably connected with the driver circuit, wherein a resistance of the variable resistance circuit is adjustable by the driver circuit to prevent spurious operation of the first solid state electronic device.

2. The circuit of claim 1, wherein the resistance of the variable resistance circuit is adjusted by the driver circuit to affect a signal at the output to prevent spurious activation of the first solid state electronic device when the first solid state electronic device is in the OFF state.

3. The circuit of claim 2, wherein the resistance of the variable resistance circuit is adjusted by the driver circuit to affect a signal at the output to prevent spurious activation of the first solid state electronic device when the first solid state electronic device operates as a synchronous switch and is in the OFF state.

4. The circuit of claim 1, wherein the resistance of the variable resistance circuit is adjustable by the driver circuit to affect a signal at the output to prevent spurious operation of the first solid state electronic device.

5. The circuit of claim 1, wherein the first solid state electronic device comprises a field effect transistor with gate, drain, and source.

6. The circuit of claim 5, wherein the field effect transistor comprises a MOSFET such as SiC MOSFET.

7. The circuit of claim 5, wherein the driver circuit comprises a gate driver circuit for the field effect transistor; and wherein the signal modulation circuit is operably connected between the gate driver circuit and the field effect transistor.

8. The circuit of claim 7, wherein the output of the signal modulation circuit is connected across the gate and source of the field effect transistor.

9. The circuit of claim 7, wherein the driver circuit further comprises: a detector circuit operable to detect a gate-source voltage of the field effect transistor; and a control circuit operable to compare the detected gate-source voltage with a reference voltage and to provide a control signal for controlling the resistance of the variable resistance circuit based on the comparison.

10. The circuit of claim 9, wherein the detector circuit comprises an amplifier operably connected with the gate and source of the field effect transistor.

11. The circuit of claim 10, wherein the control circuit comprises: a comparator operably connected with the amplifier for comparing the detected gate-source voltage with the reference voltage; and a controller operably connected with the comparator to provide the control signal.

12. The circuit of claim 11, wherein the control circuit further comprises a latch circuit operably connected with or between the comparator and the controller, wherein the latch circuit is arranged to be in a first state when it is determined that the detected gate-source voltage is larger than the reference voltage and in a second state when it is determined that the detected gate-source voltage is smaller than the reference voltage; wherein the controller is arranged to detect a state of the latch circuit and to provide the control signal based on the detected state of the latch circuit.

13. The circuit of claim 12, wherein the controller is arranged to repeatedly detect the state of the latch circuit hence to provide consecutive control signals for dynamically or adaptively adjusting the resistance of the variable resistance circuit.

14. The circuit of claim 12, wherein the controller is arranged to: provide a first control signal for reducing the resistance of the variable resistance circuit when the latch circuit is detected to be in the first state; and provide a second control signal for increasing the resistance of the variable resistance circuit when the latch circuit is detected to be in the second state.

15. The circuit of claim 14, wherein the first control signal is arranged to reduce the resistance of the variable resistance circuit by a predetermined amount; and wherein the second control signal is arranged to increase the resistance of the variable resistance circuit by a predetermined amount.

16. The circuit of claim 1, wherein the variable resistance circuit comprises a rheostat controllable by the driver circuit to adjust the resistance.

17. The circuit of claim 16, wherein the rheostat comprises a digital rheostat.

18. The circuit of claim 1, wherein the signal modulation circuit comprises: a first resistor-capacitor circuit; a second resistor-capacitor circuit; and a diode circuit; wherein the variable resistance circuit is part of the second resistor-capacitor circuit.

19. The circuit of claim 18, wherein the diode circuit is operably connected between the first resistor-capacitor circuit and the second resistor-capacitor circuit.

20. The circuit of claim 1, further comprising: a processor for determining a gate-oxide health condition of the first solid state electronic device based on the resistance of the variable resistance circuit.

21. The circuit of claim 20, further comprising: a monitoring device or circuit for monitoring resistance of the variable resistance circuit over time; and wherein the processor is arranged to determine the gate-oxide health condition of the first solid state electronic device based on the monitored resistance of the variable resistance circuit over time.

22. The circuit of claim 1, wherein the circuit comprises a converter circuit or an inverter circuit that includes the first solid state electronic device and the second solid state electronic device.

23. A signal modulation circuit for a solid state electronic device of a circuit, wherein the circuit comprises: a first solid state electronic device and a second solid state electronic device arranged in a bridge-leg configuration, the first solid state electronic device and the second solid state electronic device being each selectively operable as a control switch and a synchronous switch and each selectively operable in an ON state and an OFF state; and a driver circuit operably connected with the first solid state electronic device for controlling operation of the first solid state electronic device; wherein the signal modulation circuit is operably connectable with or between the driver circuit and the first solid state electronic device, and comprises: an input operably connectable with the driver; an output operably connectable with the first solid state electronic device; and a variable resistance circuit operably connected between the input and the output and operably connectable with the driver circuit, wherein when the signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device, a resistance of the variable resistance circuit is adjustable by the driver circuit to prevent spurious operation of the first solid state electronic device; and wherein the resistance of the variable resistance circuit is usable for determining gate-oxide health condition of the first solid state electronic device.

24. The signal modulation circuit of claim 23, wherein the resistance of the variable resistance circuit is adjustable by the driver circuit to affect a signal at the output to prevent spurious activation of the first solid state electronic device when the first solid state electronic device operates as a synchronous switch and is in the OFF state.

25. The signal modulation circuit of claim 23, wherein the resistance of the variable resistance circuit is adjustable by the driver circuit to affect a signal at the output to prevent spurious operation of the first solid state electronic device.

26. The signal modulation circuit of claim 23, wherein when the signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device, the signal modulation circuit is operable to receive from the driver circuit: a first control signal for reducing the resistance of the variable resistance circuit by a predetermined amount; and a second control signal for reducing the resistance of the variable resistance circuit by a predetermined amount.

27. The signal modulation circuit of claim 23, wherein the signal modulation circuit comprises: a first resistor-capacitor circuit; a second resistor-capacitor circuit; and a diode circuit operably connected between the first resistor-capacitor circuit and the second resistor-capacitor circuit; wherein the variable resistance circuit is part of the second resistor-capacitor circuit.

28. The signal modulation circuit of claim 23, wherein the variable resistance circuit comprises a rheostat controllable by the driver circuit to adjust the resistance.

29. The signal modulation circuit of claim 28, wherein the rheostat comprises a digital rheostat.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

(2) FIG. 1A is a circuit diagram illustrating a test setup for performing short-circuit-current stress tests on different SiC MOSFETs in one example;

(3) FIG. 1B is a graph showing waveforms of voltage v.sub.g and current i.sub.SC in the circuit of FIG. 1A as detected in the short-circuit-current stress test;

(4) FIGS. 2A to 2G are graphs showing variations of intrinsic parameters of the different SiC MOSFETs before and after the short-circuit-current stress tests: FIG. 2A shows variations of threshold voltage V.sub.th; FIG. 2B shows variations of on-state resistance R.sub.ds,on; FIG. 2C shows variations of drain-source leakage current I.sub.dss; FIG. 2D shows variations of gate-source leakage current I.sub.gss; FIG. 2E shows variations of gate-source capacitance C.sub.gs; FIG. 2F shows variations of drain-source capacitance C.sub.ds; and FIG. 2G shows variations of gate-drain capacitance C.sub.gd;

(5) FIG. 3 is a circuit diagram illustrating a gate drive circuit having an adaptive level shifter with gate voltage detection in one embodiment of the invention;

(6) FIG. 4A is a graph showing waveforms of voltages v.sub.g, v.sub.CN, v.sub.CP, and v.sub.0,LS in the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 1 (ON state);

(7) FIG. 4B is a graph showing waveforms of voltages v.sub.g, v.sub.CN, v.sub.CP, and v.sub.0,LS in the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 2 (OFF state);

(8) FIG. 5A is a circuit diagram illustrating the operation of the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 1 (ON state);

(9) FIG. 5B is a circuit diagram illustrating the operation of the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 2 (OFF state);

(10) FIG. 6 is a flow chart illustrating a control method of the gate drive circuit in FIG. 3;

(11) FIG. 7A is a graph showing relationships between the duty cycle d of the switching device M1 and the resistance R.sub.v with different values of V.sub.REF in the gate drive circuit of FIG. 3;

(12) FIG. 7B is a graph showing relationships between the duty cycle d of the switching device M1 and the resistance R.sub.v with different values of R.sub.gss in the gate drive circuit of FIG. 3;

(13) FIG. 7C is a graph showing relationships between the duty cycle d of the switching device M1 and the resistance R.sub.v with different values of capacitances ?C.sub.gs connected across gate and source terminals of the switching device M1 in the gate drive circuit of FIG. 3;

(14) FIG. 8A shows a circuit diagram of a full-bridge inverter in which the level shifter in the gate drive circuit of FIG. 3 is applied (to switching device M2) in one embodiment of the invention;

(15) FIG. 8B is a picture showing a top view of the full-bridge inverter circuit including the level shifter in the gate drive circuit of FIG. 3 in one embodiment of the invention;

(16) FIG. 8C is a picture showing a bottom view of the full-bridge inverter circuit including the level shifter in the gate drive circuit of FIG. 3 in one embodiment of the invention;

(17) FIG. 9A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(18) FIG. 9B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(19) FIG. 9C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(20) FIG. 10A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(21) FIG. 10B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(22) FIG. 10C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is deactivated;

(23) FIG. 11A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(24) FIG. 11B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(25) FIG. 11C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(26) FIG. 12A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(27) FIG. 12B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(28) FIG. 12C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gd of different capacitances is selectively connected between the gate and drain of the switching device M2 when the gate drive circuit is activated;

(29) FIG. 13A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(30) FIG. 13B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(31) FIG. 13C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(32) FIG. 14A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(33) FIG. 14B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(34) FIG. 14C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(35) FIG. 15A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(36) FIG. 15B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(37) FIG. 15C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(38) FIG. 16A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(39) FIG. 16B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(40) FIG. 16C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when resistor R.sub.gss of different resistances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(41) FIG. 17A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(42) FIG. 17B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(43) FIG. 17C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(44) FIG. 18A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(45) FIG. 18B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(46) FIG. 18C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is deactivated;

(47) FIG. 19A is a graph showing turn-on waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(48) FIG. 19B is a graph showing turn-on waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(49) FIG. 19C is a graph showing turn-on waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(50) FIG. 20A is a graph showing turn-off waveform of the gate-source voltage v.sub.gs,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(51) FIG. 20B is a graph showing turn-off waveform of the drain-source voltage v.sub.ds,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(52) FIG. 20C is a graph showing turn-off waveform of the drain current i.sub.d,2 of the switching device M2 when capacitor ?C.sub.gs of different capacitances is selectively connected between the gate and source of the switching device M2 when the gate drive circuit is activated;

(53) FIG. 21A is a graph showing waveforms of gate-source voltage v.sub.gs,2 and inverter output current i.sub.0 over one line cycle of the switching device M2 when the gate drive circuit is deactivated;

(54) FIG. 21B is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in control mode when the inverter output current i.sub.0 is at about 2 A and the gate drive circuit is deactivated;

(55) FIG. 21C is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in control mode when the inverter output current i.sub.0 is at about 10 A and the gate drive circuit is deactivated;

(56) FIG. 21D is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in synchronous mode when the inverter output current i.sub.0 is at about 2 A and the gate drive circuit is deactivated;

(57) FIG. 21E is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in synchronous mode when the inverter output current i.sub.0 is at about 10 A and the gate drive circuit is deactivated;

(58) FIG. 22A is a graph showing waveforms of gate-source voltage v.sub.gs,2 and inverter output current i.sub.0 over one line cycle of the switching device M2 when the gate drive circuit is activated;

(59) FIG. 22B is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in control mode when the inverter output current i.sub.0 is at about 2 A and the gate drive circuit is activated;

(60) FIG. 22C is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in control mode when the inverter output current i.sub.0 is at about 10 A and the gate drive circuit is activated;

(61) FIG. 22D is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in synchronous mode when the inverter output current i.sub.0 is at about 2 A and the gate drive circuit is activated;

(62) FIG. 22E is a graph showing waveforms of gate-source voltage v.sub.gs,2 of the switching device M2 in synchronous mode when the inverter output current i.sub.0 is at about 10 A and the gate drive circuit is activated; and

(63) FIG. 23 is a functional block diagram of a data processing system in one embodiment of the invention.

DETAILED DESCRIPTION

(64) Inventors of the invention have devised, through research, experiments, and trials, that magnitude of the spurious voltage pulses may depend on various intrinsic and extrinsic factors, such as parasitic elements, drain current, aging condition of switches, etc. Inventors of the invention have realized that a gate driver or a gate drive circuit, if suitably arranged, can adaptively change the off-state negative gate-source voltage to reduce or minimize the voltage stress of the gate oxide hence can extend the lifetime of the switching device.

(65) The following disclosure includes various sections. One of the sections presents experimental results of drift of intrinsic parameters of eight different solid state electronic devices before and after going through short-circuit-current stress cycling for 4000 times. The experimental results show that the magnitude of the spurious voltage pulses diminishes after aging. Another one of the sections presents a gate driver in some embodiments of the invention, which can adjust the off-state gate-source voltage dynamically for counteracting the effect of the spurious voltage pulses. The change of the off-state gate-source voltage can be monitored to determine, indirectly, the aging or health condition of the solid state electronic device switch. Another one of the sections presents an inverter circuit with a gate driver in one embodiment of the invention.

(66) Overview on Change of Intrinsic Parameters after Cycling of the Solid State Electronic Device

(67) To investigate the effect of aging of solid state electronic devices, short-circuit-current stress tests (with 4000 short-circuit-current stress cycles) are performed on eight different solid state electronic devices (in this example, SiC MOSFETs), to determine the drift of seven operation parameters associated with the MOSFETs. These parameters include threshold voltage V.sub.th, on-state resistance R.sub.ds,on, drain-source leakage current I.sub.dss, gate-source leakage current I.sub.gss, gate-source capacitance C.sub.gs, drain-source capacitance C.sub.ds, and gate-drain capacitance C.sub.gd.

(68) Table I contains a list of the eight different SiC MOSFETs used in the test. In the test, the cycling procedure is based on those described in: Fu et. al, Experimental study of 600V GaN transistor under the short-circuit aging tests Mbarek et. al, Gate oxide degradation of SiC MOSFET under short-circuit aging tests, Fu et. al, Evolution of C-V and I-V characteristics for a commercial 600 V GaN GIT power device under repetitive short-circuit tests Douzi et. al, Conducted EMI evolution of power SiC MOSFET in a Buck converter after short-circuit aging tests
FIG. 1A shows the setup used for evaluating each of the eight SiC MOSFETs (each corresponding to a device under test (DUT)). In the test, in each cycle, the MOSFET is turned on for 1000 ?s and then turned off for 4.999 seconds to reduce the effect of self-heating. In other words, each DUT takes 5.56 hours to complete a cycling test. The parameters before and after the cycling are recorded. FIG. 1B shows waveforms of voltage v.sub.g and current i.sub.SC in the setup of FIG. 1A as detected in the short-circuit-current stress test.

(69) TABLE-US-00001 TABLE I List of Power Devices under Test Device Part no. Manufacturer A NTHL080N120SC1A Onsemi B IMW120R060M1HXKSA1 Infineon Technologies C TW070J120B,S1Q Toshiba D SCTW40N120G2V STMicroelectronics E MSC080SMA120B Microchip Technology F LSIC1MO120E0080 Littelfuse G G3R75MT12D GeneSiC Semiconductor H C2M0080120D Wolfspeed

(70) In the test, the threshold voltage V.sub.th is measured by recording the gate-source voltage and drain current when the drain-source voltage V.sub.ds=10V and drain current I.sub.d=5 mA. FIG. 2A shows the changes of the threshold voltage V.sub.th, ranging from 2.7% to 19%. In the graph of FIG. 2A, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(71) In the test, the on-state resistance R.sub.ds,on is measured indirectly by measuring the voltage and current of the SiC MOSFET when V.sub.gs=15V and I.sub.d=20 A. FIG. 2B shows the changes of the on-state resistance R.sub.ds,on, ranging from 11.7% to 33.1%. In the graph of FIG. 2B, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(72) In the test, the drain-source leakage current I.sub.dss is measured under V.sub.ds=100V. FIG. 2C shows the changes of the drain-source leakage current I.sub.dss. The increment is found to be more than 36 times. In the graph of FIG. 2C, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(73) In the test, the gate-source leakage current I.sub.gss, is measured when V.sub.gs=15V. FIG. 2D shows the changes of the gate-source leakage current I.sub.gss, with a significant percentage increment. In the graph of FIG. 2D, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(74) In the test, the gate-source capacitance C.sub.gs is measured by a power device analyzer (Keysight B1506A), when V.sub.ds=0V. FIG. 2E shows the changes of the gate-source capacitance C.sub.gs, ranging from ?3.4% to 61%. In the graph of FIG. 2E, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(75) In the test, the drain-source capacitance C.sub.ds is also measured by the power device analyzer when V.sub.ds=0V. FIG. 2F shows the changes of the drain-source capacitance C.sub.ds, ranging from ?1.6% to 5.5%. If the change of device A is excluded, the changes of the rest of devices dominantly vary between ?1.6% and 0.5%. In the graph of FIG. 2F, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(76) In the test, the gate-drain capacitance C.sub.gd is also measured by the power device analyzer when V.sub.ds=0V. FIG. 2G shows the changes of the gate-drain capacitance C.sub.gd, ranging from 0% to ?24%. In the graph of FIG. 2G, for each of the devices A-H, the bar on the left represents value before the test and the bar on the right represents value after the test (aging).

(77) Based on the obtained test results, it can be determined that all the investigated parameters have different levels of changes after the cycling. Thus, aging of the solid state electronic device can be monitored on the power handling side or the gate driving side. However, if aging of the solid state electronic device is monitored on the power handling side, sophisticated circuits (such as high-voltage and high-current sensing circuits) are required whereas if aging of the solid state electronic device is monitored on the gate driving side, sophisticated circuits may also be needed for extracting individual parameters.

(78) Inventors of the invention have realized that the combined effects of the gate-related parameter changes on the magnitude of spurious voltage can be used to monitor aging of the solid state electronic device, in particular health condition of the gate-oxide of the solid state electronic device. The parameters include I.sub.gss, C.sub.gd, and C.sub.gs. After the cycling, I.sub.gss, increases whereas C.sub.gd and C.sub.gs decrease, thus the magnitude of the spurious voltage decreases. Such information can be used to adjust the negative off-state voltage and monitor device aging.

(79) Circuit with Adaptive Level Shifter

(80) FIG. 3 shows a circuit 300 in one embodiment of the invention. The circuit 300 includes a solid state electronic device M1, a driver circuit operably connected with the solid state electronic device M1 for controlling its operation, and a signal modulation circuit 302 operably connected with/between the driver circuit and the solid state electronic device M1. In this example, the solid state electronic device M1 is selectively operable as a control switch and a synchronous switch and is selectively operable in an ON state and an OFF state. The solid state electronic device M1 may be a MOSFET such as a SiC MOSFET. In this example, the driver circuit and the signal modulation circuit 302 can be considered together, as a gate drive circuit. While not illustrated, it should be noted that the circuit 300 can include at least one further solid state electronic devices operably connected with the solid state electronic device M1, at least one further signal modulation circuit for the at least one further solid state electronic devices, and the driver circuit can be further operably connected with the at least one further solid state electronic devices for controlling its/their operation.

(81) Referring to FIG. 3, the signal modulation circuit 302 includes an input 302A operably connected with the driver circuit, an output 302B operably connected with the solid state electronic device M1, and a variable resistance circuit 302C operably connected between the input 302A and the output 302B and operably connected with the driver circuit. A resistance of the variable resistance circuit 302C is adjustable by the driver circuit to prevent spurious operation of the solid state electronic device M1. In this embodiment, the variable resistance circuit 302C is implemented using a rheostat, in particular a digital rheostat R.sub.v.

(82) The resistance of the variable resistance circuit 302C may be adjusted by the driver circuit to affect a signal at the output 302B to prevent spurious activation (change to ON state) of the solid state electronic device M1 when, or only when, the first solid state electronic device is in the OFF state (e.g., the first solid state electronic device operates as a synchronous switch and is in the OFF state). The resistance of the variable resistance circuit 302C is adjustable by the driver circuit to affect a signal (e.g., voltage signal) at the output 302B to prevent spurious operation of the solid state electronic device M1.

(83) In this example, the driver circuit includes a gate driver circuit for the solid state electronic device M1 and the signal modulation circuit 302 is operably connected between the gate driver circuit and solid state electronic device M1. Specifically the output 302B of the signal modulation circuit 302 is connected across the gate and source of the solid state electronic device M1.

(84) As shown in FIG. 3, the signal modulation circuit 302 includes two resistor-capacitor (RC) circuits and a diode circuit connected between the two RC circuits. One of the RC circuit includes a resistor R.sub.N and a capacitor C.sub.N connected in parallel. The diode circuit includes a diode D.sub.P. Another one of the RC circuit includes a capacitor C.sub.P, two fixed resistance resistors R.sub.A,R.sub.B, and the digital rheostat R.sub.v. Resistor R.sub.B and the rheostat R.sub.v are connected in series. Resistor R.sub.A and the capacitor C.sub.P are connected in parallel. The resistor R.sub.B and the rheostat R.sub.v, combined, are connected in parallel with each of the resistor R.sub.A and the capacitor C.sub.P. The signal modulation circuit 302 can be considered as an adaptive level shifter.

(85) As shown in FIG. 3, the driver circuit includes a detector circuit operable to detect a gate-source voltage of the solid state electronic device M1, and a control circuit operable to compare the detected gate-source voltage with a reference voltage V.sub.REF and to provide a control signal for controlling the resistance of the rheostat R.sub.v based on the comparison. The resistance of the rheostat R.sub.v can affect the gate-source voltage of the solid state electronic device M1. In this embodiment, the detector circuit comprises an amplifier 304 operably connected with the gate and source of the solid state electronic device M1. In this embodiment, the control circuit includes a comparator 306 operably connected with the amplifier 304 for comparing the detected gate-source voltage with the reference voltage V.sub.REF and a controller 308 operably connected with the comparator 306 to provide the control signal to the signal modulation circuit 302. In this embodiment, the control circuit further includes a latch circuit 310 operably connected between the comparator 306 and the controller 308. In this embodiment the controller 308 is a converter controller. In this embodiment the circuit also includes an isolated gate driver 312, in the form of an isolated gate driver IC, electrically connected between the controller 308 and the signal modulation circuit 302. The controller 308 is arranged to provide the gate signal to the isolated gate driver 312. The isolated gate driver 312 may be considered as part of the control circuit. The control circuit may operate when the solid state electronic device M1 is ON and/or when the solid state electronic device M1 is OFF.

(86) The latch circuit 310 is arranged to be in a first state (e.g., HIGH) when it is determined that the detected gate-source voltage is larger than the reference voltage V.sub.REF and in a second state (e.g., LOW) when it is determined that the detected gate-source voltage is smaller than the reference voltage V.sub.REF. The controller 308 can detect a state of the latch circuit 310 and accordingly provide the control signal based on the detected state of the latch circuit 310. In one example, the controller 308 is arranged to detect the state of the latch circuit 310 and to provide the control signal when, or only when, the solid state electronic device M1 is in the OFF state (e.g., the solid state electronic device M1 operates as a synchronous switch and is in the OFF state). The controller 308 can repeatedly (e.g., periodically) detect the state of the latch circuit 310 and provide consecutive control signals for dynamically or adaptively adjusting the resistance of the variable resistance circuit 302C. In this embodiment, the controller 308 is arranged to provide a control signal for reducing the resistance of the variable resistance circuit 302C when the latch circuit 310 is detected to be in the first state and provide a control signal for increasing the resistance of the variable resistance circuit 302C when the latch circuit 310 is detected to be in the second state.

(87) Although not illustrated, in some embodiments, the circuit 300 may further include a processor for determining a health condition, in particular gate-oxide health condition, of the solid state electronic device M1 based on the resistance of the variable resistance circuit 302C. Although not illustrated, in some embodiments, the circuit 300 may further include a monitoring device or circuit for monitoring resistance of the variable resistance circuit 302C over time, and the processor can determine the health condition, in particular gate-oxide health condition, of the solid state electronic device M1 based on the monitored resistance of the variable resistance circuit over time. In some embodiments, the processor may further determine health condition, in particular gate-oxide health condition, of at least one further solid state electronic device based on the resistance of a variable resistance circuit associated with the at least one further solid state electronic device.

(88) Referring back to FIG. 3, in this embodiment the total resistance across C.sub.P is R.sub.P, which equals

(89) $\begin{array}{cc}{R}_P=\frac{R_A\left(R_B+R_v\right)}{R_A+R_B+R_v}& \left(1\right)\end{array}$

(90) When R.sub.v varies between zero (short-circuit condition) and infinity (open-circuit condition), R.sub.P varies between R.sub.P,min and R.sub.P,max. Based on equation (1),

(91) $\begin{array}{cc}{R}_{P,\min }=\frac{R_A{R}_B}{R_A+R_B}& \left(2\right)\end{array}$$\begin{array}{cc}{R}_{P,\max }=R_A& \left(3\right)\end{array}$

(92) The driver output v.sub.g can be switched between 0 and V.sub.GG. For the sake of simplicity in the analysis, the gate of the switching device M1 is modelled by an R.sub.gss-C.sub.gs network shown in FIG. 3.

(93) As mentioned, R.sub.gss is large initially and reduces upon aging. Thus, the impedance of the R.sub.gss-C.sub.gs network is typically larger than the gate resistance R.sub.g, which is not considered in the following analysis for simplicity.

(94) Let d and T be the duty cycle and switching period of M1, respectively.

(95) FIGS. 4A and 4B show waveforms of voltage v.sub.g, the voltage v.sub.CN across C.sub.N, the voltage v.sub.CP across C.sub.P, and the output voltage of the level shifter v.sub.0,LS in the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 1 (ON state) and in Mode 2 (OFF state) respectively.

(96) FIGS. 5A and 5B illustrate operation of the gate drive circuit in FIG. 3 when the switching device M1 operates in Mode 1 (ON state) and in Mode 2 (OFF state) respectively.

(97) Mode 1 corresponds to on-state operation.

(98) Specifically, when M1 is turned on, v.sub.g=V.sub.GG and D.sub.P conducts. Let the forward drop of D.sub.P be zero. The equivalent circuit is shown in FIG. 5A. v.sub.CN, v.sub.CP, and v.sub.0,LS are expressed as

(99) $\begin{array}{cc}{v}_{\mathrm{CN}}\left(R_v,t\right)=v_{\mathrm{CN},\mathrm{ON}}\left(R_{v,t}\right)=\frac{\left(C_N+C_{P,\mathrm{ON}}\right)R_N+\left(C_{P,\mathrm{ON}}{R}_{P,\mathrm{ON}}-C_N{R}_N\right)e^{-\frac{t}{{?}_{\mathrm{ON}}}}}{\left(C_N+C_{P,\mathrm{ON}}\right)\left(R_N+R_{P,\mathrm{ON}}\right)}{V}_{\mathrm{GG}}-\frac{C_{P,\mathrm{ON}}{e}^{-\frac{t}{{?}_{\mathrm{ON}}}}}{C_N+C_{P,\mathrm{ON}}}{V}_{\mathrm{CP}}\left(0^{+}\right)+\frac{C_N{e}^{-\frac{t}{{?}_{\mathrm{ON}}}}}{C_N+C_{P,\mathrm{ON}}}{V}_{\mathrm{CN}}\left(0^{+}\right)& \left(4\right)\end{array}$$\begin{array}{cc}{v}_{\mathrm{CP}}\left(R_v,t\right)=v_{\mathrm{CP},\mathrm{ON}}\left(R_v,t\right)=\frac{\left(C_N+C_{P,\mathrm{ON}}\right)R_{P,\mathrm{ON}}+\left(C_N{R}_N-C_{P,\mathrm{ON}}{R}_{P,\mathrm{ON}}\right)e^{-\frac{t}{{?}_{\mathrm{ON}}}}}{\left(C_N+C_{P,\mathrm{ON}}\right)\left(R_N+R_{P,\mathrm{ON}}\right)}{V}_{\mathrm{GG}}+\frac{C_{P,\mathrm{ON}}{e}^{-\frac{t}{{?}_{\mathrm{ON}}}}}{C_N+C_{P,\mathrm{ON}}}{V}_{\mathrm{CP}}\left(0^{+}\right)-\frac{C_N{e}^{-\frac{t}{{?}_{\mathrm{ON}}}}}{C_N+C_{P,\mathrm{ON}}}{V}_{\mathrm{CN}}\left(0^{+}\right)& \left(5\right)\end{array}$$\begin{array}{cc}{v}_{o,\mathrm{LS}}\left(R_v,t\right)=v_{o,\mathrm{LS},\mathrm{ON}}\left(R_v,t\right)=v_{\mathrm{CP},\mathrm{ON}}\left(R_v,t\right)& \left(6\right)\end{array}$
where t?[0 dT], V.sub.CN(0.sup.+) and V.sub.CP(0.sup.+) are the initial voltages of C.sub.N and C.sub.P, respectively,

(100) ${?}_{\mathrm{ON}}=C_{\mathrm{eq},\mathrm{ON}}{R}_{\mathrm{eq},\mathrm{ON}},C_{\mathrm{eq},\mathrm{ON}}=C_N+C_{P,\mathrm{ON}},R_{\mathrm{eq},\mathrm{ON}}=\frac{R_N{R}_{P,\mathrm{ON}}}{R_N+R_{P,\mathrm{ON}}},C_{P,\mathrm{ON}}=C_P+C_{\mathrm{gs}},\mathrm{and}{R}_{P,\mathrm{ON}}=\frac{R_P{R}_{\mathrm{gss}}}{R_P+R_{\mathrm{gss}}}.$

(101) At the end of Mode 1, v.sub.CN=v.sub.CN,ON,f, v.sub.CP=v.sub.CP,ON,f, and v.sub.0,LS=v.sub.0,LS,ON,f. They can be expressed as
V.sub.CN,ON,f=v.sub.CN,ON(R.sub.v,dT)(7)
V.sub.0,LS,ON,f=V.sub.CP,ON,f=v.sub.CP,ON(R.sub.v,dT)(8)

(102) Mode 2 corresponds to off-state operation,

(103) Specifically, when M1 is turned off, v.sub.g=0 and D.sub.P blocks. The equivalent circuit is shown in FIG. 5B. v.sub.CN, v.sub.CP, and v.sub.0,LS are expressed as

(104) $\begin{array}{cc}{v}_{\mathrm{CN}}\left(t\right)=v_{\mathrm{CN},\mathrm{OFF}}\left(t\right)=e^{-\frac{t-\mathrm{dT}}{{?}_{\mathrm{OFF}}}}{V}_{\mathrm{CN}}\left({\mathrm{dT}}^{+}\right)& \left(9\right)\end{array}$$\begin{array}{cc}{v}_{\mathrm{CP}}\left(t\right)=v_{\mathrm{CP},\mathrm{OFF}}\left(t\right)=e^{-\frac{t-\mathrm{dT}}{{?}_{\mathrm{CP}}}}{V}_{\mathrm{CP}}\left({\mathrm{dT}}^{+}\right)& \left(10\right)\end{array}$$\begin{array}{cc}{v}_{o,\mathrm{LS}}\left(t\right)=v_{o,\mathrm{LS},\mathrm{OFF}}\left(t\right)=-v_{\mathrm{CN},\mathrm{OFF}}\left(t\right)& \left(11\right)\end{array}$
where t?[0 dT], V.sub.CN(dT.sup.+) and V.sub.CP(dT.sup.+) are the initial voltages of C.sub.N and C.sub.P, respectively,

(105) ${?}_{\mathrm{OFF}}=C_{\mathrm{eq},\mathrm{OFF}}{R}_{\mathrm{eq},\mathrm{OFF}},C_{\mathrm{eq},\mathrm{OFF}}=C_N+C_{\mathrm{gs}},R_{\mathrm{eq},\mathrm{OFF}}=\frac{R_N{R}_{\mathrm{gss}}}{R_N+R_{\mathrm{gss}}},\mathrm{and}{?}_{\mathrm{CP}}=C_P{R}_P.$

(106) At the end of Mode 2, v.sub.CN=v.sub.CN,OFF,f, v.sub.CP=v.sub.CP,OFF,f, and v.sub.0,LS=v.sub.0,LS,OFF,f. They can be expressed as
V.sub.0,LS,OFF,f=?V.sub.CN,OFF,f=?v.sub.CN,OFF(R.sub.v,(1?d)T)(12)
V.sub.CP,OFF,f=v.sub.CP,OFF(R.sub.v,(1?d)T)(13)

(107) FIGS. 4A and 4B show the initial and final conditions of the capacitor voltages. The initial conditions of one mode are obtained from the final conditions of its previous mode.

(108) For Mode 1, by applying the law of conservation of charge, V.sub.CN(0.sup.+) and V.sub.CP(0.sup.+) can be expressed as

(109) $\begin{array}{cc}{V}_{\mathrm{CN}}\left(0^{+}\right)=\frac{\left(C_P+C_{\mathrm{gs}}\right)V_{\mathrm{GG}}+\left(C_N+C_{\mathrm{gs}}\right)V_{\mathrm{CN},\mathrm{OFF},f}-C_P{V}_{\mathrm{CP},\mathrm{OFF},f}}{C_N+C_P+C_{\mathrm{gs}}}& \left(14\right)\end{array}$$\begin{array}{cc}{V}_{o,\mathrm{LS}}\left(0^{+}\right)=V_{\mathrm{CP}}\left(0^{+}\right)=V_{\mathrm{GG}}-V_{\mathrm{CN}}\left(0^{+}\right)=\frac{C_N{V}_{\mathrm{GG}}-\left(C_N+C_{\mathrm{gs}}\right)V_{\mathrm{CN},\mathrm{OFF},f}+C_P{V}_{\mathrm{CP},\mathrm{OFF},f}}{C_N+C_P+C_{\mathrm{gs}}}& \left(15\right)\end{array}$
where V.sub.0,LS(0.sup.+) is the initial output voltage of the level shifter in Mode 1.

(110) For Mode 2, V.sub.CN(dT.sup.+) and V.sub.CP(dT.sup.+) can be expressed as

(111) $\begin{array}{cc}{V}_{o,\mathrm{LS}}\left({\mathrm{dT}}^{+}\right)=V_{\mathrm{CN}}\left({\mathrm{dT}}^{+}\right)=\frac{C_N{V}_{\mathrm{CN},\mathrm{ON},f}-C_{\mathrm{gs}}{V}_{\mathrm{CP},\mathrm{ON},f}}{C_N+C_{\mathrm{gs}}}& \left(16\right)\end{array}$$\begin{array}{cc}{V}_{\mathrm{CP}}\left({\mathrm{dT}}^{+}\right)=V_{\mathrm{CP},\mathrm{ON},f}& \left(17\right)\end{array}$
where V.sub.0,LS(dT.sup.+) is the initial output voltage of the level shifter in Mode 2.

(112) If V.sub.CN(0.sup.+)<V.sub.CN,ON,f, the voltage of C.sub.N will increase when the gate signal is V.sub.GG, as shown in FIG. 4A. If V.sub.CN(0.sup.+)>V.sub.CN,ON,f, the voltage of C.sub.N will decrease when the gate signal is V.sub.GG, as shown in FIG. 4B.

(113) In this embodiment, the off-State Voltage of the device M1 can be regulated.

(114) Specifically, the shifting level of v.sub.0,LS is varied by changing the value of R.sub.v, so that the spurious voltage is less than a threshold voltage of M1. A spurious voltage typically occurs when the complementary power device is turned on. That is, it appears after M1 has entered Mode 2 with a deadtime of t.sub.d. Based on equation (9):

(115) $\begin{array}{cc}-e^{-\frac{t_d}{{?}_{\mathrm{OFF}}}}{V}_{\mathrm{CN}}\left({\mathrm{dT}}^{+}\right)?V_{\mathrm{REF}}& \left(18\right)\end{array}$

(116) As illustrated in FIG. 3, when M1 has entered Mode 2, the gate-source voltage v.sub.gs is sensed and compared with a reference voltage V.sub.REF. The output of the comparator is latched to give the signal v.sub.L. The peak spurious voltage is regulated around V.sub.REF via a peak voltage control.

(117) FIG. 6 illustrates the control method 600 of the gate drive circuit in FIG. 3. In this embodiment, after two deadtime intervals, i.e., 2t.sub.d, the controller 308 will check the input pin IN1 for v.sub.L once. If v.sub.L is HIGH, it implies that v.sub.gs>V.sub.REF. The controller 308 will decrease the value of R.sub.v by ?R.sub.v, which is equal to unit change of R.sub.v. For example, the 8-bit rheostat used in the experiment has a maximum value of 20 k?. Thus, ?R.sub.v=20 k?/255=78.43?. If v.sub.L is LOW, it implies that v.sub.gs<V.sub.REF. The controller 308 will increase the value of R.sub.v by ?R.sub.v.

(118) The gate drive circuit in FIG. 3 further enables or facilities condition monitoring of switching device M1.

(119) Generally, for healthy switch devices, the spurious voltage for certain loading condition is consistent, and the required R.sub.v to control the gate-source voltage is also consistent. When I.sub.gss increase, it decreases the gate source voltage. The adaptive level shifter will increase R.sub.v to compensate the effect from I.sub.gss. Thus, by monitoring the value of R.sub.v, the increase of I.sub.gss can be monitored, and the health of the switching device can be monitored.

(120) Table II lists the components and their part number or value used in one example.

(121) TABLE-US-00002 TABLE II List of Components Parameter Part no./Value Parameter Part no./Value C.sub.N 47 nF R.sub.N 100 ? C.sub.P 4.7 nF R.sub.A 47 k? C.sub.gs 660 pF R.sub.B 10 ? V.sub.GG 15 V R.sub.v,max 10 k? t.sub.d 400 ns R.sub.g 12 ? D.sub.P 1N4148

(122) FIG. 7A shows the relationships between the duty cycle d and R.sub.v with different values of V.sub.REF. The value of R.sub.gss is assumed to be infinite under the healthy condition. The information in Table II applies. The value of R.sub.v can adjust the off-state voltage so that the condition of equation (18) can be satisfied. For the same duty cycle and loading condition, R.sub.v increases as the magnitude of the spurious voltage decreases. For example, an aged switching device has a smaller value of C.sub.gd than that in the healthy condition, giving a lower spurious voltage.

(123) FIG. 7B shows the relationships between d and R.sub.v with R.sub.gss equal to infinity, 10 k?, 5 k?, 1 k?, and 100? to represent different levels of degradation. The value of V.sub.REF is set at ?4V. Since R.sub.gss is in parallel with C.sub.P, under the same duty cycle, the required values of R.sub.v will increase as R.sub.gss decreases.

(124) FIG. 7C shows the relationships between d and R.sub.v with additional capacitance ?C.sub.gs connected across gate and source terminals. ?C.sub.gs equals 0 pF, 50 pF, 150 pF, 250 pF and 350 pF to represent different levels of degradation. The value of V.sub.REF is set at ?4V and R.sub.gss is infinitive. The required values of R.sub.v increases as C.sub.gs decreases.

(125) Based on FIGS. 7A to 7C, it can be determined that by observing the change of R.sub.v at the considered duty cycle and loading condition, the condition of the switching device can be monitored.

(126) An example design procedure of the signal modulation circuit 302 in FIG. 3 is now presented.

(127) In one embodiment, the values of C.sub.N, C.sub.P, R.sub.N, R.sub.A, and R.sub.B, are designed by considering the following design criteria: 1) V.sub.0,LS,inf(dT.sup.+): Initial off-state gate-source voltage when R.sub.v.fwdarw.?, i.e., upon open-circuit fault in R.sub.v 2) V.sub.0,LS,max(dT.sup.+): Initial off-state gate-source voltage when R.sub.v=R.sub.v,max(maximum value of R.sub.v) 3) V.sub.0,LS,min(dT.sup.+): Initial off-state gate-source voltage when R.sub.v=0 (minimum value of R.sub.v)

(128) Step 1 of the design procedure includes design of R.sub.N, R.sub.A, and R.sub.B. By considering the steady-state gate-source voltage with different values of R.sub.v, it can be shown that

(129) 0$\begin{array}{cc}\frac{R_A}{R_A+R_N}=\frac{V_{\mathrm{GG}}+V_{o,\mathrm{LS},\inf }\left({\mathrm{dT}}^{+}\right)}{V_{\mathrm{GG}}}& \left(19\right)\end{array}$$\begin{array}{cc}\frac{R_A.Math.\left(R_B+R_{v,\max }\right)}{R_N+\left(R_A.Math.\left(R_B+R_{v,\max }\right)\right)}=\frac{V_{\mathrm{GG}}+V_{o,\mathrm{LS},\max }\left({\mathrm{dT}}^{+}\right)}{V_{\mathrm{GG}}}& \left(20\right)\end{array}$$\begin{array}{cc}\frac{R_A.Math.R_B}{R_N+\left(R_A.Math.R_B\right)}=\frac{V_{\mathrm{GG}}+V_{o,\mathrm{LS},\min }\left({\mathrm{dT}}^{+}\right)}{V_{\mathrm{GG}}}& \left(21\right)\end{array}$
Thus, R.sub.N, R.sub.A, and R.sub.B are determined by solving (19), (20), and (21).

(130) Step 2 of the design procedure includes design of C.sub.P. In this example the value of C.sub.P is chosen to be at least ten times larger than C.sub.gs, so that the operation of the level shifter will not be dominated by C.sub.gs in Mode 1 operation.

(131) Step 1 of the design procedure includes design of C.sub.N. In this example the value of C.sub.N is determined by considering the designed nominal value of R.sub.v, R.sub.v,norm. Thus, the time constants of the two RC networks are designed to be substantially the same. Thus,

(132) $\begin{array}{cc}{C}_N=\frac{\left(R_{v,\mathrm{norm}}+R_B\right).Math.R_A}{R_N}{C}_P& \left(22\right)\end{array}$

Experimental Verification

(133) The performance of the level shifter of the circuit 300 of FIG. 3 is evaluated on a 1 kW, 400 Vdc/115 Vac full-bridge inverter. The output LC filter is constructed by an inductor L.sub.0=0.7 mH and a capacitor C.sub.0=1 ?F.

(134) FIG. 8A shows a full-bridge inverter in which the level shifter in the gate drive circuit of FIG. 3 (not shown) is applied to switching device M2. FIGS. 8B and 8C show the full-bridge inverter circuit including the level shifter in the gate drive circuit of FIG. 3 as constructed.

(135) In this example the nominal value of the load resistance R.sub.L=13.7?. The switching frequency is 45 kHz. All switching devices are CREE C3M0065090J with the threshold voltage of 2.1V and maximum allowable reverse gate?source voltage of ?8V. The gate drivers are Skywork SI8233 with the supply voltage of 15V.

(136) In this example, the switching device M2 is connected with the level shifter, while the rest of switching devices are driven by the gate drivers with RCD level shifters, with the voltage shifted downward by 6V. Details of the RCD level shifters can be found in Wang et. al, A Novel RCD Level Shifter for Elimination of Spurious Turn-on in the Bridge-Leg Configuration, the entire contents of which is incorporated by reference herein.

(137) The level shifter for M2 is designed by following the design procedure described above and the component values are listed in Table II.

(138) Different levels of crosstalk effect are emulated by increasing the equivalent gate-drain capacitance with external capacitors and reducing the equivalent gate-source resistance and capacitance. The system is tested without and with the dynamic gate-source voltage control included.

(139) The effects of C.sub.gd is studied.

(140) The off-state voltage is shifted downward by 6V with the RCD level shifter. FIGS. 9A to 9C respectively show the turn-on waveforms of the gate-source voltage v.sub.gs,2, drain-source voltage v.sub.ds,2, and drain current i.sub.d,2 of M2 when a capacitor ?C.sub.gd is connected between the gate and drain terminals of M2 (when the gate drive circuit is deactivated). The value of ?C.sub.gd under test includes 10 pF, 20 pF, 30 pF, 40 pF, and 50 pF, respectively. FIGS. 10A to 10C respectively show the turn-off waveforms of the gate-source voltage v.sub.gs,2, drain-source voltage v.sub.dS,2, and drain current i.sub.d,2 of M2 when a capacitor ?C.sub.gd is connected between the gate and drain terminals of M2 (when the gate drive circuit is deactivated). The magnitude of the spurious voltage is 0.7V, 1.6V, 2.2V, 2.9V, 3.7V, 4.1V, respectively. Thus, when the externally added capacitor is 50 pF, the off-state gate-source voltage reaches ?2V. Thus, with the gate-drain capacitance further increased, undesired shoot through might occur.

(141) FIGS. 11A to 11C respectively show the turn-on waveforms of the gate-source voltage v.sub.gs,2, drain-source voltage v.sub.ds,2, and drain current i.sub.d,2 of M2 when a capacitor ?C.sub.gd is connected between the gate and drain terminals of M2 (when the gate drive circuit is activated). FIGS. 12A to 12C respectively show the turn-off waveforms of the gate-source voltage v.sub.gs,2, drain-source voltage v.sub.ds,2, and drain current i.sub.d,2 of M2 when a capacitor ?C.sub.gd is connected between the gate and drain terminals of M2 (when the gate drive circuit is activated). It can be seen that with the off-state gate-source voltage control activated, the spurious voltage is regulated below ?1V, i.e., V.sub.REF=?1V.

(142) Comparing FIGS. 9A-9C with FIGS. 11A-11C, the profiles of the gate-source voltage are generally similar, both are close to zero near the end of the switching cycle.

(143) FIGS. 12A to 12C shows that, depending on the value of ?C.sub.gd, v.sub.gs,2 varies between ?3.5V and ?6.4V immediately after turning off. The peak off-state gate voltage caused by the crosstalk is kept at ?1V by decreasing R.sub.v. It gradually increases until the end of switching cycle. Hence, this can reduce the average voltage stress on the gate oxide.

(144) Table III shows a comparison of the measured power losses of M2 with the dynamic and fixed off-state voltage control, respectively.

(145) TABLE-US-00003 TABLE III Power Losses of M2 under Different ?C.sub.gd ?C.sub.gd (pF) P.sub.L,act*(W) P.sub.L,deact*(W) ?P.sub.L (%) 0 12.5 12.8 2.2 10 12.4 12.6 1.4 20 12.2 12.7 3.6 30 12.3 12.8 3.4 40 12.9 13.3 3.3 50 13.8 14.5 4.5 *Note: P.sub.L,act: Power loss of M2 with the dynamic gate-source voltage control activated P.sub.L,deact: Power loss of M2 with the dynamic gate-source voltage control deactivated $?P_L:\mathrm{Percentage}\mathrm{difference},{\mathrm{?P}}_L=\frac{\left(P_{L,\mathrm{deact}-P_{L,\mathrm{act}}}\right)?100\%}{P_{L,\mathrm{act}}}$

(146) The results show that the dynamic one gives a lower power loss than the fixed one. When ?C.sub.gd=50 pF, the gate-source voltage with dynamic and fixed off-state voltage control are designed to be the same under this worst-case condition. When the switch is in control mode, the power dissipation is lower with the dynamic off-state voltage control than the fixed one, because the on-state resistance and the off-state voltage stress are also reduced.

(147) The dynamic control gives lower power losses for at least two reasons. First, the on-state gate-source voltage can dynamically change with C.sub.gd. Upon the reduction of C.sub.gd, the gate-source voltage is increased. Thus, the power loss reduces as the on-state resistance reduces. Second, as the off-state gate-source voltage is reduced dynamically, the reverse conduction loss can also be reduced.

(148) The effect of R.sub.gss is studied.

(149) FIGS. 13A to 13C show the turn-on waveforms when a resistor R.sub.gss is connected between the gate and source of M2 (when the gate drive circuit is deactivated). The value of R.sub.gss is 10 k?, 4.7 k?, 1 k?, 470?, and 100?, respectively. The magnitude of the spurious voltage slightly reduces as R.sub.gss reduces.

(150) FIGS. 14A to 14C show the turn-off waveforms when a resistor R.sub.gss is connected between the gate and source of M2 (when the gate drive circuit is deactivated). When R.sub.gss=100?, the on-state gate-source voltage drops to 6V while the off-state gate-source voltage drops to ?8V. It is mainly due to the loading effect of R.sub.gss on the level shifter. Thus, the off-state voltage stress on the gate oxide of the switching device increases.

(151) FIGS. 15A to 15C show the turn-on waveforms when a resistor R.sub.gss is connected between the gate and source of M2 (when the gate drive circuit is activated). FIGS. 16A to 16C show the turn-off waveforms when a resistor R.sub.gss is connected between the gate and source of M2 (when the gate drive circuit is activated).

(152) Comparing FIGS. 15A-15C with FIGS. 13A-13C, the profiles of the gate-source voltage under different R.sub.gss are similar, both are close to zero near the end of the switching cycle. FIGS. 15A-15C show that the off-state gate-source voltage control keeps v.sub.gs,2 at ?2.4V immediately after turning off the switch with R.sub.gss varying between 470? and 10 k?, giving rise a lower off-state voltage on the gate oxide. The peak off-state gate-source voltage caused by the crosstalk is also regulated at ?1V by reducing R.sub.v. With R.sub.gss=100? (an extreme case), the control fails to perform the regulation. Thus, based on observing the value of R.sub.v, it is possible to monitor the change of R.sub.gss.

(153) Table IV shows a comparison of the measured power losses of M2 with the dynamic and fixed off-state voltage control, respectively, when R.sub.gss is reduced from ? to 100?.

(154) TABLE-US-00004 TABLE IV Power Losses of M2 under DifferentR.sub.gss R.sub.gss (?) P.sub.L,act*(W) P.sub.L,deact*(W) ?P.sub.L (%) ? 11.8 12.2 3.4 10k 11.7 12.6 7.7 4.7k 11.8 12.5 5.9 1k 11.8 12.8 8.5 470 11.8 12.9 9.3 100 13.3 14.5 9 *Note: P.sub.L,act: Power loss of M2 with the dynamic gate-source voltage control activated P.sub.L,deact: Power loss of M2 with the dynamic gate-source voltage control deactivated $?P_L:\mathrm{Percentage}\mathrm{difference},?P_L=\frac{\left(P_{L,\mathrm{deact}-P_{L,\mathrm{act}}}\right)?100\%}{P_{L,\mathrm{act}}}$

(155) The dynamic one gives a lower power loss than the fixed one for two main reasons. First, the on-state gate-source voltage is dynamically changed with R.sub.gss. Upon the reduction of R.sub.gss, R.sub.v is increased to regulate the gate-source voltage. The on-state gate-source voltage is higher. Thus, the power loss is lower. Second, as the off-state gate-source voltage is reduced dynamically, the reverse conduction loss can also be reduced.

(156) The effect of C.sub.gs is studied.

(157) FIGS. 17A to 17C show the turn-on waveforms when a capacitor is connected between the gate and source terminals of M2 (when the gate drive circuit is deactivated). FIGS. 18A to 18C show the turn-off waveforms when a capacitor is connected between the gate and source terminals of M2 (when the gate drive circuit is deactivated). The value of ?C.sub.gs under test includes 0 pF, 50 pF, 150 pF, 250 pF and 350 pF, respectively. It has a little effect on the magnitude of the spurious voltage. The on-state gate-source voltage is also kept at 10V at the end of the switching cycle in all cases. Since C.sub.P is designed to be much larger than gate-source capacitance, the value of ?C.sub.gs gives little impact on the equivalent capacitance in Mode 1.

(158) FIGS. 19A to 19C show the turn-on waveforms when a capacitor is connected between the gate and source terminals of M2 (when the gate drive circuit is activated). FIGS. 20A to 20C show the turn-off waveforms when a capacitor is connected between the gate and source terminals of M2 (when the gate drive circuit is activated). The spurious voltage is regulated below ?1V. Comparing FIGS. 19A-19C with FIGS. 17A-17C, the profiles of the gate-source voltage are similar, both are close to zero near the end of the switching cycle. Comparing FIGS. 20A-20C with FIGS. 18A-18C. The profiles of the gate-source voltage are all similar, irrespective to ?C.sub.gs, showing that ?C.sub.gs has limited loading effect on the circuit.

(159) Table V shows a comparison of the measured power losses of M2 with the dynamic and fixed off-state voltage control, respectively. As ?C.sub.gs increases, the turn-on and turn-off times are both increased, resulting in a higher switching loss. As the dynamic off-state voltage control does not change the turn-on and turn-off waveforms, the power losses with the dynamic and fixed off-state voltage control are not affected much.

(160) TABLE-US-00005 TABLE V Power Loss on the Switch for Variable C.sub.gs ?C.sub.gs (pF) P.sub.L,act*(W) P.sub.L,deact*(W) ?P.sub.L (%) 0 12.6 12.7 0.4 50 12.5 12.6 0.9 150 12.7 12.8 0.7 250 13.2 13.1 ?0.8 350 13.3 13.3 0.2 *Note: P.sub.L,act: Power loss of M2 with the dynamic gate-source voltage control activated P.sub.L,deact: Power loss of M2 with the dynamic gate-source voltage control deactivated $?P_L:\mathrm{Percentage}\mathrm{difference},?P_L=\frac{\left(P_{L,\mathrm{deact}-P_{L,\mathrm{act}}}\right)?100\%}{P_{L,\mathrm{act}}}$

(161) FIGS. 21A to 21E illustrate the situation without the gate driver (or not operating). FIG. 21A shows the waveforms of v.sub.gs,2 and the inverter output current i.sub.0 over one line cycle. FIGS. 21B and 21C show the waveforms when i.sub.0??2 A and i.sub.0??10 A, respectively, and M2 is in control mode. FIGS. 21D and 21E show the waveforms when i.sub.0??2 A and i.sub.0??10 A, respectively, and M2 is in synchronous mode. Due to the load current variation, the magnitude of the spurious voltage varies accordingly. FIG. 21C shows a more negative off-state voltage than that in FIG. 21B, because of the difference in the duty cycle. FIG. 21D shows that the peak spurious voltage is below V.sub.REF, while FIG. 21E shows that the peak spurious voltage is the same as V.sub.REF.

(162) FIGS. 22A to 22E illustrate corresponding waveforms and with the without the gate driver operating). R.sub.v and thus v.sub.gs,2 are varied to regulate the off-state peak spurious voltage at V.sub.REF. FIGS. 22B and 22C show that the gate-source voltage after the dead time, i.e., 400 ns, is regulated at ?1V. FIGS. 22D and 22E show the waveforms, when i.sub.0?2 A and i.sub.0?10 A, respectively, and M2 is in synchronous mode. The peak spurious voltage is V.sub.REF in both cases. The magnified waveform of v.sub.gs,2 with i.sub.0=2 A and i.sub.0=10 A confirm such voltage regulation control.

(163) The above embodiments of the invention have provided a circuit, e.g., an adaptive gate driver, which can adjust the off-state gate-source voltage to counteract the spurious voltage caused by crosstalk effect. The above embodiments of the invention have provided a circuit, e.g., an adaptive gate driver, that can be used to monitor the health condition of a solid state electronic device (e.g., switch) directly by observing the change of the voltage level. An optimal off-state gate-source voltage for the switch can address the crosstalk issue and can potentially improve the life expectancy of the switch. The technique is evaluated on a 1 kW inverter. By introducing different values of gate-drain capacitance, gate-source resistance, and gate-source capacitance, the results in the above disclosure show that the peak spurious voltage caused by crosstalk is regulated, and that the power loss is less than the driver with a fixed off-state gate-source voltage.

(164) FIG. 23 shows an example data processing system 2300 in one embodiment of the invention. The data processing system 2300 can be used to process data, e.g., measured resistance R.sub.v, for determining or facilitate determining of health condition of a solid state electronic device (e.g., the switching device in the above embodiments). The data processing system 2300 generally comprises suitable components necessary to receive, store, and execute appropriate computer instructions, commands, and/or codes. The main components of the data processing system 2300 are a processor 2302 and a memory (storage) 2304. The processor 2302 may include one or more: CPU(s), MCU(s), logic circuit(s), Raspberry Pi chip(s), digital signal processor(s) (DSP), application-specific integrated circuit(s) (ASIC), field-programmable gate array(s) (FPGA), and/or any other digital or analog circuitry/circuitries configured to interpret and/or to execute program instructions and/or to process signals and/or information and/or data. The memory 2304 may include one or more volatile memory (such as RAM, DRAM, SRAM), one or more non-volatile memory (such as ROM, PROM, EPROM, EEPROM, FRAM, MRAM, FLASH, SSD, NAND, NVDIMM), or any of their combinations. Appropriate computer instructions, commands, codes, information and/or data may be stored in the memory 2304. Computer instructions for executing or facilitating executing the method embodiments of the invention may be stored in the memory 2304. The processor 2302 and memory (storage) 2304 may be integrated or separated (and operably connected). A person skilled in the art would appreciate that the data processing system 2300 shown in FIG. 23 is merely an example and that the data processing system 2300 can in other embodiments have different configurations (e.g., include additional components, has fewer components, etc.).

(165) Some embodiments of the invention have provided a circuit that can ensure or guarantee normal operation of a solid state electronic device in a converter/inverter circuit under spurious voltage. Some embodiments of the invention have provided a circuit that can optimize the voltage to extend the lifetime of the solid state electronic device and monitoring the health condition of the solid state electronic device. Some embodiments of the invention can adapt the loading condition of the solid state electronic device (or the converter incorporating the solid state electronic device) to give optimized voltage. Some embodiments of the invention can provide built-in health condition monitoring of the solid state electronic device (or the converter incorporating the solid state electronic device), with requiring extra or substantial components.

(166) The circuit of the invention can be applied to various power electronic circuits and devices, such as solar inverters, power supplies, etc.

(167) It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments to provide other embodiments of the invention. The described embodiments of the invention should therefore be considered in all respects as illustrative, not restrictive. Example optional features of some aspects of the invention are set forth in the summary section above. Some embodiments of the invention may include one or more of these optional features (some of which are not specifically illustrated in the drawings). Some embodiments of the invention may lack one or more of these optional features (some of which are not specifically illustrated in the drawings). One or more features in one embodiment and one or more features in another embodiment may be combined to provide further embodiment(s) of the invention. For example, the circuit and method of the invention can be applied to other solid state electronic device(s) not limited to MOSFET or SiC MOSFET. For example, the illustrated circuit components can be implemented using equivalent circuit arrangement or components. For example, the signal modulation circuit can be used in different types of converter or inverter circuits with bridge-leg configured solid state electronic devices (two or more). The variable resistance circuit can be implemented using switch(es) and resistors, not necessarily using a digital rheostat or a rheostat.