IGBT/MOSFET fault protection

Abstract

A circuit for detecting faults affecting a power transistor comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The power transistor is turned on and off by assertion and de-assertion, respectively, of an input signal. The conditioning circuit produces a conditioned gate voltage signal from a gate voltage of the power transistor. The first fault status circuit asserts a first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval after the assertion of the input signal. The fault signaling circuit asserts a fault signal in response to the first fault indication being asserted, and de-asserting the fault signal in response to the input signal being de-asserted.

Claims

1. A circuit configured to detect faults, the circuit comprising: a conditioning circuit configured to produce a conditioned gate voltage signal according to a gate voltage of a power transistor by; voltage dividing a gate voltage signal indicating the gate voltage, and low-pass filtering a result of a buffering of the voltage-divided gate voltage signal; a first fault status circuit configured to produce a first fault indication by: performing a comparison of the conditioned gate voltage signal to a first fault reference voltage, and asserting the first fault indication in response to the comparison indicating that the conditioned gate voltage signal is greater than the first fault reference voltage during a first interval that begins at an assertion of an input signal, wherein the first fault reference voltage is set according to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor; and a fault signaling circuit configured to produce a fault signal by: determining a second interval having a pre-determined duration and starting at a de-assertion of the input signal, asserting the fault signal in response to the first fault indication being asserted outside the second interval, and resetting the fault signal during the second interval, wherein assertion of the input signal indicates that the power transistor is to be turned on, and de-assertion of the input signal indicates that the power transistor is to be turned off.

2. The circuit of claim 1, further comprising: a second fault status circuit configured to produce a second fault indication by asserting the second fault indication when the conditioned gate voltage signal is greater than a second fault reference voltage, the second fault reference voltage being greater than the first fault reference voltage, wherein the fault signaling circuit is further configured to produce the fault signal by asserting the fault signal in response to the second fault indication being asserted.

3. The circuit of claim 2, wherein the second fault reference voltage corresponds to a value of the conditioned gate voltage signal greater than the value of the conditioned gate voltage signal when the gate voltage of the power transistor is equal to a maximum gate voltage present on a gate of the power transistor during normal operation.

4. The circuit of claim 1, further comprising: a soft-off driver circuit configured to pull down the gate voltage to a clamp voltage when the fault signal is asserted, and to pull down the gate voltage to ground after a soft-off delay time has elapsed from the assertion of the fault signal.

5. The circuit of claim 1, wherein the first fault reference voltage is set to be greater than the value of the conditioned gate voltage signal corresponding to the Miller voltage of the power transistor, and wherein a duration of the first interval corresponds to a time after the assertion of the input signal when a Miller plateau occurs in the gate voltage of the power transistor under normal operation.

6. The circuit of claim 1, wherein the power transistor is an Insulated Gate Bipolar Transistor or a Metal Oxide Semiconductor Field Effect Transistor.

7. A circuit configured to detect faults, the circuit comprising: a gate voltage signal input configured to receive a gate voltage signal indicating a gate voltage of a power transistor; an input signal input configured to receive an input signal used to control the gate voltage of the power transistor; a conditioning circuit configured to produce a conditioned gate voltage signal according to the gate voltage signal by: voltage dividing the gate voltage signal, and low-pass filtering a buffering of the voltage-divided gate voltage signal; a first fault status circuit configured to produce a first fault indication according to the input signal and the conditioned gate voltage signal, the first fault indication indicating an over-current fault, a hard switching fault, or both, the first fault status circuit comprising: a comparator having a positive input coupled to the conditioned gate voltage signal and a negative input coupled to a first fault reference voltage, the first fault reference voltage being determined according to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor; and a fault signaling circuit configured to produce a fault signal by: generating a pulse having a duration equal to a second interval by asserting the pulse for the second interval in response to a de-assertion of the input signal, de-asserting the fault signal in response to the pulse being asserted, and asserting the fault signal in response to the first fault indication being asserted when the pulse is not asserted.

8. The circuit of claim 7, wherein the first fault status circuit further comprises: a delay circuit configured to de-assert an output disable signal for the duration of a first delay in response to an assertion of the input signal and to assert the output disable signal otherwise; an output circuit configured to assert the first fault indication when an output of the comparator is asserted and the output disable signal is de-asserted and to de-assert the first fault indication otherwise.

9. The circuit of claim 8, wherein the first fault reference voltage is set to have a value higher than the value of the conditioned gate voltage signal when the gate voltage is equal to the Miller voltage of the power transistor, and wherein the duration of the first delay corresponds to an interval between the assertion of the input signal and an expected time of occurrence of a Miller plateau during normal operation of the power transistor.

10. The circuit of claim 7, further comprising: a second fault status circuit configured to produce a second fault indication according to the conditioned gate voltage signal, the second fault indication indicating a fault under load, wherein the fault signaling circuit is further configured to produce the fault signal by asserting the fault signal in response to the second fault indication being asserted.

11. The circuit of claim 10, wherein the second fault status circuit comprises: a comparator having a positive input coupled to the conditioned gate voltage signal, a negative input coupled to a second fault reference voltage, and an output coupled to the second fault indication, wherein the second fault reference voltage corresponds to a voltage higher than a value of the conditioned gate voltage signal when the gate voltage is equal to a maximum gate voltage present on a gate of the power transistor during normal operation.

12. The circuit of claim 7, wherein the fault signaling circuit comprises: a pulse generator circuit having an input coupled to the input signal and an output, and configured to produce a pulse on the output in response to the de-assertion of the input signal; a set-reset flip-flop having a set input coupled to the first fault indication, a reset input coupled to the output of the pulse generator circuit, and an output coupled to the fault signal.

13. The circuit of claim 7, further comprising a soft off driver circuit, the soft off driver circuit comprising: a first transistor having a control input coupled to the fault signal, a first conduction terminal coupled to ground, and a second conduction terminal coupled to a first terminal of a Zener diode; the Zener diode having a second terminal coupled to the gate voltage signal; a delay circuit having an input coupled to the fault signal; and a second transistor having a control input coupled to an output of the delay circuit, a first conduction terminal coupled to ground, and a second conduction terminal coupled to the gate voltage signal.

14. A method of detecting faults, the method comprising: receiving an input signal used to control a gate voltage of a power transistor; receiving a gate voltage signal corresponding to the gate voltage; generating a conditioned gate voltage signal using the gate voltage signal by: voltage dividing the gate voltage signal, and low-pass filtering a buffering of the voltage-divided gate voltage signal; performing a first comparison of the conditioned gate voltage signal to a first fault reference voltage, the first fault reference voltage being set to a value corresponding to a value of the conditioned gate voltage signal corresponding to a Miller voltage of the power transistor; determining a first time period having a first predetermined duration and starting at an assertion of the input signal, determining a second time period having a second predetermined duration and starting at a de-assertion of the input signal, in response to the first comparison indicating that the conditioned gate voltage signal is greater than the first fault reference voltage: asserting a fault signal when the indication occurs during the first time period, and not asserting the fault signal when the indication occurs during the second time period; and de-asserting the fault signal during the second time period.

15. The method of claim 14, wherein the first fault reference voltage has a value greater than the value of the conditioned gate voltage signal corresponding to the gate voltage being equal to the Miller voltage of the power transistor, and wherein a duration of the first time period corresponds to an interval between an assertion of the input signal and an expected end of a Miller plateau during normal operation.

16. The method of claim 14, further comprising: performing a second comparison of the conditioned gate voltage signal to a second fault reference voltage; and in response to the second comparison indicating that the conditioned gate voltage signal is greater than the second fault reference voltage: asserting the fault signal when the indication of the second comparison occurs outside the second time period, and not asserting the fault signal when the indication of the second comparison occurs during the second time period.

17. The method of claim 16, wherein the second fault reference voltage is greater than a value of the conditioned gate voltage signal corresponding to the gate voltage being equal to a maximum gate voltage present on a gate of the power transistor during normal operation.

18. The method of claim 14, further comprising: in response to the assertion of the fault signal, performing gate voltage clamping of the power transistor, soft turn off of the power transistor, or both.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying figures like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, and are incorporated in and form part of the specification to further illustrate embodiments of concepts that include the claimed invention and explain various principles and advantages of those embodiments.

(2) FIG. 1 illustrates a driver circuit according to an embodiment controlling an Insulated Gate Bipolar Transistor (IGBT).

(3) FIG. 2 illustrates voltages and currents of an IGBT being switched on under normal operating conditions.

(4) FIG. 3 illustrates transfer characteristics of an IGBT or MOSFET.

(5) FIG. 4 illustrates a gate voltage status analyzing logic circuit according to an embodiment.

(6) FIG. 5 illustrates a gate voltage signal conditioning circuit according to an embodiment.

(7) FIG. 6 illustrates an over-current and hard switching fault status circuit according to an embodiment.

(8) FIG. 7 illustrates a gate voltage of an IGBT during turn-on when an over-current fault or a hard switching fault occurs.

(9) FIG. 8 illustrates a fault-under-load status circuit according to an embodiment.

(10) FIG. 9 illustrates a gate voltage of an IGBT when a fault-under-load occurs.

(11) FIG. 10 illustrates a fault status circuit according to an embodiment.

(12) FIG. 11 illustrates a gate voltage clamp and soft-off driver circuit for use in an embodiment.

(13) FIG. 12 illustrates operation of an embodiment when an over-current fault or hard switching fault occurs.

(14) FIG. 13 illustrates operation of an embodiment when a fault-under-load occurs.

DETAILED DESCRIPTION

(15) Embodiments relate to detecting fault conditions in circuits using IGBTs or power MOSFETs.

(16) In the following detailed description, certain illustrative embodiments have been illustrated and described. As those skilled in the art would realize, these embodiments may be modified in various different ways without departing from the scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements in the specification.

(17) In the following, some components are disclosed as being bipolar junction transistors (BJTs), but embodiments are not limited thereto. Accordingly, a BJT in the examples may be replaced with a transistor of some other suitable kind (such as a FET), with a control input (such as a gate), a first conduction terminal (such as a source or drain), and a second conduction terminal (such as the other of the source or drain) of that transistor corresponding to a base, a collector, and an emitter of the BJT, respectively.

(18) In an embodiment, a circuit is configured to detect faults. The circuit comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The conditioning circuit produces a conditioned gate voltage signal according to a gate voltage of a power transistor such as an IGBT or power MOSFET. The first fault status circuit produces a first fault indication by asserting the first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval that begins at an assertion of an input signal. The fault signaling circuit produces a fault signal by asserting the fault signal in response the first fault indication being asserted and by de-asserting the fault signal in response to the input signal being de-asserted. Assertion of the input signal indicates that the power transistor is to be turned on, and de-assertion of the input signal indicates that the power transistor is to be turned off.

(19) In an embodiment, a fault detection circuit included in a gate driver circuit detects fault conditions based on a gate voltage of a power IGBT or power MOSFET (hereinafter, a power transistor) controlled by the gate driver circuit, and an input signal that controls the turning on and off of the power transistor. The fault detection circuit may detect any or all of over-current faults, hard switching faults, faults under load, or combinations thereof. The fault detection circuit may use only the input signal and gate voltage (along with one or more internal reference voltages and one or more internal durations) to detect the faults. In particular, embodiments of the fault detection circuit do not need information regarding a gate current of the power transistor, a current through the power transistor, an input voltage to the power transistor, or an output voltage produced using the power transistor to detect the faults. Accordingly, a parts count of the circuit including the power transistor may be reduced and efficiency of that circuit may be improved by removing the need to monitor additional currents and/or voltages to provide fault protection. Furthermore, fault protection may be provided in situations where monitoring currents through the power transistor or output voltages produced using the power transistor is prohibitively difficult.

(20) FIG. 1 illustrates a driver circuit 100 according to an embodiment controlling an IGBT 110 that controls power to an inductive load. In another embodiment, the driver circuit 100 may control a power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).

(21) The driver circuit 100 includes a pre-driver circuit 102 and a fault handling circuit 104. The driver circuit 100 receives an input signal INP from an outside source, monitors and, in some situations, controls a gate voltage V.sub.GE (more precisely, a gate-to-emitter voltage) of a gate G of the IGBT 110, and generally controls the IGBT 110 using a gate on signal G.sub.on to source current to the gate G of the IGBT 110 and a gate off signal G.sub.off to sink current from the gate G of the IGBT 110.

(22) The pre-driver circuit 102 produces, using an input signal INP from an external source and a fault signal FLT produced by the fault handling circuit 104, the gate on signal G.sub.on and the gate off signal G.sub.off.

(23) In an embodiment, when the fault signal FLT is de-asserted (indicating that no fault has been detected), in response to the input signal INP indicating that the IGBT 110 is to be turned on, the pre-driver circuit 102 sources current to the gate on signal G.sub.on and floats the gate off signal G.sub.off; and in response to the input signal INP indicating that the IGBT 110 is to be turned off, the pre-driver circuit 102 floats the gate on signal G.sub.on and sinks current into the gate off signal G.sub.off. However, when the fault signal FLT is asserted (indicating that a fault has been detected) the pre-driver circuit 102 may float both the gate on signal G.sub.on and the gate off signal G.sub.off.

(24) The gate on signal G.sub.on is coupled to the gate G of the IGBT 110 by the on resistor 112. The on resister 112 controls a rate at which the IGBT 110 is turned on. The gate off signal G.sub.off is coupled to the gate G of the IGBT 110 by the off resistor 114. The off resister 114 controls a rate at which the IGBT 110 is turned off in non-fault situations.

(25) In another embodiment, the driver circuit 100 and the pre-driver circuit 102 may produce a single gate on/off signal that sinks and sources current as described above. In another embodiment, a single resistor may control both the rate of turn on and the normal rate of turn off of the IGBT 110. In another embodiment, a single gate on/off signal may be coupled to the gate G of the IGBT 110 using two diodes and two resistors configured so that one of the two resistors controls the rate of turn on and the other the normal rate of turn off of the IGBT 110.

(26) The fault handling circuit 104 detects faults using the input signal INP and the gate voltage V.sub.GE of the IGBT 110. In response to detecting a fault, the fault handling circuit 104 outputs a fault signal FLT to the pre-driver circuit 102 and controls the gate voltage V.sub.GE to safely turn off the IGBT 110. The fault handling circuit 104 includes a gate voltage status analyzing logic (GVSL) circuit 106 to produce the fault signal FLT using the input signal INP and the gate voltage V.sub.GE, and a soft-off driver circuit 108 that controls the gate voltage V.sub.GE to safely turn off the IGBT 110 in response to the fault signal FLT being asserted.

(27) The IGBT 110 has a collector C coupled to a first end of an inductor 120 and an emitter E coupled to ground. A second end of the inductor 120 is coupled to a DC power supply V.sub.DC. A cathode of a freewheeling diode 122 is coupled to the second end of the inductor 120, and an anode of the freewheeling diode 122 is coupled to the first end of the inductor 120. A protection diode 116 has a cathode connected to the collector C of the IGBT 110 and an anode connected to the emitter E of the IGBT 110.

(28) The inductor 120 may be an energy storage component of a power supply, a coil of an electromechanical device such as a motor or solenoid, or the like. The IGBT 110 controls a collector current I.sub.C through the inductor 110 by turning on and off.

(29) FIG. 2 illustrates voltages and currents of an IGBT being switched on under normal operating conditions while driving an inductive load, such as the inductor 120 shown in FIG. 1. Herein, “normal operation” refers to operation of the circuit when a fault (such as an over-current fault, hard switching fault, or fault-under-load) is not affecting the operation of the IGBT. The waveforms illustrated include a gate voltage V.sub.GE (more precisely, a gate-to-emitter voltage) of the IGBT, a collector current I.sub.C being conducted from the collector to the emitter of the IGBT when the IGBT is on, and a collector-emitter voltage V.sub.CE across the collector and the emitter of the IGBT.

(30) In a first time interval t0, the IGBT is off. The gate voltage V.sub.GE is initially zero but towards the end of the interval begins to rise until it reaches the gate threshold voltage V.sub.GE(th). During this interval the collector current I.sub.C and the collector-emitter voltage V.sub.CE do not change.

(31) In a second time interval t1, the gate voltage V.sub.GE exceeds the gate threshold voltage V.sub.GE(th), which allows the collector current I.sub.C to start flowing. In the second time interval t1, the IGBT may be in an active phase and the collector current I.sub.C may increase according to the gate voltage V.sub.GE. The collector current I.sub.C gradually increases to the full load current I.sub.L. The collector-emitter voltage V.sub.CE decreases in proportion to a stray inductance of the IGBT and the collector current's time derivative, δI.sub.C/δt.

(32) In a third time intervals t2, the collector-emitter voltage V.sub.CE continues to decrease in proportion to the stray inductance of the IGBT and the collector current's time derivative, δI.sub.C/δt. The collector current I.sub.C continues increasing according to the reverse recovery current of a free-wheeling diode, such as the freewheeling diode 122 of FIG. 1. The reverse recovery current of the free-wheeling diode starts flowing in the third time interval t2, increasing over the third time interval t2. Accordingly, the gate voltage V.sub.GE rises during the third time interval t2.

(33) The reverse recovery current of the free-wheeling diode starts decreasing during the fourth time interval t3. In this same fourth time interval t3, the voltage across the free-wheeling diode can increase, and the collector-emitter voltage V.sub.CE can drop. If the gate-collector collector capacitance C.sub.GC of the IGBT is low and the DC voltage V.sub.DC being provided to the inductive load is high enough, the collector-emitter voltage V.sub.CE can decrease sharply.

(34) During the fourth time interval t3, the gate-collector capacitance C.sub.GC of the IGBT and the gate-emitter capacitance C.sub.GE of the IGBT may discharge. The reverse recovery of the freewheeling diode terminates at the end of the fourth time interval t3.

(35) In a fifth time interval t4, the gate current I.sub.G being provided to the gate of the IGBT charges the gate-emitter capacitance C.sub.GE of the IGBT. The gate voltage V.sub.GE may substantially remain at the full load gate voltage V.sub.GE(I.sub.L), and the collector current I.sub.C may substantially remain at the full load current I.sub.L; because the gate voltage V.sub.GE stays at the same value during this period, this period may be called the Miller plateau. However, the collector-emitter voltage V.sub.CE may drop with a ratio of (V.sub.DD−V.sub.GE(I.sub.L))//(R.sub.GC.sub.GC), where R.sub.G is the resistance controlling the current being provided to the gate and V.sub.DD is a maximum gate voltage. In embodiments, the maximum gate voltage V.sub.DD is a maximum voltage that can be output by a pre-driver circuit coupled to the gate of the IGBT, such as the pre-driver circuit 102 of FIG. 1.

(36) In a sixth time interval t5, the gate voltage V.sub.GE can increase with a time constant Rg(C.sub.GE+C.sub.GC,miller), where C.sub.GC,miller is a Miller capacitance of the IGBT, until the gate voltage V.sub.GE reaches the maximum gate voltage V.sub.DD. In the sixth time interval t5, the collector-emitter voltage V.sub.CE gradually decreases until it reaches the saturation voltage V.sub.CE(SAT).

(37) FIG. 3 illustrates transfer characteristics of an IGBT or MOSFET. The figure illustrates the relationships between the transconductance g.sub.m of the IGBT or MOSFET, the gate voltage V.sub.GE of the IGBT or MOSFET, and the collector current I.sub.C of the IGBT or MOSFET.

(38) As shown in FIG. 3, the gate voltage V.sub.GE when the IGBT or MOSFET is turned on may be determined as the sum of the gate threshold voltage V.sub.GE(th) and the collector current I.sub.C divided by the transconductance g.sub.m. Accordingly, if the full load current I.sub.L is known, the gate voltage V.sub.GE during the fifth time interval t4 of FIG. 2, known hereinafter as the Miller voltage, may be determined by dividing the full load current I.sub.L by the transconductance g.sub.m and adding the gate threshold voltage V.sub.GE(th).

(39) FIG. 4 illustrates a gate voltage status analyzing logic (GVSL) circuit 406 according to an embodiment. The GVSL circuit 406 receives an input signal INP and a gate voltage V.sub.GE, and produces a fault signal FLT. The input signal INP may be asserted to indicate that the IGBT is to be turned on, and de-asserted to indicate that the IGBT is to be turned off. The fault signal FLT may be asserted to indicate that a fault has occurred, and de-asserted otherwise. The GVSL circuit 406 may be included in the GVSL circuit 106 of FIG. 1.

(40) The GVSL circuit 406 includes a signal conditioning circuit 412, an Over-Current/Hard Switching Fault (OC/HSF) status circuit 414, a Fault-under-Load (FUL) status circuit 416, and a fault status circuit 418. The fault status circuit 418 may be referred to as a fault signaling circuit.

(41) The signal conditioning circuit 412 receives the gate voltage V.sub.GE and produces a conditioned gate voltage V.sub.GE_SC. In embodiments, the signal conditioning circuit 412 may produce the conditioned gate voltage V.sub.GE_SC by limiting, reducing and/or shifting a voltage range of the gate voltage V.sub.GE and by filtering the gate voltage V.sub.GE to, for example, attenuate noise and transients on the gate voltage V.sub.GE.

(42) The OC/HSF status circuit 414 receives the input signal INP and the conditioned gate voltage V.sub.GE_SC and produces an OC/HSF fault signal F.sub.OCHSF. In embodiments, the OC/HSF status circuit 414 generates the OC/HSF fault signal F.sub.OCHSF according to a magnitude of the conditioned gate voltage V.sub.GE_SC during the Miller plateau.

(43) The FUL status circuit 416 receives the conditioned gate voltage V.sub.GE_SC and produces a FUL fault signal F.sub.FUL. In embodiments, the FUL status circuit 416 produces the FUL fault signal F.sub.FUL by comparing the conditioned gate voltage V.sub.GE_SC to a predetermined threshold voltage corresponding to the maximum gate voltage V.sub.DD.

(44) The fault status circuit 418 receives the input signal INP, the OC/HSF fault signal F.sub.OCHSF, and the FUL fault signal F.sub.FUL, and produces the fault signal FLT. In an embodiment, the fault status circuit 418 de-asserts the fault signal FLT in response to the input signal INP being de-asserted, and asserts the fault signal FLT in response to an assertion of either or both of the OC/HSF fault signal F.sub.OCHSF and the FUL fault signal F.sub.FUL being asserted.

(45) Notably, the GVSL circuit 406 detects the OC/HSF and FUL conditions without using information on the gate current flowing to the IGBT or power MOSFET being controlled, and without using information on the current flowing through the IGBT or power MOSFET (that is, without needing to measure the collector-emitter current of the IGBT or the drain-source current of the power MOSFET).

(46) FIG. 5 illustrates a signal conditioning circuit 512 according to an embodiment. The signal conditioning circuit 512 produces a conditioned gate voltage V.sub.GE_SC according to a gate voltage V.sub.GE, and includes a voltage divider formed by a first resistor 522 and a second resistor 524, an operational amplifier 526, and a low pass filter circuit 528. The signal conditioning circuit 512 may be included in the signal conditioning circuit 412 of FIG. 4.

(47) The gate voltage V.sub.GE is provided to the voltage divider, and the output of the voltage divider is provided to the positive input of the operational amplifier 526. Accordingly, the voltage at the positive input of the operational amplifier 526 is equal to V.sub.GE×R.sub.524/(R.sub.524+R.sub.522), where R.sub.522 is the resistance of the first resistor 522 and R.sub.524 is the resistance of the first resistor 524.

(48) The operational amplifier 526 is configured as a unity-gain amplifier, and accordingly an output of the operational amplifier 526 is equal to the signal at the positive input of the operational amplifier 526, that is, to V.sub.GE×R.sub.524/(R.sub.524+R.sub.522). However, embodiments are not limited thereto, and in embodiments, the operational amplifier 526 may be configured to provide gain less than one or greater than one.

(49) The low pass filter 528 produces the conditioned gate voltage V.sub.GE_SC by low-pass filtering the output of the operational amplifier 526. In an embodiment, a time constant of the low pass filter 528 is 40 nanoseconds.

(50) FIG. 6 illustrates an over-current and hard switching fault (OC/HSF) status circuit 614 according to an embodiment. The OC/HSF status circuit 614 produces an OC/HSF fault signal F.sub.OCHSF according to the input signal INP and the conditioned gate voltage V.sub.GE_SC. The OC/HSF status circuit 614 may be included in the OC/HSF status circuit 414 of FIG. 4.

(51) The OC/HSF status circuit 614 includes a voltage divider comprising a first resistor 622 and a second resistor 642, a comparator 626, a delay circuit 630, an AND gate 632, an Exclusive-NOR (XNOR) gate 634, a third resistor 638, and a transistor 638.

(52) The voltage divider including the first and second resistors 622 and 624 produces an OC/HSF reference voltage V.sub.ref_OC/HSF by dividing a supply voltage V.sub.DD. In an embodiment, the OC/HSF reference voltage V.sub.ref_OC/HSF corresponds to voltage higher than a value of the conditioned gate voltage V.sub.GE_SC that would be produced by the signal conditioning circuit 512 when the gate voltage V.sub.GE has a value equal to a Miller voltage of the IGBT or MOSFET.

(53) In an embodiment, the value of the OC/HSF reference voltage Vref_OC/HSF is a predetermined fraction of the supply voltage V.sub.DD. In another embodiment, one or more of the first and second resistors 622 and 624 may be external resistors chosen to set the value of the OC/HSF reference voltage Vref_OC/HSF. In another embodiment, one or more of the first and second resistors 622 and 624 may be a programmable variable resistor than can be programmed to set the OC/HSF reference voltage Vref_OC/HSF. Although FIG. 6 discloses generating the OC/HSF reference voltage V.sub.ref_OC/HSF using a resistive voltage divider, embodiments are not limited thereto.

(54) The comparator 626 compares the OC/HSF reference voltage V.sub.ref_OC/HSF to the conditioned gate voltage V.sub.GE_SC and attempts to assert the OC/HSF fault signal F.sub.OCHSF when the conditioned gate voltage V.sub.GE_SC greater than the OC/HSF reference voltage V.sub.ref_OC/HSF. However, the comparator 626 will be unable to assert the OC/HSF fault signal F.sub.OCHSF while the transistor 638 is turned on.

(55) The transistor 638 is controlled by the delay circuit 630, the AND gate 632, and the XNOR gate 634, which operate to turn the transistor 638 off (allowing the OC/HSF fault signal F.sub.OCHSF to be asserted) for the period corresponding to the delay time t of the delay circuit 630 immediately after the input signal INP is asserted, and to turn the transistor 638 back on after the delay time of the delay circuit 630 has elapsed after the input signal INP was asserted. In an embodiment, the delay time t of the delay circuit 630 is a time Δ.sub.M corresponding to the expected delay between the assertion of the input signal INP and the end of the Miller plateau, such as shown in the fifth interval t4 of FIG. 2.

(56) The delay time of the delay circuit 630 may be selected so that the transistor 638 is turned off before and during the Miller plateau (the fifth time t4 of FIG. 2), and is turned back on after the end of the Miller plateau, so that the OC/HSF fault signal F.sub.OCHSF can only be asserted when the conditioned gate voltage V.sub.GE_SC rises above the OC/HSF reference voltage V.sub.ref_OC/HSF before or during the Miller plateau. In an embodiment, the OC/HSF reference voltage V.sub.ref_OC/HSF is set higher than an expected value of the conditioned gate voltage V.sub.GE_SC at the peak in the gate voltage V.sub.GE shown in FIG. 2 between t2 and t3. In another embodiment, the low pass filter 528 eliminates or substantially attenuates the effect of the peak in the gate voltage V.sub.GE shown in FIG. 2 between t2 and t3 on the conditioned gate voltage V.sub.GE_SC.

(57) FIG. 7 illustrates a gate voltage of an IGBT (or MOSFET) during turn-on when an over-current fault or a hard-switching fault occurs, and will be used to explain operation of an OC/HSF status circuit according to an embodiment, such as the OC/HSF status circuit 614 of FIG. 6. In FIG. 7, the slight bump in the gate voltage V.sub.GE that may occur before the Miller plateau (as shown in FIG. 2) has been omitted to focus attention on the behavior of the gate voltage V.sub.GE during the interval t3,t4 that normally corresponds to the Miller plateau.

(58) As shown in FIG. 7, when a circuit such as that shown in FIG. 1 is operating normally, the gate voltage V.sub.GE during the interval t3,t4 will be the Miller voltage V.sub.GE(I.sub.L), as previously discussed. Accordingly, if the OC/HSF reference voltage V.sub.ref_OC/HSF of FIG. 6 is configured to be higher than the value of conditioned gate voltage V.sub.GE_SC when the gate voltage V.sub.GE is equal to the Miller voltage V.sub.GE(I.sub.L), the comparator 626 will not assert the OC/HSF fault signal F.sub.OCHSF during the interval t3,t4 when the circuit is operating normally. Accordingly, if the delay value of the delay circuit 630 is configured to prevent assertion of the OC/HSF fault signal F.sub.OCHSF after the interval t3,t4, the OC/HSF fault signal F.sub.OCHSF will not be asserted during normal operation.

(59) However, when the circuit such as that shown in FIG. 1 experiences an over-current condition or a hard switching fault condition, the gate voltage V.sub.GE may rise to be substantially above the Miller voltage V.sub.GE(I.sub.L) during the interval t3,t4. Accordingly, if the OC/HSF reference voltage V.sub.ref_OC/HSF is configured to be higher than the value of conditioned gate voltage V.sub.GE_SC when the gate voltage V.sub.GE is equal to the Miller voltage V.sub.GE(I.sub.L) but lower than the value of conditioned gate voltage V.sub.GE_SC when the over-current condition or hard switching fault condition occur, the OC/HSF fault signal F.sub.OCHSF will be asserted during the interval t3,t4 in response to the over-current or hard switching fault.

(60) FIG. 8 illustrates a fault-under-load (FUL) status circuit 816 according to an embodiment. The FUL status circuit 816 produces a FUL fault signal F.sub.FUL using a conditioned gate voltage V.sub.GE_SC, and includes a comparator 846 and voltage divider comprising a first resistor 842 and a second resistor 844. The FUL status circuit 816 may be included in the FUL status circuit 416 of FIG. 4.

(61) The voltage divider comprising first and second resistors 842 and 844 operates to produce a FUL reference voltage V.sub.ref_FUL by dividing a supply voltage V.sub.DD. In an embodiment, the FUL reference voltage V.sub.ref_FUL corresponds to voltage higher than a value of the conditioned gate voltage V.sub.GE_SC that would be produced by the signal conditioning circuit 512 when the gate voltage V.sub.GE is equal to a maximum voltage V.sub.DD that a pre-driver can provide to a gate of an IGBT or MOSFET.

(62) In an embodiment, the value of the FUL reference voltage V9.sub.ref_FUL is a predetermined fraction of the supply voltage VDD. In another embodiment, one or more of the first and second resistors 842 and 844 may be external resistors chosen to set the value of the FUL reference voltage V.sub.ref_FUL. In another embodiment, one or more of the first and second resistors 842 and 844 may be a programmable variable resistor than can be programmed to set the FUL reference voltage V.sub.ref_FUL. And although FIG. 8 discloses generating the FUL reference voltage V.sub.ref_FUL using a resistive voltage divider, embodiments are not limited thereto.

(63) FIG. 9 illustrates a gate voltage of an IGBT (or MOSFET) when a fault-under-load (FUL) occurs, and will be used to explain operation of a FUL status circuit according to an embodiment, such as the FUL status circuit 816 of FIG. 8.

(64) In intervals t0, t1, t2, t3, t4, t5, the IGBT operates normally as described for the corresponding intervals t0 to t5 of FIG. 2.

(65) In interval t.sub.FUL, a fault-under load (FUL) occurs. The FUL corresponds to a short-circuit that occurred after the IGBT was turned on. As a result, the collector current I.sub.C may increase sharply and the IGBT may leave a saturated mode and enter an active mode. Accordingly, the collector-emitter voltage V.sub.CE of the IGBT may increase and collector current I.sub.C may flow into the Miller capacitance C.sub.GC,miller of the IGBT. This may cause the gate voltage V.sub.GE to rise, and in particular may cause the gate voltage V.sub.GE to rise above the maximum voltage (here, supply voltage V.sub.DD) that a pre-driver is able to provide to the gate of the IGBT, as shown by the dashed line in interval t.sub.FUL (where the solid line shows what the gate voltage V.sub.GE would be in the absence of the FUL).

(66) Referring to FIG. 8, when the gate voltage V.sub.GE rises above supply voltage VDD during the FUL interval t.sub.FUL, the conditioned gate voltage V.sub.GE_SC rises above the FUL reference voltage V.sub.ref_FUL, and as a result the comparator 846 asserts the FUL fault signal F.sub.FUL to indicate that the FUL is occurring.

(67) FIG. 10 illustrates a fault status circuit 1018 according to an embodiment. The fault status circuit 1018 produces the fault signal FLT according to the OC/HSF fault signal F.sub.OCHSF, the FUL fault signal F.sub.FUL, and the input signal INP. The fault status circuit 1018 may be included in the fault status circuit 418 of FIG. 4.

(68) The fault status circuit 1018 includes a delay circuit 1050, a first OR gate 1052, an Exclusive-OR (XOR) gate 1054, a second OR gate 1056, and a Set-Reset Flip-Flop (SRFF) 1058.

(69) The delay circuit 1050, first OR gate 1052, and XOR gate 1054 operate as a negative-edge triggered pulse generator that produce a pulse on an output of the XOR gate 1054 in response to the input signal INP being de-asserted. The pulse on the output of the XOR gate is provided to a reset input R of the SRFF 1058 and has a duration equal to the delay of the delay circuit 1050. In an embodiment, the duration of the pulse corresponds to a minimum pulse width that will be recognized by the reset input R of the SRFF 1058.

(70) The second OR gate 1056 receives the OC/HSF fault signal F.sub.OCHSF and the FUL fault signal F.sub.FUL and produces an output that is asserted (i.e., has a logical 1 value) when one or both of the OC/HSF fault signal F.sub.OCHSF and the FUL fault signal F.sub.FUL are asserted, and is de-asserted (i.e., has a logical 1 value) otherwise. The output of the second OR gate 1056 is provided to a set input S of the SRFF 1058.

(71) The fault signal FLT is generated at an output Q of the SRFF 1058 by de-asserting the fault signal FLT in response to the input signal INP being de-asserted, and asserting the fault signal FLT when one or both of the OC/HSF fault signal F.sub.OCHSF and the FUL fault signal F.sub.FUL are asserted.

(72) FIG. 11 illustrates a soft-off driver circuit 1108 for use in an embodiment. The soft-off driver circuit 1108 controls a gate voltage V.sub.GE in response to a fault signal FLT being asserted. The soft-off driver circuit 1108 may be included in the soft-off driver circuit 108 of FIG. 1.

(73) The soft-off driver circuit 1108 includes a gate voltage clamp circuit 1162, a delay circuit 1164, and a soft turn-off circuit 1166.

(74) The gate voltage clamp circuit 1162 operates to pull the gate voltage V.sub.GE down to a reverse breakdown voltage of a Zener diode ZD at a predetermined rate when the fault signal FLT is asserted, and does not affect the gate voltage V.sub.GE when the fault signal FLT is de-asserted.

(75) The delay circuit 1164 produces a delayed fault signal FLT_D by delaying the fault signal FLT by a predetermined soft off delay time ΔSO. In an illustrative embodiment, the soft off delay time ΔSO may be 1.2 μs.

(76) The soft turn-off circuit 1166 operates to pull the gate voltage V.sub.GE down to ground at a predetermined rate when the delayed fault signal FLT_D is asserted, and does not affect the gate voltage V.sub.GE when the delayed fault signal FLT_D is not asserted.

(77) FIG. 12 illustrates operation of an embodiment when an over-current fault or hard switching fault occurs. FIG. 12 shows waveforms for the input signal INP which is a logic value (asserted when high and de-asserted when low), the conditioned gate voltage V.sub.GE_SC in volts, the set input S and reset input R of the SRFF 1058 of FIG. 10 which are logic values, and the fault signal FLT which is a logic value.

(78) In a first interval t0, the input signal INP is de-asserted and as a result the gate voltage V.sub.GE is low (here, 0V), turning the IGBT (or MOSFET) off. Because the gate voltage V.sub.GE is 0V, the conditioned gate voltage V.sub.GE_SC is also 0V.

(79) At the beginning of a second interval t.sub.1, the input signal INP is asserted, and as a result the gate voltage V.sub.GE and the conditioned gate voltage V.sub.GE_SC begin to rise. The conditioned gate voltage V.sub.GE_SC continues to rise through the third interval t2, eventually rising above the full load conditioned gate voltage V.sub.GE_SC(I.sub.L), which is the value of the conditioned gate voltage V.sub.GE_SC when the gate voltage V.sub.GE is at the full load gate voltage V.sub.GE(I.sub.L).

(80) During the fourth interval t3, when the gate voltage V.sub.GE would normally fall to the full load gate voltage V.sub.GE(I.sub.L) as shown in FIG. 2, the gate voltage V.sub.GE remains higher than the full load gate voltage V.sub.GE(I.sub.L) and as a result the conditioned gate voltage V.sub.GE_SC remains higher than the full load conditioned gate voltage V9.sub.GE_SC(I.sub.L).

(81) During the fifth interval t4, when the gate voltage V.sub.GE would normally enter the Miller plateau at a voltage equal to the full load gate voltage V.sub.GE(I.sub.L), the gate voltage V.sub.GE remains higher than the full load gate voltage V.sub.GE(I.sub.L) and as a result the conditioned gate voltage V.sub.GE_SC remains higher than the full load conditioned gate voltage V.sub.GE_SC(I.sub.L).

(82) For a delay of a time Δ.sub.M corresponding to the expected delay between the assertion of the input signal INP and the end of the Miller plateau, the embodiment enables detection of the over-current fault or hard switching fault. For example, in the embodiment shown as the OC/HSF status circuit 614 in FIG. 6, detection of over-current faults or hard switching faults is enabled by turning off the transistor 638 during the delay of a time Δ.sub.M after assertion of the input signal INP, allowing the output of comparator 626 to rise when the conditioned gate voltage V.sub.GE_SC is greater than the OC/HSF reference voltage V.sub.ref_OC/HSF. As shown in FIG. 12, the OC/HSF reference voltage V.sub.ref_OC/HSF is configured to be higher than the full load conditioned gate voltage V.sub.GE_SC(I.sub.L).

(83) Because the conditioned gate voltage V.sub.GE_SC is greater than the OC/HSF reference voltage V.sub.ref_OC/HSF while the transistor 638 is turned off, the OC/HSF fault signal F.sub.OCHSF is asserted, causing the set input S of the SRFF 1058 of FIG. 10 to be asserted. This causes the fault signal FLT to be asserted during the fifth interval t4.

(84) In response to the assertion of the fault signal FLT, in a sixth interval t5 the pre-driver circuit 102 of FIG. 1 stops driving the gate on signal G.sub.ON, and the gate voltage clamp circuit 1162 activates. The gate voltage clamp circuit 1162 discharges the gate capacitance of the IGBT (or MOSFET) until the gate voltage V.sub.GE reaches a predetermined clamp voltage (here, the breakdown voltage of the Zener diode ZD in the gate voltage clamp circuit 1162.) As shown in FIG. 12, the conditioned gate voltage V.sub.GE_SC declines as a result of the gate voltage V.sub.GE declining.

(85) In a seventh interval t6 beginning a soft-off delay time after the assertion of the fault signal FLT, a soft turn-off circuit 1166 activates and discharges the gate capacitance of the IGBT (or MOSFET) until the gate voltage V.sub.GE reaches 0V, with the conditioned gate voltage V.sub.GE_SC declining accordingly. When the gate voltage V.sub.GE reaches 0V, the IGBT (or MOSFET) is turned off.

(86) The IGBT (or MOSFET) remains turned off until the end of the eighth interval t7, which ends when the input signal INP is de-asserted. In response to the input signal INP being de-asserted, the OC/HSF fault signal F.sub.OCHSF and the fault signal FLT are de-asserted. The fault signal FLT being de-asserted causes the gate voltage clamp circuit 1162 and the soft turn-off circuit 1166 to be turned off, and enables the pre-driver circuit 102 of FIG. 1 to drive the gate on signal G.sub.ON the next time the input signal INP is asserted.

(87) In this manner, the embodiment protects against over-current and hard switching faults by detecting that the gate voltage V.sub.GE is too high during the time that normally corresponds to the Miller plateau, and safely turning off the IGBT (or MOSFET) in response.

(88) FIG. 13 illustrates operation of an embodiment when a fault-under-load occurs. FIG. 13 shows waveforms for the input signal INP which is a logic value, the conditioned gate voltage V.sub.GE_SC in volts, the set input S and reset input R of the SRFF 1058 of FIG. 10 which are logic values, and the fault signal FLT which is a logic value.

(89) Operation of the embodiment is normal, as described FIG. 2, for the first to sixth intervals t0 to t5.

(90) In the seventh interval t6, a fault-under-load occurs. As a result, the gate voltage V.sub.GE rises above the (normal) maximum gate voltage V.sub.DD shown in FIG. 2, and therefore the conditioned gate voltage V.sub.GE_SC rises above the FUL reference voltage V.sub.ref_FUL.

(91) In response to the conditioned gate voltage V.sub.GE_SC rising above the FUL reference voltage V.sub.ref_FUL, the FUL fault signal F.sub.FUL is asserted by the full status circuit 816, which causes the set input S of the SRFF 1058 of FIG. 10 to be asserted. This causes the fault signal FLT to be asserted during the fifth interval seventh interval t6.

(92) In response to the assertion of the fault signal FLT, in the seventh interval t6 the pre-driver circuit 102 of FIG. 1 stops driving the gate on signal G.sub.ON, and the gate voltage clamp circuit 1162 activates. In an eighth interval t7, the gate voltage clamp circuit 1162 discharges the gate capacitance of the IGBT (or MOSFET) until the gate voltage V.sub.GE reaches a predetermined clamp voltage (here, the breakdown voltage of the Zener diode ZD in the gate voltage clamp circuit 1162.) As shown in FIG. 13, the conditioned gate voltage V.sub.GE_SC declines as the gate voltage V.sub.GE does.

(93) In a ninth interval t8 beginning a soft-off delay time after the assertion of the fault signal FLT, a soft turn-off circuit 1166 activates and discharges the gate capacitance of the IGBT (or MOSFET) until the gate voltage V.sub.GE reaches 0V, with the conditioned gate voltage V.sub.GE_SC declining accordingly. When the gate voltage V.sub.GE reaches 0V, the IGBT (or MOSFET) is turned off.

(94) The IGBT (or MOSFET) remains turned off until the end of the tenth interval t9, which ends when the input signal INP is de-asserted. In response to the input signal INP being de-asserted, the OC/HSF fault signal F.sub.OCHSF and the fault signal FLT are de-asserted. The fault signal FLT being de-asserted causes the gate voltage clamp circuit 1162 and the soft turn-off circuit 1166 to be turned off, and enables the pre-driver circuit 102 of FIG. 1 to drive the gate on signal G.sub.ON the next time the input signal INP is asserted.

(95) In this manner, the embodiment protects against Fault-under-Load faults by detecting that the gate voltage V.sub.GE is higher than the maximum normal gate voltage and safely turning off the IGBT (or MOSFET) in response.

(96) Embodiments of the present disclosure include electronic devices, e.g., one or more packaged semiconductor devices, configured to perform one or more of the operations described herein. However, embodiments are not limited thereto.

(97) While this invention has been described in connection with what is presently considered to be practical embodiments, embodiments are not limited to the disclosed embodiments, but, on the contrary, may include various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The order of operations described in a process is illustrative and some operations may be re-ordered. Further, two or more embodiments may be combined.