Digital time processing over time sensitive networks

Abstract

The Digital Time Processing over Time Sensitive Networks (DTP TSN) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks recovered from PTP messages and/or compatible with them data receiver clocks for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages, wherein such distribution of the master time includes filtering out phase noise of a timing referencing signals communicated by PTP messages in order to produce accurate timing implementing signals such as the slave clock, local slave time and local master time.

Claims

1. A method for Digital Time Processing over Time Sensitive Networks (DTP TSN) using messages of a Precision Time Protocol for distributing a master time secured by a master unit to a slave unit, wherein a timing implementing frame constructed with a slave clock is produced as synchronous to a timing referencing frame, signaled by messages sent by the master unit, by filtering out phase distortions from the timing referencing frame and the slave clock is maintaining a local slave time which is increased by a transmission delay in order to produce a local master time tracking the master time wherein the timing implementing frame and the slave clock are produced using a free running local clock or subclocks of the local clock; wherein the DTP TSN method comprises the steps of: using time stamps of arrivals of sync messages captured by the slave unit for defining detected lengths of intervals of the timing referencing frame; wherein the arrivals are captured and the lengths of the intervals of the timing referencing frame are detected with a time to digital converter (TDC) using the local clock or subclocks of the local clock for implementing a hardware time stamping maintaining a known delay between the arrivals and actual said hardware time stamping; using, by the slave unit, time stamps captured with a master clock or subclocks of the master clock by the master unit and communicated with the sync messages or other messages, for defining expected lengths of intervals of the timing referencing frame; using the detected lengths and the expected lengths for estimating phase errors between the timing referencing frame and the timing implementing frame, based on known relations maintained between the local clock and the slave clock and between the slave clock and the timing implementing frame; processing the estimated phase errors in order to filter out phase noise carried by the referencing frame and to define the timing implementing frame and the slave clock which are synchronous to the timing referencing frame timed by the arrivals of the sync messages to the slave unit but are delayed by the transmission delay in relation to departures of the sync messages from the master unit; wherein the defined timing implementing frame and the slave clock are produced by using a digital to time converter (DTC) driven by the local clock or subclocks of the local clock; using, by the slave unit, messages received from the master unit and the slave clock or subclocks of the slave clock, for producing a local slave time and estimating the transmission delay; producing a local master time by adding the estimated transmission delay to the local slave time.

2. A DTP TSN method as claimed in claim 1, wherein: the timing implementing frame and the slave clock are initialized by starting a first such interval of the timing implementing frame when such arrival of a first such sync message is detected and such time stamp of the arrival of the first sync message is captured.

3. A DTP TSN method as claimed in claim 1, wherein: the local slave time, lagging by the transmission delay behind the master time, is preset at starting of a first such interval of the timing implementing frame, as equal to such time stamp captured by the master unit and communicated by a first such sync message; the local slave time is being continuously updated by the slave clock in order to maintain the transmission delay versus the master time.

4. A DTP TSN method as claimed in claim 1, wherein: consecutive values of the transmission delay are calculated repeatedly using consecutive said sync messages and other messages.

5. A DTP TSN method as claimed in claim 4, wherein: the calculated values of the transmission delay are filtered in order to reduce phase distortions introduced by a transmission channel and messages capturing circuits; the filtered values of the transmission delay are used as the estimated transmission delay added to the local slave time in order to produce the local master time.

6. A method for Digital Time Processing over Time Sensitive Networks (DTP TSN) using messages of a Precision Time Protocol for distributing a master time secured by a master unit to a slave unit, wherein a timing implementing frame, constructed with a slave clock, is produced as synchronous to a timing referencing frame, signaled by messages sent by the master unit, after filtering out phase distortions carried by the timing referencing frame, and the slave clock is maintaining a local slave time which is increased by a transmission delay in order to produce a local master time tracking the master time; wherein the DTP TSN method comprises the steps of: using time stamps of arrivals of sync messages captured by the slave unit for detecting lengths of intervals of the timing referencing frame; wherein the arrivals are captured with a hardware time stamping using a local clock or subclocks of the local clock; using, by the slave unit, time stamps captured with a master clock or subclocks of the master clock by the master unit and communicated with the sync messages or other messages, for defining expected lengths of intervals of the timing referencing frame; using the detected lengths and the expected lengths for estimating phase errors between the timing referencing frame and the timing implementing frame, based on known relations maintained between the local clock and the slave clock and between the slave clock and the timing implementing frame; processing the estimated phase errors in order to filter out phase noise carried by the referencing frame and to define the timing implementing frame and the slave clock which are synchronous to the timing referencing frame timed by the arrivals of the sync messages to the slave unit; using, by the slave unit, messages received from the master unit and the slave clock or subclocks of the slave clock, for producing a local slave time and estimating the transmission delay; producing the local master time by adding the estimated transmission delay to the local slave time.

7. A DTP TSN method as claimed in claim 6, wherein: the timing implementing frame and the slave clock are initialized by starting a first such interval of the timing implementing frame when such arrival of a first such sync message is detected and such time stamp of the arrival of the first sync message is captured.

8. A DTP TSN method as claimed in claim 6, wherein: the local slave time, lagging by the transmission delay behind the master time, is preset at starting of a first such interval of the timing implementing frame, as equal to such time stamp captured by the master unit and communicated by a first such sync message; the local slave time is being continuously updated by the slave clock in order to maintain the transmission delay versus the master time.

9. A DTP TSN method as claimed in claim 6, wherein: consecutive values of the transmission delay are calculated repeatedly using consecutive said sync messages and other messages.

10. A DTP TSN method as claimed in claim 9, wherein: the calculated values of the transmission delay are filtered in order to reduce phase distortions introduced by a transmission channel and messages capturing circuits; the filtered values of the transmission delay are used as the estimated transmission delay added to the local slave time in order to produce the local master time.

11. A method for Digital Time Processing over Time Sensitive Networks (DTP TSN) using messages of a Precision Time Protocol for distributing a master time secured by a master unit to a slave unit, wherein: a timing referencing frame is detected as delimited by time stamps of sync messages captured by the slave unit; an expected timing referencing frame is defined by time stamps captured by the master unit and communicated to the slave unit with the sync messages; phase errors defined by differences between such expected and such detected timing referencing frames are processed to produce a timing implementing frame and a slave clock synchronous to the timing referencing frame communicated by the master unit with the sync messages; using, by the slave unit, the slave clock for producing a local slave time and the messages of the Precision Time Protocol for estimating a transmission delay; producing a local master time by adding the estimated transmission delay to the local slave time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A, FIG. 1B and FIG. 1C are showing block diagrams of different implementations of the Digital Time Processing.

(2) FIG. 2A shows Frequency Response of the FIR Filter designed using Frequency Sampling Method.

(3) FIG. 2B shows Rational Number Filter implementing this FIR Filter.

(4) FIG. 2C shows Frequency Response of the IIR Filter of 1.sup.st order.

(5) FIG. 2D shows Rational Number Filter approximating this IIR Filter.

(6) FIG. 2E shows Impulse Response of the RNF approximating this IIR.

(7) FIG. 3A shows block diagram of Time to Digital Converter (TDC).

(8) FIG. 3B shows Detector of Fractional Phase (DFP).

(9) FIG. 4 shows Block Diagram of Digital to Time Converter (DTC).

(10) FIG. 4A shows Sequential Clocks Generator (SCG) and Output Selection Circuit (OSC), wherein the SCG generates the subclocks and the phase 1/phase 2 subclocks of LOC_Clk and the OSC selects a specific such phase 1/phase 2 subclock for implementing digital to time conversion defined by the real time sequential processor (RTSP).

(11) FIG. 4B shows Clocks Equalization Circuit (CEC) exemplifying system of buffers securing subclocks compliance with timing needed to implement TDC, DTC and the time processing system (TPS).

(12) FIG. 5A shows Detector of Initial Frame Phase (DIFP).

(13) FIG. 5B shows Timing Starting Circuit (TSC) generating timing signals which control initial preloading of the sequential stages of the RTSP.

(14) FIG. 5C shows Timing Control Circuit controlling operations of the RTSP.

(15) FIG. 6 shows Real Time Sequential Processor (RTSP)

(16) FIG. 7A shows Timing Diagram of the Sequential Clocks Generator (SCG).

(17) FIG. 7B shows Timing Diagram of DTC Operations.

(18) FIG. 8 shows Generation of Sampling Clock, Local Carrier Clock and Baseband Recovery.

(19) FIG. 9 shows PTP Time Distribution providing a base for phase noise and time delay filtering.

DETAILED DESCRIPTION

(20) Principles of operations of the time processing systems defined above are illustrated below as including utilization of FIR and IIR filters for the phase noise reduction.

(21) The time processing systems utilizing such FIR and IIR filters are shown further below as related to an exemplary OFDM system (corresponding to IEEE 802.16e-2005 Wireless MAN OFDMA) characterized below.

(22) A baseband of a demodulated OFDM signal has BW=20 MHz, a sub-carriers spacing ΔFsc=10.94 kHz, a number of FFT points N=2048, a cyclic prefix (CP) contains Ncp=256 of sampling periods Ts, the referencing frame (OFDM symbol) contains Nref=2304 Ts, sampling frequency Fs=˜22.4 MHz, the sampling period Ts=˜45 ns.

(23) Time periods between consecutive subclocks Tsc, are defining phase measurement & phase synthesis steps determining TDC & DTC resolutions.

(24) Such Tsc may be reduced to <5 pS, by using an advanced VLSI process (such as TSMCs 5 nm FinFET) and multi-path ring oscillator implementation (such as that described in the article “A Multi-Path Ring Oscillator TDC With First Order Noise Shaping” by Matthew Z. Straayer and Michael H. Perrot published in IEEE Journal of Solid State Circuits, Vol. 44, No 4, April 2009).

(25) Functioning of OFDM systems may be affected by:

(26) OFDM signal phase drift or low frequency changes caused by factors such as changing geographic environment affecting signal fading or a frequency drift of the local clock;

(27) higher frequency phase noise introduced to the referencing signal by factors such as inaccurate detection of OFDM symbol boundaries defining the referencing frame and/or interference of a noisy RF environment.

(28) While such phase drift and low frequency changes shall be followed by the synchronous frame and the synchronous clock, such higher frequency phase noise shall be reduced by filtering it out before the synchronous frame and clock are produced.

(29) 1. Phase Tracking System

(30) The phase tracking system is presented in FIG. 1B.

(31) TDC utilizes the local clock or subclocks for measuring lengths of periods of the referencing frame.

(32) TDC signals ends of the referencing frame periods (and availability of the measured lengths of the periods) to PCU.

(33) PCU reads the measured lengths and derives lengths of following periods of the synchronous frame and the synchronous clock.

(34) wherein the derivation of the lengths includes filtering out the phase noise contributed by the referencing frame.

(35) Availability of a first such derived length of the synchronous frame and lengths of its clocks is signaled by PCU to DTC immediately after processing said measured length of an initial said referencing frame period.

(36) However, the DTC starts using the first derived lengths of the synchronous frame and its clocks for producing a first period of the synchronous frame and periods of its clocks, only after detecting an end of a referencing frame period next to the initial referencing frame period.

(37) After such initialization of DTC, PCU makes next the derived lengths available for reading by the DTC immediately after processing previous such measured lengths, but DTC reads and utilizes the next derived lengths for producing next the synchronous frame periods only after producing previous the synchronous frame periods.

(38) An end phase of a first the synchronous frame period may be made equal to a penultimate such measured length of such referencing frame period or a more complex estimate such as an weighted average of plurality of the lengths of the referencing frame periods measured by TDC before the first synchronous frame period is produced.

(39) All the following consecutive the measured lengths are filtered and utilized for deriving lengths of the synchronous frame periods constructing the synchronous frame which is tracking phase of the referencing frame without any accumulation of quantization errors.

(40) Such TDC, PCU and DTC interactions shall satisfy timing relations explained below.

(41) As differences between consecutive the measured lengths may be significant (e.g. ¼ of the measured lengths for OFDM),

(42) securing the availability of the measured lengths for the deriving the lengths of following synchronous frame periods may require a time amounting to a significant fraction of the synchronous frame periods next to the measured referencing frame periods.

(43) The deriving the lengths, performed by the PCU, shall also require a time amounting to a fraction of the lengths of the next synchronous frame periods.

(44) Therefore the producing the synchronous frame periods consisting of the synchronous clock periods, can be started only after a time delay sufficient to:

(45) accommodate safely both the time required for the securing the availability of the measured lengths and the time required for the deriving the lengths of the next synchronous frame periods,

(46) before DTC can read and utilize the derived lengths for producing the next synchronous frame periods after the producing the previous synchronous frame periods.

(47) In order to assure such safe accommodation of both time delays it is assumed herein that:

(48) every the measured lengths with the exception of following x(0) the second measured phase x(1), is used by PCU for the deriving the length of the synchronous frame period which begins after the synchronous frame period next to the measured one,

(49) the synchronous frame period y(2) is started at the end of the referencing frame period x(1) and its length is made equal to that of x(0).

(50) The filtering out of the phase noise of the referencing frame is performed by PCU by utilizing FIR or IIR filters detailed further on.

(51) It shall be noted that mentioned in SUMMARY OF THE INVENTION utilization of FIR and IIR filters for the phase noise reduction in such phase tracking systems, is covering applications of a wide variety of filters which are exemplified by but not limited to applications of FIR and IIR filters described below.

(52) 2. Implementations of RNF, OLS and CLS.

(53) 2.1 Rational Number Filter with Finite Impulse Response (RNF FIR).

(54) The synchronous frame periods y(2), y(3), y(4), . . . y(n−1), y(n) are tracking the referencing frame periods x(0), x(1), x(2), . . . x(n−3), x(n−2).

(55) Such phase tracking may include phase noise reduction implemented by passing time intervals containing pluralities the measured lengths x(0), x(1), x(2), . . . x(n−3), x(n−2) through a low pass filter.

(56) However the measured lengths can be treated as comprising:

(57) a bigger constant component expected to be closer to non-distorted original phases of the referencing frame tracked actually;

(58) significantly smaller variable components closer to a phase noise which is caused by transmission channel distortions and shall be filtered out.

(59) In order to improve filtering efficiency only the variable components, defined by differences between consecutive the measured lengths and the expected constant component, are passed through the low pass filter.

(60) Using such differences instead of entire the measured lengths reduces amount of processing needed to filter the phase noise out.

(61) The expected constant component may be estimated as equal to a first such measured length x(0) or an average of the lengths measured initially.

(62) It is assumed below that:

(63) the expected constant component is equal to x(0);

(64) the measured lengths differences are defined as equal to
Δx(1)=x(1)−x(0), Δx(2)=x(2)−x(0), . . . Δx(n−2)=x(n−2)−x(0);

(65) the phase tracking is initialized at the end of x(1) by starting the original period produced by DTC as y(2)=x(0).

(66) Consequently outputs of the low pass filter are supplying differences between entire derived lengths and the original derived length which are amounting to:
Δy(3)=y(3)−y(2), Δy(4)=y(4)−y(2), . . . Δy(n)=y(n)−y(2).

(67) Resulting phase tracking operation is based on using the measured lengths differences for deriving supplements of the original derived length y(2) needed to calculate the entire derived lengths of the synchronous frame periods y(n).

(68) Such supplementation of the original length y(2) is accomplished by adding to it a noise filtering products of the measured lengths differences Δx(2), Δx(3), . . . Δx(n−2),

(69) wherein filter DC gain G(ω=0) has to be equal to 1 in order to enable accurate phase tracking without uncontrolled phase transients.

(70) When a FIR filter is defined with coefficients h(0), h(1), . . . h(k), the synchronous frame periods tracking phase of the referencing frame are derived as:

(71) y(2)=x(0). wherein using such y(2) for an actual synchronous frame synthesis begins when the time to digital converter (TDC) detects the end of the x(1) period of the referencing frame;

(72) y(3)=y(2), since x(2) and Δx(2) are not available yet when a derivation of y(3) is conducted;
y(4)=y(2)+h(0)Δx(2);
y(5)=y(2)+h(0)Δx(3)+h(1)Δx(2);
and further on
y(k+2+2)=y(2)+h(0)Δx(k+2)+h(1)Δx(k+1)+ . . . +h(k−1)Δx(3)+h(k)Δx(2),
y(n)=y(2)+h(0)Δx(n−2)+h(1)Δx(n−3)+ . . . +h(k−1)Δx(n−k−1)+h(k)Δx(n−k−2).
Consequently
Δy(n)=h(0)Δx(n−2)+h(1)Δx(n−3)+ . . . +h(k−1)Δx(n−k−1)+h(k)Δx(n−k2).

(73) The resulting transfer function of such FIR filter is presented below as:
ΔY(z)/ΔX(z)=z.sup.−2(h(0)+h(1)z.sup.−1+ . . . +h(k−1)z.sup.−(k−1)+h(k)z.sup.−k.

(74) Such FIR filter is designed below using a Frequency Sampling Method (FSM).

(75) The FSM is described in Section 10.2.3 of 4.sup.th Edition of “Digital Signal Processing” by John Proakis and Dimitris Manolakis.

(76) For exemplifying solutions claimed: the low pass filter of length M=15 with BW=1 and 2 Transition Coefficients equal to 0.590 and 0.095 chosen from Appendix B of the 4.sup.th Edition, has been designed with the Matlab program presented below.
N=15; k=0:N−1;
H=[1 0.590 0.095 0 0 0 0 0];
H=[H fliplr(H(2:end))];
H=H.*exp(−j*2*pi/N*(N−1)/2*k);
hlp2=real(ifft(H));
hlp2t2i5f=round(hlp2t, 5);
t=[k;hlp2t2i5f];
fprintf(′%2i%1.6f\n′,t);

(77) Such program produced filter coefficients listed below:
h(0)=h(14)=0.001290, h(1)=h(13)=0.006940, h(2)=h(12)=0.021000, h(3)=h(11)=0.046050,
h(4)=h(10)=0.080730, h(5)=h(9)=0.117980, h(6)=h(8)=0.147010, h(7)=0.158000.

(78) The DC gain of such filter G(ω=0) is equal to the sum (h(0)+h(1)+ . . . +h(13)+h(14))=1.

(79) The frequency response of such filter shown in FIG. 2A was produced using the Matlab program:
[H,W]=freqz(hlp2t2i5f,1);
Hdb=mag2db(abs(H));
plot(W,Hdb)

(80) Such FIR filter implementation using RNF method is shown in FIG. 2B and described below.

(81) It is explained in “SUMMARY OF THE INVENTION” that the measured lengths are expressed with integer numbers and can be added without any accumulation of time quantization errors, in order to define any longer time interval containing a plurality of the referencing frame periods.

(82) The differences Δx(n) defined using such measured lengths are integer numbers providing an accurate and complete base for the filter operations.

(83) The RNF FIR shown in FIG. 2B is producing the difference estimate Δy.sub.fil(n) which may contain an integer part Δy.sub.int(n) and a fractional part Δy.sub.fra(n).

(84) However DTC can introduce integer numbers only of the subclock periods to the lengths of the synchronous frame periods.

(85) Such DTC limitation would cause accumulation of quantization errors if such fractional parts Δy.sub.fra(n) were disregarded.

(86) Therefore the fractional parts Δy.sub.fra(n) are added instead to contents of the Modulo 1 Accumulator Δy.sub.acc(n−1) until such content becomes equal or greater than 1.

(87) When it happens only a fractional part of such content is kept in the Modulo 1 Accumulator and 1 is added to Δy.sub.int(n) and y(2) in order to produce y(n)=y(2)+Δy.sub.int(n)+1 expressed as an integer number.

(88) Such elimination of quantization errors accumulation can be achieved for every FIR filter having limited number of coefficients expressed with rational numbers,

(89) by deriving a common denominator and expressing these coefficients with rational numbers having such common denominator.

(90) All the coefficients of the FIR filter specified above, may be treated as rational numbers having the common denominator equal to 10.sup.5.

(91) All this filter outputs, shown in FIG. 2A as Δy.sub.fil(n)=Δy.sub.int(n)+Δy.sub.fra(n), may be obviously presented as rational numbers having the same common denominator equal to 10.sup.5.

(92) Consequently all the fractional parts of such outputs Δy.sub.fra(n) have the same denominator 10.sup.5 and can be accumulated using the Modulo 1 Accumulator until Δy.sub.acc_ovf=1 is produced and added to Δy.sub.int(n) and y(2) in order to prevent any accumulation of quantization errors.

(93) The y(n) specifies the length of such synchronous frame period with an integer number of the subclocks of the local clock.

(94) Since every synchronous frame period contains Nref=2304 periods of the synchronous clock synthesized by DTC, a length of every period of the synchronous clock shall amount to s(n)=y(n)/Nref=y(n)/2304.

(95) Such s(n) can be presented as a rational number containing an integer part s.sub.int(n) and a fractional part s.sub.fra(n).

(96) However DTC can use integer numbers only of the subclock periods for defining the lengths of the synchronous clock periods which it is producing.

(97) Therefore the s(n) are rounded by:

(98) adding the fractional part s.sub.fra(n) to consecutive contents of the Modulo 1 Accumulator (similar to that described above) corresponding to consecutive cycles of the synchronous clock until such contents are becoming equal or greater than 1;

(99) and when it happens, adding 1 to s.sub.int(n) in order to produce s.sub.acc_int(n,i)=s.sub.int(n)+1 wherein index i indicates a sequential number of a particular synchronous clock cycle within the synchronous frame period y(n).

(100) The resulting sequence defining 2304 of such synchronous clock cycles may be stored in a FIFO memory in PCU and downloaded gradually to DTC in reply to the LD_BU1 and LD_BU2 signals shown in FIG. 6, in order to produce i=1 to 2304 cycles of the synchronousclock contained in the synchronous frame period y(n).

(101) Methods covered by this invention include also downloading such sequence from PCU to a FIFO memory located in DTC equipped for utilizing content of such internal FIFO for producing the cycles of the synchronousclock contained in corresponding the synchronous frame period.

(102) 2.2 Rational Number Filter Approximating Infinite Impulse Response (RNF IIR)

(103) Principles of operations the RNF IIR are explained below as relating to approximations of IIR filters of 1.sup.st and higher orders as well.

(104) Such principles of operations are illustrated in the following subsection 2.2.1 showing their detailed implementation with the 1.sup.st order IIR filter.

(105) The measured length difference of the referencing signal frame Δx.sub.del(n) is applied to the filter input as an integer number Δx.sub.del(n) (see the subsection 2.2.1 and FIG. 2C).

(106) The filter outputs Δy(n)=Δy.sub.int(n)+Δy.sub.fra(n) are comprising both the integer and fractional components.

(107) The fractional components Δy.sub.fra(n) can not be implemented by DTC and their application to recursive branches of an IIR filter would produce a sequence of such Δy.sub.fra(n) which could not be expressed with rational numbers using a limited set of integer denominators.

(108) Such Δy.sub.fra(n) expressed with unlimited numbers of denominators could not be accumulated and utilized for driving the DTC in the way explained above for the FIR filter.

(109) Therefore only the integer part of the filtered phase Δy.sub.int(n) is applied to DTC and the recursive branches of the filter.

(110) Such omission of the the remaining fractional Δy.sub.fra(n) is equivalent to: a hypothetical subtracting of a part of of the present Δx.sub.del(n) corresponding to the Δy.sub.fra(n) from the entire Δx.sub.del(n) before applying the resulting quotient to the input of the filter which would consequently produce only the integer output Δy.sub.int(n).

(111) The subtracted part of the Δx.sub.del(n) corresponding to the Δy.sub.fra(n) is retained as Δx.sub.ret(n) and added to next the Δx.sub.del(n) in order to preserve filter DC gain (Gdc=G(ω=0)=1).

(112) It shall be noted that:

(113) such omission of Δy.sub.fra(n) is the only consequence of the subtraction of the corresponding part of Δx.sub.del(n), if and only if filters equation does not include any utilization of any delayed sample of Δx.sub.del(n);

(114) however if such utilization of the delayed sample occurs, than the delayed sample is affected as well and it shall be amended by subtracting from it the Δx.sub.ret(n).

(115) The resulting filter operates as a conventional IIR filter having LTI properties, but it is fed with Δx.sub.del modified by such subtracting of the Δx.sub.ret from the present Δx.sub.del and adding the same Δx.sub.ret to the next Δx.sub.del.

(116) Such modifications of the Δx.sub.del are affecting dynamic characteristics of the filter output but cannot change its DC gain.

(117) Due to high resolution of the Δx(n) produced by the TDC and corresponding to it Δy(n) applied to and utilized by the DTC, resulting changes of the dynamic characteristics shall be insignificant.

(118) Due to the LTI properties of such IIR filter, filters impulse response can be used for defining filter operations.

(119) An analysis of the impulse response of such IIR filter (see FIG. 2E) shows that such omission, retaining and addition are continuing until Δy.sub.int(n)=0 is reached and causes recursive branches to become inactive and returning zeroes.

(120) When the Δy.sub.int(n)=0 is settled, the same Δx.sub.ret is reapplied continuously and the same Δy.sub.fra would be circulated while Δy.sub.int(n)=0 would be outputted by the filter.

(121) Such ending of the impulse response would cause a granularity error of the filter to be equal to such settled Δx.sub.ret corresponding to the settled Δy.sub.fra.

(122) Although such granularity error is not cumulative, it can be multiple times greater than TDC or DTC quantization error.

(123) Such granularity error multiple times greater than quantization error introduced to Δx.sub.del by TDC, may be reduced to a size of the TDC quantization error, by adding the integer part of the last applied Δx.sub.ret to filter output.

(124) In order to reduce phase jitter, such addition may be distributed over time as it is exemplified in the Subsection 2.2.1 and FIG. 2C, wherein:

(125) coefficient “a” is subtracted from Δy.sub.fra and 1 is added to every consecutive filter output Δy(n), for as long as modulo(Δy.sub.fra) is greater than or equal to “a”;

(126) wherein the subtracting of “a” from Δy.sub.fra is equivalent to subtracting 1 from Δx.sub.ret, since aΔx.sub.ret=Δy.sub.fra.

(127) Such elimination of quantization errors accumulation can be achieved for every IIR filter using a limited number of coefficients expressed with rational numbers, by:

(128) using these coefficients and integer input signal for deriving components of this filter equation expressed with rational numbers having common denominator determined by these coefficients;

(129) preventing further multiplications of such rational numbers by recursive branches coefficients, by eliminating fractional parts of filter output signal (feeding the recursive branches) by modulating the input signal without changing filters DC gain.

(130) Such transforming of the remaining fractional parts of the filtered phase into retained parts of the measured lengths differences and adding them to next filter inputs in order to compensate the remaining fractional parts later on, is influencing still dynamic characteristics of the phase filter.

(131) However due to the high resolution of the TDC and DTC defined by the sub-clocks of the local clock, such influence on the dynamic characteristics shall be negligible.

(132) 2.2.1 Example of RNF Approximating IIR Filter.

(133) For exemplifying solutions claimed, an implementation of a low pass 1.sup.st order IIR filter is described first and the RNF approximating such IIR filter is presented next.

(134) It is assumed that this IIR filter is using factor a<<1 to attenuate variable components of the phase differences in order to filter out phase noise contributed by the referencing signal.

(135) Similarly as it is explained above in Sec. 2.1 it is assumed that:

(136) the phase tracking is initialized at the end of x(1) by starting the original produced period y(2)=x(0);

(137) the synchronous frame periods y(2), y(3), y(4), . . . y(n−1), y(n) are tracking the referencing frame periods x(0), x(1), x(2), . . . x(n−3), x(n−2);
Δx(1)=x(1)−x(0), Δx(2)=x(2)−x(0), . . . Δx(n−2)=x(n−2)−x(0);
Δy(3)=y(3)−y(2), Δy(4)=y(4)−y(2), . . . Δy(n)=y(n)−y(2).

(138) Phase tracking deviations d(k) between x(k) and y(k) are estimated and utilized for deriving following them y(k+1) as it is shown below:

(139) y(2)=x(0) wherein using such y(2) for an actual synchronous frame synthesis begins when the digital to time converter (DTC) detects the end of the x(1) period of the referencing frame,
d(2)=x(2)−x(0)=Δx(2),
y(3)=y(2);
d(3)=Δx(3)+Δx(2),
y(4)=y(2)+aΔx(2);
d(4)=Δx(4)+Δx(3)+(1−a)Δx(2),
y(5)=y(2)+aΔx(3)+a(1−a)Δx(2);
d(5)=Δx(5)+Δx(4)+(1−a)(Δx(3)+(1−a)Δx(2)),
y(6)=y(2)+a(Δx(4)+(1−a)(Δx(4)+(1−a)(Δx(3)+(1−a)Δx(2))).
Consequently
Δy(n)=aΔx(n−2)+(1−a)Δy(n−1).

(140) The resulting transfer function of such IIR filter amounts to:
ΔY(z)/ΔX(z)=a z.sup.−2/(1−(1−a)z.sup.−1).

(141) Impulse response of such IIR filter is derived below.
When Δx(2)=Δx.sub.imp>0 and Δx(3)=Δx(4= . . . =Δx(n−1)=Δx(n)=0:
Δy(2)=0
Δy(3)=0,
Δy(4)=aΔx(2)=aΔx.sub.imp,
Δy(5)=aΔx(3)+a(1−a)Δx.sub.imp=(1−a)aΔx.sub.imp

(142) and finally
Δy(n)=aΔx(n−2)+(1−a)Δy(n−1)=(1−a).sup.n−4aΔx.sub.imp.

(143) The resulting sum is
Δy(2)+Δy(3)+Δy(4)+ . . . +Δy(n)=aΔx.sub.imp(1+(1−a)+(1−a).sup.2 . . . (1−a).sup.n−4),

(144) and such sum converges to aΔx.sub.imp(1/(1−(1−a)))=aΔx.sub.imp (1/a)=Δx.sub.imp

(145) when n converges to infinity.

(146) Consequently this IIR filter has DC gain G(ω=0) equal to 1.

(147) Frequency response of conventional implementation of such IIR filter using a=0.05, is shown in FIG. 2C.

(148) Such conventional IIR filter would be expressed conventionally with the equation:
Δy(n)=aΔx.sub.del(n)+(1−a)Δy(n−1)).

(149) The RNF approximating this IIR filter is shown in FIG. 2D as comprising modifications explained below.

(150) In order to omit the Δy.sub.fra(n) and apply only Δy.sub.int(n) to the output and recursive branch, the corresponding to it Δx.sub.ret(n) shall be treated as being subtracted from the Δx.sub.del(n) and it shall be added to a next Δx.sub.del(n) to compensate for this subtraction.

(151) However such Δx.sub.ret(n) would equal to Δy.sub.fra(n)/a and adding it to the next Δx.sub.del(n) would be equivalent to increasing a next Δy.sub.fil(n) by aΔx.sub.ret(n)=aΔy.sub.fra(n)/a=Δy.sub.fra(n).

(152) Such unneeded multiplication and division of Δy.sub.fra(n) by the same factor a, is avoided by the direct increasing of the next Δy.sub.fil(n) by Δy.sub.fra(n) shown in FIG. 2D.

(153) Since this filter's forward branch coefficient equals to “a” and the recursive branch coefficient equals to “1−a”, it's Δx.sub.ret(n) would always amount to an integer number if it were calculated.

(154) Therefore the accumulation of fractional parts of Δx.sub.ret(n), mentioned in SUMMARY OF THE INVENTION, is not needed for this particular filter and not shown in FIG. 2D.

(155) An analysis of the impulse response of such IIR filter shows that

(156) Such omission of Δy.sub.fra(n) and increasing by it the next Δy.sub.fil(n) continues until Δy.sub.int(n)=0 is reached and causes recursive branches to become inactive and returning zeroes. When the Δy.sub.int(n)=0 is settled, the same Δy.sub.fra would be reapplied continuously and the same Δy.sub.int=0 would be outputted indefinitely by the filter.

(157) Such ending of an impulse response of the filter would cause a granularity error of the filter to be equal to Δx.sub.del=Δy.sub.fra/a.

(158) Due to the hypothetical Δy.sub.fra circulation continuing indefinitely, such granularity error would be noncumulative.

(159) However it would be 1/a times greater than Δx.sub.del quantization error.

(160) It is shown in FIG. 2D that such granularity error is reduced to the Δx.sub.del quantization error, by:

(161) subtracting “a” from Δy.sub.fra and forcing every consecutive filter output Δy(n) to 1, for as long as Δy.sub.int(n)=0 and modulo(Δy.sub.fra) is greater than or equal to “a”;

(162) wherein the subtracting of “a” from Δy.sub.fra is equivalent to subtracting 1 from Δx.sub.ret, since aΔx.sub.ret=Δy.sub.fra.

(163) Impulse Response of the RNF IIR shown in FIG. 2D and based on assumptions that a=0.05 and Δx.sub.imp(0=50, is detailed in FIG. 2E confirming achieving noncumulative filter quantization error lesser than that of the filter input Δx.sub.del.

(164) Thus this specification contributes elimination of accumulation of quantization errors of RNF approximating IIR filters, by delaying applications of parts of their input signal which are corresponding to fractional parts of their output signal.

(165) 2.3 Phase Transferring Using the CLS.

(166) The implementation of CLS with the phase transferring configuration (PTC shown in FIG. 1C) replacing a VCO used conventionally with a cost lowering free running oscillator, has been introduced in SUMMARY OF THE INVENTION.

(167) Both OLS RNF and CLS based PTCs can be implemented with the same hardware configuration presented in FIG. 1C.

(168) The PTC implementing CLS comprises PCU programmed to initiate the phase transferring process by:

(169) measuring a lengths of initial interval of the referencing signal x(0) by subtracting a first phase captured by TDC1 from a second phase captured by TDC1 (as in OLS RNF based PTC);

(170) driving DTC into presetting a length of the 2nd interval of SYN_FRA y(2) to x(0) and a length of the 3rd interval of SYN_FRA y(3) to x(0) as well (as in OLS RNF based PTC);

(171) After the initialization the PCU programmed to implement CLS, shall:

(172) measure phase errors Δx.sub.err(2), . . . Δx.sub.err(n−2) between the timing referencing signal REF_FRA and the timing implementing signal SYN_FRA,

(173) by subtracting a phase of the end of the number 2, . . . (n−2) interval of SYN_FRA (supplied by Phase Reg.2 and named as y.sub.end(2), . . . y.sub.end(n−2)) from a phase of the end of the number 2, . . . (n−2) interval of REF_FRA accordingly (supplied by Phase Reg.1 and named as x.sub.end(2), . . . x.sub.end(n−2));

(174) apply Δx.sub.err(2), . . . Δx.sub.err(n−2) to an input of a CLS filter (similarly as Δx.sub.del(2), . . . Δx.sub.del(n−2) are applied to RNF);

(175) add outputs of the CLS filter Δy.sub.fil(2), . . . Δy.sub.fil(n−2) to the y(2), in order to derive synthesized synchronous frame intervals y(4)=y(2)+Δy.sub.fil(2), . . . y(n)=y(2)+Δy.sub.fil(n−2) accordingly (similarly as in OLS RNF based PTC);

(176) wherein the CLS filter shall be designed by using methods of digital control engineering known commonly (taught in books such as “Digital Control Engineering Analysis and Design” by Sami Fadali and Antonio Visioli and in the Chapter 6 of this book specifically);

(177) apply the synchronous frame intervals y(2), y(3), y(4), . . . y(n) to the input of DTC which is using them for producing the synchronous clock and frame (SYN_Clk and SYN_FRA) from the subclocks of the free running local clock (LOC_Clk represented by the Clk0.1 in FIG. 1C).

(178) 2.4 Adaptive PTC Applications

(179) The PTC hardware is defined by system presented in FIG. 1C.

(180) Such PTC hardware may be driven by diversified software systems in order to create different PTC versions needed to satisfy requirements of diversified PTC applications.

(181) Such different versions include but are not limited to PTC implementing OLS with performance monitoring & control described in Subsection 1B of SUMMARY OF INVENTION and PTC implementing CLS described above in Subsection 2.3.

(182) In addition to the mentioned above PTC versions, such different versions defined by diversified software systems may include:

(183) analysing frequency spectrum and/or other quality indicators of REF_FRA (by using the measured timing referencing intervals) and/or those of SYN_FRA (by measuring and using the timing implementing intervals of SYN_FRA);

(184) adaptive changing of PTC operations to those performing different functions more suitable for satisfying said application requirements;

(185) wherein such adaptive changing of PTC operations may include but is not limited to changing PTC operations by modifying RNF filter used or switching from implementing OLS with performance monitoring & control to the implementing of CLS.

(186) Such software systems may be downloaded to PTC from an external memory and may perform such switchings on the fly during continuing PTC operations.

(187) Thus the implementations of the diversified versions of PTC and changes of PTC functionality mentioned above, may be enabled by utilizing different software systems consisting of different codes and/or micro-codes for controlling PTC hardware.

(188) 3. Time to Digital Converter (TDC)

(189) Block diagram of TDC is shown in FIG. 3A.

(190) The Sequential Clock Generator detailed in FIG. 4A and Sec. 4 utilizes a ring oscillator for multiplying frequency of the oscillator clock (OSC_Clk) for producing the local clock (LOC_Clk) and its subclocks Clk0, Clk1, . . . ClkR needed to secure high resolution of digital phase measurements.

(191) Such subclocks Clk0, Clk1, ClkR occurring during every period of the local clock are used for producing subclocks 1Clk0, 1Clk1, . . . 1ClkR/2Clk0, 2Clk1, 2ClkR occurring during odd/even periods accordingly of the local clock.

(192) Such odd/even periods can be treated as belonging to phase 1/phase 2 accordingly of the local clock.

(193) The subclocks 1Clk0, 1Clk1, . . . 1ClkR/2Clk0, 2Clk1, . . . 2ClkR are named as 1Clk(R:0)/2Clk(R:0) accordingly in FIG. 3A and FIG. 4.

(194) The clock equalization circuit (CEC) shown in FIG. 4B exemplifies system of buffers designed to secure timing of the Clk(R:0).1 1Clk(R:0).1, 2Clk(R:0).1 defined by their prefixes and suffixes and corresponding to their functions.

(195) When different loads are driven by the clocks, different sizes and numbers of buffers producing these clocks shall be utilized to achieve the timing defined in FIG. 3A, FIG. 3B and FIG. 5A, FIG. 5B, FIG. 7A, FIG. 7B.

(196) Requirements imposed on CEC accuracy can be reduced by increasing tolerance margins of phase alignments of the subclocks defining timing of DTP, TDC and DTC,

(197) by increasing numbers of the parallel subclock phases used in the multiphase processors implemented with specific IC technologies having specific performance accuracies (see also Sec.3 of SUMMARY OF THE INVENTION).

(198) The equalization may be also needed for other clocks such as Clk0.1 shown in FIG. 3A.

(199) For the sake of easier readability the common name Clk0.1 is used in FIG. 3A for signals driving DFP, SC and IPR, while in reality these signals may require an equalization in time by using different buffers securing sufficient time alignment to the original Clk0.1.

(200) A detector of fractional phase (DFP) detailed in FIG. 3B uses 1Clk(R:0), 2Clk(R:0) for capturing accurate phase of a referencing frame (REF_FRA) signal activated when a boundary of the referencing frame occurs.

(201) The splitting of the subclocks Clk0, Clk1, . . . ClkR into adjacent subsets 1Clk(R:0) and 2Clk(R:0) allows elimination of a dead zone condition explained below.

(202) When the end of frame occurs and its phase is captured with 1Clk(R:0)/2Clk(R:0) during such odd/even period, the captured phase remains unchanged during following adjacent even/odd period.

(203) Therefore this captured phase can be safely registered using ClkR-1.1 occurring during such following even/odd period and any occurrence of a dead zone can be avoided.

(204) The DFP keeps sensing REF_FRA signal when TDC enable (TDC_ENA) signal sent by PCU is active.

(205) PCU initiates entire process of time to digital conversion by activating TDC_ENA in a middle of a period of the referencing frame in order to avoid TDC_ENA interference with REF_FRA signal defining a boundary of the referencing frame.

(206) When REF_FRA signal becomes active it keeps setting to 1 all consecutive bits of frame capture buffers FCB1(0:R) and FCB2(0:R) loaded by consecutive subclocks 1Clk(0:R).1 and 2Clk(0:R).1.

(207) When initially the bit R of a frame capture buffer of FCB1(0:R)/FCB2(0:R) is set to 1 by the subclock 1ClkR.1/2ClkR.1 accordingly, the bit R of next to it FCB2(0:R)/FCB1(0:R) accordingly remains reset for time period equal to Clk0.1 cycle equivalent to that of LOC_Clk cycle.

(208) Therefore the signal FCB1_SEL/FCB2_SEL is selecting FCB1(0:R)/FCB2(0:R) to be loaded to frame capture register FCR(0:R) with the CLKR-1.1 following such initial setting of bit R by almost one cycle of Clk0.1 defining timing equivalent to that of LOC_Clk.

(209) However such FCB1_SEL/FCB2_SEL is deactivated when the bit R of the FCB2/FCB1 accordingly is activated at the end of the following Loc-Clk cycle.

(210) Therefore the 3:1 Selector will keep selecting the FCR(R:0) to be reloaded with its previous content and the FCR(0:R) will remain unchanged for as long as active REF_FRA and active TDC_ENA are supplying 1s to consecutive bits of the FCB1 and FCB2.

(211) Such content of FCR(0:R) is encoded into binary form by the selector R+1:1 SEL producing fractional phase number FPN(S:0) specifying a number of subclocks defining accurate time delay between preceding Clk0.1 (LOC_Clk) and the REF_FRA signal.

(212) The R bit of FCR (FCRR) enables activation of the control flip-flop 1 (C_FF1) and load synchronous counter (LD_SC) signal with a falling edge of Clk0.1.

(213) The LD_SC selects the synchronous counter (SC(K:0)) to be loaded to the integer phase register (IPR(K:0)) which supplies an integer number of local clock cycles, occurring between consecutive detections of reference frame boundaries, to PCU.

(214) The C_FF1 enables activation of the control flip-flop 2 (C_FF2) with the next falling edge of the Clk0.1 and generation of the read request (RD_REQ) signal; which are:

(215) deactivating the C_FF1 and the LD_SC signal in order to preserve content of the IPR supplying to PCU an increased by 2 number of Clk0.1 cycles counted with the synchronous counter (SC(K:0)) before the REF_FRA activation;

(216) loading the FPN(S:0) to the fractional phase register (FPR(S:0)) supplying a number of subclocks occurring between the last activation of Clk0.1 and the activation REF FRA signal;

(217) signaling to PCU that the IPR(K:0) and the FPR(S:0) shall be read.

(218) PCU replies to the RD_PHA by deactivating TDC_ENA signal for a time interval lasting several cycles of LOC_Clk.

(219) The deactivated TDC_ENA is resetting FCR(R:0) and C_FF2 in order to prepare for correct capturing of the next edge of REF_FRA.

(220) 4. Digital to Time Converter (DTC)

(221) DTC outlined in Sec.3 of SUMMARY OF INVENTION is shown in FIG. 4, FIG. 4A-B, FIG. 5A-C, and FIG. 6. The timing diagram of DTC operations is shown in FIG. 7B.

(222) The Block Diagram of DTC is shown in FIG. 4.

(223) The Detector of Initial Frame Phase (DIFP) (detailed in FIG. 5A) utilizes sequential subclocks of LOC_Clk for capturing phase of REF_FRA with resolution matching single subclock delay, in order to enable accurate DTC initialization by the real time event presented by the appearance of an edge of REF_FRA signaling the end of x(1).

(224) In order to secure real time operations, all timing of SYN_Clk programmed by PCU is generated by DTC as related to the real time event signaled with the REF_FRA which causes the initialization of the startup process with the signal SC_ACT generated by DFIP.

(225) The Timing Starting Circuit (TSC) (detailed in FIG. 5B) is activated by SC_ACT and it synchronizes DTC startup by assigning timing steps needed to secure correct initialization of consecutive stages of the real time sequential processor (RTSP) with timely delivered phase adjustments supplied by PCU with signals PN1, FN1 and PN2, FN2.

(226) The Timing Control Circuit (TCC) (detailed in FIG. 5C) is activated by signals S1E, S2E, and it produces signals LD_BU1, LD_BU2 securing timely delivery and downloading of the phase adjustments and signals controlling processing of the phase adjustments by the RTSP stages.

(227) The Real Time Sequential Processor (RTSP) detailed in FIG. 6 is controlled by signals generated by TCC and it produces:

(228) signals C1E/C2E communicating to TCC that processing of consecutive such phase adjustment by RTSP's phase1/phase 2 accordingly has been ended;

(229) signals 1CS(R:0)/2CS(R:0) designed to select subclocks belonging to LOC_Clk's phase1/phase 2 accordingly as those implementing the phase adjustments programmed by PCU.

(230) The Output Selection Circuit (OSC) (detailed in FIG. 4A) is using such 1CS(R:0)/2CS(R:0) for such selection of these subclocks and for outputting the selected subclocks as the SYN_Clks.

(231) The Sequential Counter Modulo 2304 and the Selector of Frame Boundary Clock are selecting every 2304.sup.th SYN_Clk as signaling an end of SYN_FRA.

(232) RTSP implements the DWS MSC method explained in Sec.3 of SUMMARY OF INVENTION.

(233) In order to allow higher frequencies of time signaling waveforms/eliminate dead zones in time synthesizing circuits, the sequential processing stages/parallel processing phases are utilized for deriving/implementing accordingly phases of consecutive edges of the synchronous clock.

(234) In order to facilitate processing of consecutive timing data programmed by PCU and supplied as sequence of PN1+FN1 alternating in time with PN2+FN2, said sequential processing stages are implemented as PC1, PNR1, PNB1 and PC2, PNR2, PNB2 timed by the signals detailed further below.

(235) DTC operations described herein are explained and confirmed additionally by timing diagrams of SCG and DTC shown in FIG. 7A and FIG. 7B accordingly.

(236) It shall be noted that:

(237) all the selectors shown in the drawings presented herein are using a most top active selecting signal for selecting a corresponding (looking from the left) input signal, while all the next selecting signals are disabled by the most top active selective signal;

(238) when all selecting signals shown are inactive (and none of corresponding to them input signals is selected), the last (looking from the left) input is selected even if choosing it selecting signal is not shown.

(239) The DTC uses the same Sequential Clocks Generator (SCG) (shown in FIG. 4A and FIG. 7A) as the TDC (described above in Sec.3).

(240) Such SCG produces subclocks of the local clock (LOC_Clk) by implementing the odd/even phase generator (mentioned above in Sec.3 of SUMMARY OF THE INVENTION); wherein:

(241) the reference propagation circuit is implemented as the ring oscillator multiplying frequency of the oscillator clock (OSC_Clk) by factor of L and producing local clock subclocks Clk(R:0);

(242) the serially connected flip-flops driven by the subclocks Clk(R:0), are shown as producing signals PR(R:0), PR(R:0)N;

(243) the odd/even selector is shown as using the signals PR(R:0), PR(R:0)N for producing subclocks 1Clk(R:0)/2Clk(R:0) activated during odd/even cycles of the local clock (LOC_Clk) accordingly.

(244) Since the frequency multiplication (applied optionally to enable more efficient operations of the phase tracking system) maintains fixed relation of the local clock to the free running oscillator clock, the local clock shall be considered to be free running as well.

(245) The same subclocks 1Clk(R:0), 2Clk(R:0) are used by TDC1 & TDC2/DTC for measuring/synthesizing phase of the referencing frame (REF_FRA)/synchronous frame & synchronous clock (SYN_FRA&SYN_Clk) accordingly (see FIG. 1B and FIG. 1C).

(246) Similarly as it has been explained for TDC, the subclocks generated by SCG may need to be equalized by circuits exemplified in FIG. 4B in order to maintain timing defined by the ring oscillator outputs Clk0, Clk1, ClkR-1, ClkR.

(247) Output Selection Circuit (OSC) shown in FIG. 4A uses the clock selection signals 1CS(R:0)/2CS(R:0 produced by the 1.sup.st clock selector (1CS)/2.sup.nd clock selector (2CS) shown in FIG. 6 for selecting one of the subclocks 1Clk(R:0)/2Clk(R:0) accordingly for producing the synthesized synchronous clock (SYN_Clk).

(248) In order to improve resolution to better than that of LOC_Clk cycle, more accurate timing of REF_FRA is measured using a detector of initial frame phase (DIFP) shown in FIG. 5A.

(249) The DFIP operates similarly as the DFP shown in FIG. 3B and described in the Sec. 3 presented above.

(250) PCU enables DIFP operations starting entire process of digital to time conversion, by activating DTC_ENA in a middle of a period of the referencing frame,

(251) in order to avoid DTC_ENA interference with REF_FRA signal defining timing of a boundary of the referencing frame.

(252) Such REF_FRA keeps setting to 1 all consecutive bits of frame capture buffers FCB1(0:R) and FCB2(0:R) loaded by consecutive subclocks 1Clk(0:R).1 and 2Clk(0:R).1.

(253) When initially the bit R of a frame capture buffer of FCB1(0:R)/FCB2(0:R) is set to 1 by the subclock 1ClkR.1/2ClkR.1 accordingly, the bit R of next to it FCB2(0:R)/FCB1(0:R) remains reset for time period equal to LOC_Clk cycle.

(254) Therefore the signal FCB1_SEL/FCB2_SEL keeps selecting FCB1(0:R)/FCB2(0:R) to be loaded to frame capture register FCR(0:R) by CLKR-1.1 (following such initial setting of bit R), by almost one cycle of LOC_Clk.

(255) Content of FCR(0:R) remains unchanged for as long as both DTC_ENA and REF_FRA are active.

(256) The DTC_ENA and REF_FRA can be deactivated after deactivation of the S2E signal only, wherein the S2E indicates that RTSP stages are not pre-loaded yet and FCR(0:R), FN(S:0) shall not be changed yet.

(257) Content of FCR(0:R) is encoded into binary form by the selector R+1:1 SEL producing FN(S:0) specifying number of a subclocks defining accurate time delay between preceding LOC_Clk and REF_FRA signal.

(258) The R bit of FCR (FCRR) is used to set starting counter activation (SC_ACT) signal with the falling edge of ClkR.1.

(259) The SC_ACT is used to initiate DTC startup operations which are needed for pre-loading multiple stages of the real time sequential processor (RTSP) shown in FIG. 6 before any derivation and generation of the synchronous clock (SYN_Clk) may begin.

(260) Such SC_ACT initiates the timing starting circuit (TSC) shown in FIG. 5B by setting S2E signal with the Clk1.1 (which is timing majority of other DTC operations as well).

(261) The setting of S2E enables starting counter (SC) to identify starting steps 0 to 5 needed to define S1E and S2E signals driving timing control circuit (TCC) during DTC startup operations.

(262) The TCC is shown in FIG. 5C and its timing is shown in FIG. 7B.

(263) S2E activates load counter 1 (LD_C1) signal and enables activation of load register 1 (LD_RE1) signal by following Clk1.1.

(264) LD_C1 loads periodical number register 1 (PNR1) to periodical counter 1 (PC1) (see FIG. 6).

(265) LD_RE1 loads periodical number buffer 1 (PNB1) to periodical number register 1 (PNR1) (see FIG. 6).

(266) LD_C1 is deactivated instantly when the LD_RE1 is activated.

(267) S1E is activated by one cycle later than S2E when the SC is switched from SC=0 to SC=1.

(268) S1E activates load counter 2 (LD_C2) signal and enables activation of load register 2 (LD_RE2) signal by following Clk1.1.

(269) LD_C2 loads periodical number register 2 (PNR2) to periodical counter 2 (PC2).

(270) LD_RE2 loads periodical number buffer 2 (PNB2) to periodical number register 2 (PNR2).

(271) LD_C2 enables deactivation of the LD_RE1 and activation of load buffer 1 (LD_BU1) signal, by Clk1.1.

(272) LD_BU1 loads periodical number 1 (PN1) supplied by PCU to PNB1 (see FIG. 6).

(273) LD_C2 is deactivated instantly when the LD_RE2 is activated.

(274) Such interactions between the S2E, LD_C1, LD_RE1 and S1E, LD_C2, LD_RE2 are repeated during the DTC startup, until PNB1, PNR1, PC1 and PNB2, PNR2 are preloaded from PCU with a content defining positioning of SYN_Clk edges.

(275) In addition to driving such TCC operations, the S2E is used to:

(276) signal to PCU if the startup is in progress or discontinued;

(277) disable specific RTSP functions which could cause generation of redundant or erroneous SYN_Clks during the startup (see FIG. 6).

(278) TCC produces also synthesis preparation (SYN_PRE) signal activated by RESET and deactivated by LD_BU2.

(279) SYN_PRE is shown in FIG. 6 as causing a subtraction of 9 from the first PN1(P:0) and addition of FN(S:0) to the first FN1(S:0) downloaded from PCU.

(280) Such initial amendments of the first PN1(P:0) and FN1(S:0) are designed to align SYN_Clk to the real time event detected by DFIP (such as the end of x(1)), by subtracting inherent startup delay (amounting to 9 cycles of LOC_Clk minus FN(S:0) subclocks delays) from the length of the first period of SYN_Clk defined by PCU.

(281) Periods of SYN_Clk must be defined by PC1/PC2 as equal to or longer than 1 cycle of LOC_Clk, in order to be implemented by RTSP.

(282) Consequently the first period of SYN_Clk must be defined by PCU as equal to or longer than 10 cycles of LOC_Clk, in order to satisfy the 1 cycle requirement after the initial amendments mentioned above.

(283) When SYN_Clk periods shorter than 10 LOC_Clk cycles need to be generated, PCU may:

(284) define first SYN_Clk period as equal to the 10 still;

(285) subtract the expected lengths of the first SYN_Clk period from the 10;

(286) distribute the quotient between next expected SYN_Clk periods by adding to them gradually all the parts of the quotient.

(287) It shall be noted that such start up irregularity may affect SYN_Clks of the first SYN_FRA only and cannot cause any further timing misalignment in relation to the real time event initiating DTC.

(288) At the end of the startup, LD_C1 signal enables downloading to PC1 a number of periods which the previous stages of the RTSP have calculated for the current phase adjustment.

(289) Such downloading activates counter 1 end (C1E) signal if a downloaded value is equal to 1.

(290) When said downloaded value is bigger than 1, the C1E=0 causes generation of PlEN=1 signal which enables decreasing the PC1 content by 1 by Clk1.1 until the PC1=1 condition is detected by the PC1=1 Detector producing C1E=1 signal.

(291) After such startup, the C1E and counter 2 end (C2E) signals are generated alternately as indicating that programmed by PCU numbers of LOC_Clk cycles specifying positioning of consecutive edges of SYN_Clk have expired.

(292) Such C1E/C2E signals are driving TCC in the same way as S1E/S2E accordingly, as it is shown in FIG. 5C, FIG. 6 and FIG. 7B.

(293) It can be seen in FIG. 7B that such initialization and startup operations are adding a delay of 9 cycles of LOC_Clk to that defined by the first PN1(P:0) for the first generated SYN_Clk.

(294) The 9 cycles delay is contributed by initial preloading of sequential stages of DFIP and RTSP, before actual implementation of phase adjustments of SYN_Clk may begin.

(295) Since fractional time delay between preceding LOC_Clk and REF_FRA signal is specified by the FN(S:0), actual time delay between REF_FRA and following it LOC_Clk amounts to 1−FN(S:0).

(296) Such 1−FN(S:0) delay is taken into account by:

(297) including 1 LOC_Clk delay into the 9 cycles delay specified above;

(298) adding FN(S:0) to FN1(S:0) as it is described below.

(299) Another delay equal to 1 cycle (included into the 9 cycles delay as well) is added inherently during splitting to different parallel phases, when clock selection register 1 (CSR1) or clock selection register 2 (CSR2) is loaded with a content of a fraction selection register (FSR(ICS,S:0)) and actual subclock selection is implemented during the next cycle of LOC_Clk (see detailed description further below).

(300) In order to apply timing started by REF_FRA and defined by PCU to SYN_Clk generation, the SYN_PRE active at the beginning of startup operations is selecting:

(301) PN1(P:0)−9 to be loaded to PNB1(P:0);

(302) FN1(S:0)+FN(S:0) to be loaded to FNB1(OVF,S:0).

(303) After being loaded by LD_BU1/LD_BU2 signals, fractional number buffers FNB1/FNB2 are merged into the fractional number selector FNS(OVF(1:0),S:O) produced by 3:1 selector controlled by selecting fractional number SEL_FN1/SEL_FN2 signals generated by TCC shown in FIG. 5C.

(304) The SEL_FN1/SEL_FN2 is activated for a period equal to LOC_Clk cycle when Clk0.1 encounters active LD_C1/LD_C2 signal accordingly (see also FIG. 7B).

(305) The FNS(OVF(1:0),S:O) is loaded into fractional number register FNR(OVF(1:0),S:0) with LD_RE signal activated by delayed derivatives of SEL_FN1 or SEL_FN2 for a time longer than half of LOC_Clk cycle.

(306) The FNR(OVF(1:0)), indicating if FNR content accumulated during previous operations exceeds a fractional value and amounts to 1 or 2 plus FNR(S:0), is adding 1 or 2 to a content of PNR1/PNR2 before such increased content is downloaded to PC1/PC2 accordingly.

(307) It is assumed that P:0 range is sufficient to avoid any overflow caused by such addition.

(308) The FNR(S:0) is combined with inhibiting clock selection signal FNR(ICS) described below, before being loaded to the fraction selection register FSR(ICS,S:0) by Clk1.1.

(309) The FNR(ICS) is preventing generation of redundant edges of SYN_Clk during entire DTC startup and after the startup when phases of SYN_Clk edges are not derived yet.

(310) During the startup the deactivation of FNR(ICS) by LD_C1/LD_C2 is prevented by S2E signal indicating that this LD_C1/LD_C2 is generated during pre loading of PC1, PNR1, PBU1/PC2, PNR2, PBU2 accordingly and phase of an initial edge of SYN_Clk is not derived yet.

(311) After the startup FNR(ICS) is deactivated when LD_C1 or LD_C2 are signaling that phases of edges of SYN_Clk have been derived and shall be implemented.

(312) The FNR(ICS) is supplementing FNR(S:0) in order to construct FNR(ICS,S:0) which is loaded to the fraction selection register FSR(ICS,S:0) specifying number of a subclock of LOC-Clk which will define phase of a next edge of SYN_Clk.

(313) The clock selection registers CSR1(ICS,S:0)/CSR2(ICS,S:0) are loaded with a current content of the FSR(ICS,S:0).

(314) When CSR1(ICS)/CSR2(ICS)=0, such CSR1/CSR2 specifies a subclock which will be selected in a forthcoming Phase1/Phase2 by a clock selector 1CS(R:0)/2CS(R:0) accordingly by decoding (S:0) binary code and activating its corresponding R:0 output.

(315) In order to avoid any dead zone and keep clocks selector 1CS(R:0)/2CS(R:0) settled during a whole next cycle of LOC_clk, CSR1/CSR2 registers are loaded by the falling edge of subclock 2Clk0.1/1Clk0.1 of a current Phase2/Phase1 accordingly of LOC-Clk

(316) In order to secure SYN_FRA timing programmed by PCU, the first SYN_FRA having lengths defined by y(2), shall be initialized exactly at the end of x(1) interval of REF_FRA.

(317) It is described above how such exact timely initialization is secured by:

(318) using DIFP for detecting the end of x(1) interval and measuring a delay between the end of x(1) and following it edge of LOC_Clk as equal to 1−FN(S:0);

(319) using the measured delay for presetting RTSP to produce the first SYN_FRA interval defined by y(2) beginning at the end of x(1).

(320) However solutions based on using the PTC shown in FIG. 1C are including also using TDC2 for simplifying DTC described above by eliminating DFIP.

(321) Such elimination of DFIP can be achieved by supplementing PCU circuit and program functions with:

(322) initiating DTC to produce the first SYN_FRA interval defined by y(2), when RD_REQ signaling the end of x(1) is received;

(323) measuring time delay between the phase of the end of x(1) supplied in Phase Reg.1 and the phase of the end of such first SYN_FRA interval supplied in Phase Reg.2;

(324) deriving delay of the RTSP initialization by subtracting the y(2) from the measured time delay;

(325) amending length of y(4) interval by subtracting from it the derived delay.

(326) It is shown in FIG. 8 that the synchronous clock (SYN_Clk) may be connected to the jitter filter of the SYN_Clk (JFSC) added for producing the sampling clock (SAM_Clk) which may be used instead of the SYN_Clk for sampling the baseband signal mixed out from the received OFDM signal with the high frequency local carrier clock (CAR_Clk).

(327) The JFSC can be designed to prevent inter carrier interference (ICI) by reducing analog jitter (introduced by the SCG and the OSC) and digital jitter (caused by the granularity of TDC output determined by the Tsc).

(328) Sufficient filtering out of such analog & digital jitter can be achieved by using the JFSC based on technologies such as:

(329) “DPLL—Jitter Cleaner PLL Digital Loop Filter” from Creative Silicon;

(330) “Si5386 1-DSPLL Wireless Clock” from Silicon Labs.

(331) Such jitter filtering technologies are enabling very high efficiency by replacing two-stage cascaded PLL with two-stage nested DSPLL such as that described in Silicon Labs publication “Clocks for 4.5G Radio Access Networks”.

(332) It is also shown in FIG. 8 that the SAM_Clk may be connected to the jitter filtering frequency multiplier (JFFM) which can utilize a dual loop configuration (based on the technologies mentioned above) for producing the high frequency local carrier clock (CAR_Clk) used to mix down the received OFDM signal into the base-band sampled with the SAM_Clk.

(333) The DTP described above can be utilized for implementing IEEE 1588 as it is described in greater detail below.

(334) It is shown in FIG. 9 that: times Tn,1 & Tn,4/Tn,2 & Tn,3 are communicated to/detected by PTP Slave, during the messaging cycle numbered n; times Tn+1,1 & Tn+1,4/Tn+1,2 & Tn+1,3 are communicated to/detected by PTP Slave, during the messaging cycle numbered n+1.

(335) The referencing frame REF_FRA described above as detected by referencing signal receivers, can be defined for the PTP as:
REF_FRA(n)=Tn+1,2−Tn,2.

(336) However a nominal number of syntonized PTP clocks Nref(n) (corresponding to the nominal number Nref of the SYN-Clks) expected to occur during the REF_FRA(n) is not constant (in contrary to that of the SYN_Clks) and defined by:
Nref(n)=Tn+1,1−Tn,1.

(337) Since every period of a syntonized frame (SYNT_FRA(n)) period shall contain Nref(n) periods of such syntonized PTP clock (SYNT_Clk(n)) synthesized by DTC, a length of every period of the SYNT_Clk(n) shall amount to s(n)=y(n)/Nref(n); wherein the y(n) shall be derived as it is explained in Sec.2 of Detailed Description.

(338) Any accumulation of quantization errors during the synthesis of consecutive periods SYNT_Clk(n,i) of SYNT_Clk(n), can be prevented in the same way as that shown above for the synthesis of the periods s(n,i) of SYN_Clk.

(339) A latency of a specific SYNT_FRA(n) and the SYNT_Clk(n,i) can be derived as equal to: LAT(n)=[(Tn,2−Tn,1)+(Tn,4−Tn,3]/2, when delay symmetry is assumed.

(340) Such latency LAT(n) can be:

(341) used directly for defining periods of a second following synchronous PTP clock (SYNC_Clk(n+2)) aligned in time to PTP Master Clock;

(342) passed through a low pass filter before being utilized for defining such SYNC_Clk(n+2), similarly as the x(n) is passed through FIR/IIR filters producing the y(n) used for synthesizing the SYN_Clk (see the Sec.2 of Detailed Description).

(343) It shall be noted that the DTP TSN method, apparatus and circuits exemplified herein as implemented by using the DTP can be also implemented, by any person skilled in the art, by using conventional signal & time processing methods and circuits such as DPLL.

(344) Therefore such DTP TSN implementations using the conventional signal & time processing methods and circuits are covered as well by the invention presented herein.

CONCLUSION

(345) In view of the above description of the invention and associated drawings, other modifications and variations will now become apparent to those skilled in the art based on the teachings contained herein. Such other modifications and variations fall within the scope and spirit of the present invention.