BASELINE RESTORER CIRCUIT

Abstract

A baseline restorer circuit including a controller; a sample control circuit arranged to receive an input voltage signal that is output from a circuit stage comprising an amplifier, and configured to capture a sample of the input voltage signal at a sampling time in response to receiving a control signal from the controller; an analogue processing stage to receive the sample and a constant baseline reference voltage and selectively process the sample to provide an output voltage; a transconductance stage to convert the output voltage to a compensation current and supply the compensation current to an input of the circuit stage; and a change detector to monitor if the input voltage signal changes during a time interval around the sampling time, and if no change is detected in the input voltage signal during the time interval, the controller is configured to control the analogue processing stage to process the sample.

Claims

1. A baseline restorer circuit, the baseline restorer circuit comprising: a controller; a sample control circuit arranged to receive an input voltage signal that is output from a circuit stage comprising an amplifier, wherein the sample control circuit is configured to capture a sample of the input voltage signal at a sampling time in response to receiving a first control signal from the controller; an analogue processing stage arranged to receive the sample of the input voltage signal and a constant baseline reference voltage and selectively process the sample of the input voltage signal to provide an output voltage; a transconductance stage configured to convert the output voltage to a compensation current and supply the compensation current to an input of the circuit stage; and a change detector configured to monitor if the input voltage signal changes during a time interval around the sampling time, and if no change is detected in the input voltage signal during the time interval, the controller is further configured to transmit a second control signal to the analogue processing stage to control the analogue processing stage to process the sample of the input voltage signal.

2. The baseline restorer circuit of claim 1, wherein the change detector comprises a change detector stage arranged to continuously receive the input voltage signal.

3. The baseline restorer circuit of claim 2, wherein commencement and expiry of the time interval is controlled by the controller transmitting a third control signal to the change detector.

4. The baseline restorer circuit of claim 3, wherein at commencement of the time interval the change detector is configured to capture an instantaneous value of the input voltage signal and is configured to monitor if the input voltage signal changes during the time interval by comparing the input voltage signal to said instantaneous value of the input voltage signal.

5. The baseline restorer circuit of claim 4, wherein the change detector is configured to: determine a voltage difference value based on said comparing; and determine that the input voltage signal has changed during the time interval by at least one of: detecting that the voltage difference value is less than a first negative predetermined threshold voltage; and detecting that the voltage difference value is greater than a second positive predetermined threshold voltage.

6. The baseline restorer circuit of claim 1, wherein the change detector comprises a change detector stage arranged to receive a digital signal output from an energy discriminator, wherein the digital signal is generated by the energy discriminator in dependence on a comparison of a level of the input voltage signal with at least one threshold value, the change detector stage configured to monitor if the input voltage signal changes during a time interval around the sampling time based on the digital signal.

7. The baseline restorer circuit of claim 6, wherein the change detector stage is configured to determine that the input voltage signal has changed during the time interval by detecting a change of state of the digital signal.

8. The baseline restorer circuit of claim 1, wherein the change detector is arranged to supply an output signal to the controller, said output signal indicating whether the input voltage signal has changed during the time interval.

9. The baseline restorer circuit of claim 1, wherein if the change detector detects a change in the input voltage signal during the time interval, the controller is further configured to transmit the second control signal to the analogue processing stage to control the analogue processing stage to discard the sample of the input voltage signal.

10. The baseline restorer circuit of claim 1, further comprising a comparator arranged to receive a sample of the input voltage signal and the constant baseline reference voltage, the comparator configured to: compare the sample of the input voltage signal to the constant baseline reference voltage to determine a differential voltage value; and determine, using the differential voltage value, whether the sample of the input voltage signal is within an acceptable range of the constant baseline reference voltage; and output a fourth control signal to the processor, the fourth control signal indicating whether the sample of the input voltage signal is within the acceptable range of the constant baseline reference voltage, wherein transmission of the second control signal to the analogue processing stage to control the analogue processing stage to process the sample of the input voltage signal is further based on the fourth control signal indicating that the sample of the input voltage signal is within the acceptable range of the constant baseline reference voltage.

11. The baseline restorer circuit of claim 10, wherein the comparator is configured to determine that the sample of the input voltage signal is within an acceptable range of the constant baseline reference voltage by at least one of: detecting that the differential voltage value is greater than a third negative predetermined threshold voltage; and detecting that the differential voltage value is less than a fourth positive predetermined threshold voltage.

12. The baseline restorer circuit of claim 10, wherein if the comparator determines that the sample of the input voltage signal is outside of the acceptable range of the constant baseline reference voltage, the controller is further configured to transmit the second control signal to the analogue processing stage to control the analogue processing stage to discard the sample of the input voltage signal.

13. The baseline restorer circuit of claim 12, wherein the controller is further configured to: count a number of samples of the input voltage signal that are discarded only due to the fourth control signal output by the comparator; and if the counted number of samples exceeds a threshold, enter an operating mode in which the controller processes further samples of the input voltage signal in dependence on only the output signal of the change detector.

14. The baseline restorer circuit of claim 13, wherein the controller is configured to exit said operating mode in response to the fourth control signal indicating that a predetermined number of samples of the input voltage signal are within the acceptable range of the constant baseline reference voltage.

15. The baseline restorer circuit of claim 10, wherein the sample of the input voltage signal received by the comparator is the sample of the input voltage signal captured by the sample control circuit.

16. The baseline restorer circuit of claim 10, wherein the sample of the input voltage signal received by the comparator is captured by a further sample control circuit, the further sample control circuit arranged to receive the input voltage signal that is output from the circuit stage.

17. The baseline restorer circuit of claim 10, wherein the sample control circuit is arranged to receive the constant baseline reference voltage and is configured to capture a sample of the constant baseline reference voltage, wherein the comparator is arranged to receive the sample of the constant baseline reference voltage.

18. The baseline restorer circuit of 16, wherein the further sample control circuit is arranged to receive the constant baseline reference voltage and is configured to capture a sample of the constant baseline reference voltage, wherein the comparator is arranged to receive the sample of the constant baseline reference voltage.

19. (canceled)

20. A photon counting circuit, comprising: the baseline restorer circuit according to any preceding claim; a photon detector having a photon sensitive area, the photon detector being configured to generate a current signal in dependence on an impact of a photon on the photon sensitive area; the circuit stage comprising the amplifier, the circuit stage arranged to receive the current signal and provide the input voltage signal in response to the current signal; and an energy discriminator being connected to the front-end electronic circuitry, the energy discriminator being configured to generate a digital signal in dependence on a comparison of a level of the input voltage signal with at least one threshold value.

21. A device for medical diagnostics, comprising a photon counting circuitry of claim 20, wherein the device is configured as an X-ray apparatus or a computed tomography scanner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles disclosed herein. Some embodiments of the disclosure will now be described by way of example only and with reference to the accompanying drawings, in which:

[0050] FIG. 1 illustrates a photon counting circuit including a baseline restorer circuit;

[0051] FIG. 2 is an example timing diagram for the photon counting circuit shown in FIG. 1;

[0052] FIG. 3 illustrates a baseline restorer circuit according to an embodiment of the present disclosure;

[0053] FIG. 4 illustrates a photon counting circuit including the baseline restorer circuit shown in FIG. 3;

[0054] FIG. 5 shows example timing diagrams for the baseline restorer circuit shown in FIG. 3;

[0055] FIG. 6 shows an example implementation of a change detector using in the baseline restorer circuit shown in FIG. 3;

[0056] FIG. 7 shows another example implementation of a change detector using in the baseline restorer circuit shown in FIG. 3;

[0057] FIG. 8 illustrates a photon counting circuit including a baseline restorer circuit that monitors information from a pulse discriminator of the photon counting circuit; and

[0058] FIG. 9 is a schematic block diagram of a device for medical diagnostics.

DETAILED DESCRIPTION

[0059] Specific embodiments will now be described with reference to the drawings.

[0060] Reference is first made to FIG. 3 which illustrates a baseline restorer circuit 300 according to one embodiment of the present disclosure.

[0061] As shown in FIG. 3, the baseline restorer circuit 300 comprises a sample-and-hold stage 302 (otherwise referred to herein as a sample control circuit), a change detector stage 314, a controller 324, an analogue processing stage 326, and a transconductance stage 328. The baseline restorer circuit 300 may also comprise a comparator 312.

[0062] One example implementation of the sample-and-hold stage 302 is shown in FIG. 3. As shown, the sample-and-hold stage 302 is arranged to receive an input voltage signal V.sub.sha that is output from a front-end circuit stage 104 of a photon counting circuit.

[0063] The sample-and-hold stage 302 is configured to capture a sample of the input voltage signal V.sub.sha at a sampling time in response to receiving a control signal (sh) from the controller 324. As shown in FIG. 3, this may be implemented by a switch 308 that is controllable in dependence on the control signal (sh), and a capacitor 310. In particular, when the control signal (sh) is low (e.g. logic 0) the switch 308 is controlled to be open, and when the control signal (sh) is high (e.g. logic 1) the switch 308 is controlled to be closed. When the switch 308 transitions from being closed to open, the sample-and-hold stage 302 captures (e.g. freezes, memorizes) a sample of the input voltage signal V.sub.sha. The sample-and-hold stage 302 is arranged to supply a captured sample of the input voltage signal V.sub.sha to the analogue processing stage 326.

[0064] The sample-and-hold stage 302 may also be arranged to receive a desired baseline reference voltage V.sub.bl,ref. The sample-and-hold stage 302 is configured to capture a sample of the desired baseline reference voltage V.sub.bl,ref. As shown in FIG. 3, this may be implemented by a switch 304 that is controllable in dependence on the control signal (sh), and a capacitor 306. In particular, when the control signal (sh) is low (e.g. logic 0) the switch 304 is controlled to be open, and when the control signal (sh) is high (e.g. logic 1) the switch 308 is controlled to be closed. When the switch 304 transitions from being closed to open, the sample-and-hold stage 302 captures (e.g. freezes, memorizes) a sample of the desired baseline reference voltage V.sub.bl,ref. Thus, the sample-and-hold stage 302 may be arranged to supply a captured sample of the desired baseline reference voltage V.sub.bl,ref to the analogue processing stage 326.

[0065] The sample-and-hold stage 302 may be configured to capture a sample of the desired baseline reference voltage V.sub.bl,ref at the same instant as the sampling time of the input voltage signal V.sub.sha. The sampling of the desired baseline reference voltage V.sub.bl,ref does not necessarily need to be at the same instant as the sampling time of the input voltage signal V.sub.sha. For example, the fact that the V.sub.bl,ref is constant and the difference between V.sub.sha and V.sub.bl,ref is of interest, could be exploited by a switched capacitor sampling network that first captures V.sub.bl,ref and then in a second step samples & subtracts V.sub.sha in one go.

[0066] Alternatively, the sample-and-hold stage 302 may not sample the desired baseline reference voltage V.sub.bl,ref and instead the analogue processing stage 326 may receive the desired baseline reference voltage V.sub.bl,ref as a continuous non-sampled input.

[0067] The change detector stage 314 is arranged to receive the input voltage signal V.sub.sha as a continuous non-sampled input.

[0068] In response to receiving a control signal (chen) from the controller 324, the change detector stage 314 is configured to capture an instantaneous value of the input voltage signal V.sub.sha. As shown in FIG. 3, this may be implemented by a switch 316 that is controllable in dependence on the control signal (chen), and a capacitor 318. In particular, when the control signal (chen) is low (e.g. logic 0) the switch 316 is controlled to be closed, and when the control signal (chen) is high (e.g. logic 1) the switch 316 is controlled to be open. When the switch 316 transitions from being closed to open, the change detector stage 314 captures (e.g. freezes, memorizes) a sample of the input voltage signal V.sub.sha.

[0069] The change detector stage 314 is configured to monitor if the input voltage signal V.sub.sha changes during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302. The change detector stage 314 is configured to supply an output signal (chg) to the controller 324, the output signal (chg) indicating whether the input voltage signal V.sub.sha has changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302.

[0070] The change detector stage 314 comprises a comparator 320 which receives the input voltage signal V.sub.sha as a continuous non-sampled input, and the instantaneous value of the input voltage signal V.sub.sha captured by the change detector stage 314. The change detector stage 314 is configured to determine a voltage difference value (x) by determining the difference between the input voltage signal V.sub.sha and the instantaneous value of the input voltage signal V.sub.sha captured by the change detector stage 314.

[0071] The comparator 320 shown in FIG. 3 is a window comparator that is configured to determine whether the voltage difference value (x) is within a voltage range defined by V1?X?V2.

[0072] If the voltage difference value (x) is always within the voltage range defined by the window comparator 320 e.g. that the voltage difference value (x) is greater than a first negative predetermined threshold voltage V1 (e.g. ?20 mV) and is less than a second positive predetermined threshold voltage (e.g. +20 mV), then the change detector stage 314 determines that the input voltage signal V.sub.sha has not changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302. In this scenario, the comparator 320 never flags a change to the memory element 322, which therefore signals no change to the controller 324 by supplying the output signal (chg) having a low (e.g. logic 0) value to the controller 324. The memory element 322 may for example be a flip-flop or an RS latch.

[0073] If the voltage difference value (x) leaves the voltage range defined by the window comparator 320 at least once e.g. that the voltage difference value (x) is less than a first negative predetermined threshold voltage V1 (e.g. ?20 mV) or is greater than a second positive predetermined threshold voltage (e.g. +20 mV), then the change detector stage 314 determines that the input voltage signal V.sub.sha has changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302. In this scenario, the comparator 320 flags a change one or more times to the memory element 322, which therefore trips and signals change to the controller 324 by supplying the output signal (chg) having a high (e.g. logic 1) value to the controller 324.

[0074] Whilst the comparator 320 shown in FIG. 3 is a window comparator, in other implementations the change detector stage 314 comprises a comparator 320 that is sensitive only in one direction.

[0075] The controller 324 is configured to transmit a control signal (exe) to the analogue processing stage 326 to control the analogue processing stage 326 to either discard or process the sample of the input voltage signal V.sub.sha.

[0076] The analogue processing stage 326 processes the sample of the input voltage signal V.sub.sha when the control signal (exe) received from the controller 324 is high (e.g. logic 1).

[0077] The analogue processing stage 326 discards the sample of the input voltage signal V.sub.sha (does not process it) when the control signal (exe) received from the controller 324 is low (e.g. logic 0).

[0078] In embodiments whereby the baseline restorer circuit 300 does not comprise the comparator 312, the value of the control signal (exe) is solely dependent on the output signal (chg) received from the change detector stage 314.

[0079] That is, in response to the controller 324 receiving a low output signal (chg) (e.g. logic 0) indicating that the input voltage signal V.sub.sha has not changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302, the controller 324 is configured to supply the control signal (exe) having a high (e.g. logic 1) value to allow processing of the sample of the input voltage signal V.sub.sha. Similarly, in response to the controller 324 receiving a high output signal (chg) (e.g. logic 1) indicating that the input voltage signal V.sub.sha has changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302, the controller 324 is configured to supply the control signal (exe) having a low (e.g. logic 0) value to discard the sample of the input voltage signal V.sub.sha.

[0080] The analogue processing stage 326 is arranged to receive the sample of the input voltage signal V.sub.sha from the sample-and-hold stage 302. The analogue processing stage 326 is further arranged to receive a sample of the desired baseline reference voltage V.sub.bl,ref from the sample-and-hold stage 302 or may receive the desired baseline reference voltage V.sub.bl,ref as a continuous non-sampled input. The analogue processing stage 326 also receives the control signal (exe) from the controller 324. The analogue processing stage 326 selectively processes the sample of the input voltage signal V.sub.sha to provide an output voltage.

[0081] The analogue processing stage 326 may be an integrator (e.g. a switched capacitor integrator). In operation, the analogue processing stage 326 computes the difference of the desired baseline reference voltage V.sub.bl,ref and the amplifier output V.sub.sha (i.e. the sampled baseline error), weights it by some factor, and adds it to what was already summed up before (if allowed to do so by controller when exe=1). For example, if V.sub.bl,ref=500 mV and V.sub.sha=505 mV (i.e. error is +5 mV) and the voltage already stored in the analogue processing stage 326 was +123 mV and a weighting (gain) of 0.2 is implemented, then the output voltage of the analogue processing stage 326 would change from +123 mV to +124 mV (=+123 mV+0.2*(505 mV-500 mV)) for this period. This way, the resulting compensation current I.sub.blr would move a little bit towards a better compensation, trying to reduce the baseline error. The signs in the regulation loop are relevant: the positive error must cause a change in the direction towards less error (lower V.sub.sha), which can be either by the amplifier (104) having a negative phase as shown FIG. 1, or by the baseline restorer circuit being inverted (not shown in the Figures).

[0082] The transconductance stage 328 is arranged to receive the output voltage from the analogue processing stage 326 and convert the output voltage to a compensation current I.sub.blr. Thus the transconductance stage 328 can be considered as a voltage to current converter. The transconductance stage 328 is arranged to supply the compensation current to an input of a front-end circuit stage 104 of a photon counting circuit e.g. to an an input of the amplifier 106.

[0083] The functionality of the controller 324 described herein may be implemented in code (software) stored on a memory comprising one or more storage media, and arranged for execution on a processor comprising on or more processing units. The code is configured so as when fetched from the memory and executed on the processor to perform operations in line with embodiments discussed below. Alternatively it is not excluded that some or all of the functionality of the controller 324 is implemented in dedicated hardware circuitry, or configurable hardware circuitry like an FPGA.

[0084] As noted above, the baseline restorer circuit 300 may also comprise a comparator 312.

[0085] The comparator 312 is arranged to receive the sample of the input voltage signal V.sub.sha from the sample-and-hold stage 302. The comparator 312 may be further arranged to receive a sample of the desired baseline reference voltage V.sub.bl,ref from the sample-and-hold stage 302 or may receive the desired baseline reference voltage V.sub.bl,ref as a continuous non-sampled input. The comparator 312 is configured to supply an output signal (inw) to the controller 324, the output signal (inw) indicating whether the sample of the input voltage signal V.sub.sha is within an acceptable range of the desired baseline reference voltage V.sub.bl,ref.

[0086] The comparator 312 is configured to determine a differential voltage value (x) by determining the difference between the sample of the input voltage signal V.sub.sha and the desired baseline reference voltage V.sub.bl,ref.

[0087] The comparator 312 shown in FIG. 3 is a window comparator in that it is configured to determine whether the differential voltage value (x) is within a voltage range defined by V3?X?V4.

[0088] If the differential voltage value (x) is within the voltage range defined by the window comparator 312 e.g. that the differential voltage value (x) is greater than a third negative predetermined threshold voltage V3 (e.g. ?5 mV) and is less than a second positive predetermined threshold voltage (e.g. +5 mV), then the window comparator 312 determines that the input voltage signal V.sub.sha is within an acceptable range of the desired baseline reference voltage V.sub.bl,ref. In this scenario, the comparator 312 outputs the output signal (inw) having a high (e.g. logic 1) value to the controller 324.

[0089] If the differential voltage value (x) is outside the voltage range defined by the window comparator 312 e.g. that the differential voltage value (x) is less than the third negative predetermined threshold voltage V3 (e.g. ?5 mV) or is more than a second positive predetermined threshold voltage (e.g. +5 mV), then the window comparator 312 determines that the input voltage signal V.sub.sha is outside of the acceptable range of the desired baseline reference voltage V.sub.bl,ref. In this scenario, the comparator 312 outputs the output signal (inw) having a low (e.g. logic 0) value to the controller 324.

[0090] Whilst the comparator 312 shown in FIG. 3 is a window comparator, in other implementations the comparator 312 is sensitive only in one direction.

[0091] In embodiments whereby the baseline restorer circuit 300 comprises the comparator 312, the value of the control signal (exe) is dependent on both the output signal (chg) received from the change detector stage 314 and the output signal (inw) received from the comparator 312.

[0092] In these embodiments, the controller 324 is configured to supply the control signal (exe) having a high (e.g. logic 1) value to allow processing of the sample of the input voltage signal V.sub.sha only when the controller 324 receives (i) a low output signal (chg) (e.g. logic 0) from the change detector stage 314 indicating that the input voltage signal V.sub.sha has not changed during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302, and (ii) a high output signal (inw) (e.g. logic 1) from the comparator 312.

[0093] In embodiments whereby both the comparator 320 and the comparator 312 are window comparators, V1 &V2 of the comparator 320 may be selected to provide a wider (larger) range than the values of V3&V4 associated with the comparator 312 because it is easier to do an accurate comparison with the sampled window comparator which just receives one constant input to process, while the change detector stage 314 has to quickly react on fast changes of the input voltage signal V.sub.sha which is a more expensive operation. Therefore, for a given overall baseline extraction performance, it may be preferable to have the change detector stage 314 less accurate and the sampled window comparator 312 more accurate.

[0094] Whilst FIG. 3 illustrates a single sample-and-hold stage 302, in other implementations the baseline restorer circuit 300 comprises two sample-and-hold stages operating in parallel. That is a first sample-and-hold stage 302 feeds the analogue processing stage 326 and a further sample-and-hold stage 302 feeds the comparator. The two sample-and-hold stages both receive the control signal (sh) from the controller 324 and thus operate with the same sample of the input voltage signal V.sub.sha. The two sample-and-hold stages can be incorporated into a switched capacitor network which uses the charge stored in the sampling capacitors directly rather than just sensing their voltage through a high impedance input. In such a configuration, the charge is consumed and can only be used by one circuit (either the analogue processing stage 326 or the comparator 312), i.e. using the charge usually resets the capacitor and leaves nothing for a second circuit.

[0095] In the embodiments described herein, the controller 324 may be operable to enter a recovery mode which is activated if a defined number of samples of the input voltage signal V.sub.sha had to be discarded only due to the comparator 312 i.e. inw=0 (while the change detector would have released them). In the recovery mode, the controller 324 is configured to ignore the output signal (inw) of the comparator 312, such that the processing of further samples depends only on the output signal (chg) received from the change detector stage 314. This way, a large but constant V.sub.sha error can pass through and is regulated away, allowing the system to recover from an unexpected charge event or at startup. In the recovery mode, the controller 324 continues to receive the digital signal inw from the comparator 312, even though it does not use it to decide if a sample has to be discarded during recovery mode. The controller 324 is configured to exit the recovery mode if the comparator 312 reports a low baseline error again. That is, when operating in the recovery mode the controller 324 uses the output signal (inw) of the comparator 312 to observe if the samples have returned to within the target error range, for example by waiting for a predetermined number of samples in a row which fall into the target error range, indicated by the output signal (inw) having a high (e.g. logic 1) value from the comparator 312.

[0096] FIG. 4 illustrates using the baseline restorer circuit 300 in a photon counting circuit 100.

[0097] Referring to FIG. 4, the photon counting circuit 100 comprises a photon detector 102 having a photon sensitive area. The photon detector 102 is configured to generate a current signal I.sub.det in dependence on an impact of a photon on the photon sensitive area. The photon counting circuit 100 comprises a front-end circuit stage 104 to receive the current signal I.sub.det from the photon detector 102 and to provide the voltage signal V.sub.sha (the baseline signal V.sub.bl+?V) in response to the current signal. The front-end circuit stage 104 comprises a charge sensitive amplifier (CSA) 106. The inverting input of the CSA 106 receives the current signal I.sub.det. A feedback capacitor 110 may be connected between the inverting input of the CSA 106 and the output of the CSA 106. A feedback resistor 108 may be connected between the inverting input of the CSA 106 and the output of the CSA 106. The front-end circuit stage 104 senses charge at its input and shapes a voltage at its output to produce bell-shaped pulses. The front-end circuit stage 104 may comprise an inverting current buffer stage (not shown), to receive the I.sub.det current signal and feed into the amplifier 106.

[0098] The photon counting circuit 100 comprises an energy discriminator 112 being connected to the front-end circuit stage 104. In particular, the front-end circuit stage 104 provides the voltage signal V.sub.sha to the energy discriminator 112.

[0099] The energy discriminator 112 is configured to generate a digital signal in dependence on a comparison of a level of the voltage signal V.sub.sha with at least one threshold value Vth1, . . . , Vthn. In particular, the energy discriminator 112 may comprise several comparators 114,118 with different thresholds Vth1, . . . , VthN?1, VthN. The output signals of the comparators 114,118 are then individually counted by counters 116,120. It will be appreciated that the energy discriminator 112 may comprise any number of comparators (each with an associated counter).

[0100] As shown in FIG. 4, the baseline restorer circuit 300 receives the voltage signal V.sub.sha that is output from the front-end circuit stage 104. The baseline restorer circuit 300 may receive the voltage signal V.sub.sha directly from the CSA 106. The baseline restorer circuit 300 may receive the voltage signal V.sub.sha indirectly from the CSA 106. That is, after being output by the CSA 106, the voltage signal V.sub.sha may pass through one or more further components of the front-end circuit stage 104 (not shown in FIG. 4) e.g. a shaping amplifier stage, before being supplied to the baseline restorer circuit 300.

[0101] As shown in FIG. 4, the transconductance stage 328 is arranged to supply the compensation current I.sub.blr to an input of the front-end circuit stage 104. As shown in FIG. 4, the output of the transconductance stage 328 is coupled to the inverting input of the CSA 106.

[0102] The photon counting circuit 100 may be used for various photon counting applications, especially those which require low noise intensity measurements and possibly also spectral information. This includes medical imaging, spectroscopy, security scanners, computed tomography, etc.

[0103] FIG. 5 shows three example timing diagrams to illustrate the operation of the baseline restorer circuit 300 shown in FIG. 3. In FIG. 5, the time t.sub.1 corresponds to when the change detector stage 314 captures (freezes, memorizes) the instantaneous value of the voltage signal V.sub.sha in response to receiving the control signal (chen) from the controller 324, and starts to compare the continuous (non-sampled) input voltage signal V.sub.sha against this reference. The time t.sub.2 corresponds to the point in time when the sample-and-hold stage 302 captures a sample of the input voltage signal V.sub.sha (sampling instant) in response to receiving the control signal (sh) from the controller 324, and the window comparator 312 starts to process it. The time t.sub.3 corresponds to the end of the sensing period of the change detector stage 314. At time t.sub.4 the result of the window comparator 312 is ready. The time t.sub.5 corresponds to when the controller 324 is ready to flag to the analogue processing stage 326 if it can use the sample of the voltage signal V.sub.sha. The time t.sub.6 corresponds to the end of the sampling trial and the controller 324 is ready for the next sampling trial. A sampling trial corresponds to the time between the time t.sub.1 and the time t.sub.6, in that it comprises the capturing of a sample of the voltage signal V.sub.sha, along with all the associated checks performed by the change detector stage 314 and comparator 312 for that sample.

[0104] Thus the interval between time t.sub.1 and time t.sub.2 corresponds to the monitoring period of the change detector stage 314 before the sample-and-hold stage 302 captures a sample of the input voltage signal V.sub.sha. The interval between time t.sub.2 and time t.sub.3 corresponds to the monitoring period of the change detector stage 314 after the sample-and-hold stage 302 captures the sample of the input voltage signal V.sub.sha. The interval between time t.sub.2 and time t.sub.4 corresponds to the decision time of the window comparator 312. The interval between time t.sub.4 and time t.sub.5 corresponds to the time the controller 324 takes to compute the final decision. The interval between time t.sub.5 and time t.sub.6 corresponds to the time the analogue processing stage 326 takes to use (usually integrate) the current sample of the input voltage signal V.sub.sha from the sample-and-hold stage 302.

[0105] FIG. 5 shows a first example of the sample-and-hold stage 302 sampling an input voltage signal V.sub.sha500 (left-side waveform).In the first example, the sample-and-hold stage 302 samples right into a pulse at the input voltage signal V.sub.sha 500. Both the window comparator 312 and the change detector stage 314 recognize the pulse (inw stays low, chg goes high), and as a result the controller 324 discards the sample (exe stays low).

[0106] FIG. 5 shows a second example of the sample-and-hold stage 302 sampling an input voltage signal V.sub.sha 502 (central waveform). In the second example, no pulse is present around the sampling instant of the sample-and-hold stage 302. The window comparator 312 flags this by setting inw=1 after its decision time at time t.sub.4, and the change detector stage 314 keeps the output signal (chg) low. As a result, the controller 324 brings the control signal (exe) high to allow processing of the sample.

[0107] FIG. 5 shows a third example of the sample-and-hold stage 302 sampling an input voltage signal V.sub.sha504 (right-side waveform). In the third example, a pulse is occurring just after the sampling instant of the sample-and-hold stage 302, causing the sample-and-hold stage 302 to sample the onset of the pulse. The window comparator 312 does not recognize this small error (inw goes high), but the change detector stage 314 successfully recognizes the pulse, causing the controller 324 to discard the sample (exe stays low).

[0108] FIG. 6 shows a variant of the change detector stage 314, which has a different switch/capacitor configuration than the one shown in FIG. 3. In particular, the change detector stage 314 shown in FIG. 6 has the capacitor 318 at the input of the switch 316 so that it is arranged to continuously receive the input voltage signal V.sub.sha. The change detector stage 314 shown in FIG. 6 follows the same operation as the change detector stage 314 shown in FIG. 3. In particular, as soon as the control signal chen (change detector enable) from the controller 324 goes high, the coarse window comparator 320 inside of the change detector monitors the input voltage signal V.sub.sha for changes compared to the voltage at the chen rising edge instant. Any such change in either direction during the monitoring period (chen=1 period) is memorized in the memory element 322. The AC coupling provided by the capacitor advantageously allows the further circuitry of the change detector stage 314 to operate at a different DC level than the input voltage signal V.sub.sha.

[0109] FIG. 7 shows a variant of the change detector stage 314 which uses the input capacitor 318 to also perform an auto-zero (AZ) operation of a gain stage comprised of a transistor 704 and a current source 702, to reduce offset in front of the coarse window comparator 320. The gain stage reduces the accuracy requirements of the coarse window comparator 320 by providing it with an amplified signal. The window comparator 320 is configured to derive a voltage difference x between its input voltage at the instant of switch 316 opening (chen rising edge) and its input voltage throughout the monitoring period (chen high), and compare this voltage difference against the thresholds V1 and V2. FIG. 7 also shows how a memory element 322 (e.g. a D-flipflop) can be used to memorize a detected change during the monitoring period: at the beginning of the monitoring period (chen rising edge) the D-flipflop 322 is initialized to a low state using its clock input and D input. Afterwards, a high signal at its set input is changing the state to high, and leaves it there. This way, even a short violation of the window comparator's thresholds is captured and memorized in the D-flipflop 322.

[0110] Whilst the comparator 320 in the change detector of FIGS. 6 and 7 may be a window comparator, in other implementations these change detector stages may comprises a comparator 320 that is sensitive only in one direction.

[0111] The change detector stage 314 described above performs dedicated monitoring of the input voltage signal V.sub.sha. Additionally or alternatively, a change detector stage 802 shown in FIG. 8 may be used to check for changes in the input voltage signal V.sub.sha. That is, in embodiments of the present disclosure a change detector comprises one or both of the change detector stage 314 and the change detector stage 802.

[0112] The change detector stage 802 is illustrated in FIG. 8.

[0113] As shown in FIG. 8, the change detector stage 802 is arranged to receive a digital signal output from each of the comparators 114,118 of the energy discriminator 112 of the photon counting circuit 100, wherein each digital signal is generated by the energy discriminator 112 in dependence on a comparison of a level of the input voltage signal V.sub.sha with a threshold value. The change detector stage 802 is configured to monitor if the input voltage signal V.sub.sha changes during a time interval around the sampling time of the input voltage signal V.sub.sha performed by the sample-and-hold stage 302 based on the digital signal(s) received from the comparators 114,118.

[0114] If, during the monitoring period of the change detector stage 802 (corresponding to the time interval between t.sub.1 and t.sub.3 in FIG. 5), any of the pulse discriminator comparators changes state, then the change detector stage 802 considers this as a change of V.sub.sha detected condition and the change detector stage 802 supplies the output signal (chg) having a high (e.g. logic 1) value to the controller 324.

[0115] In the embodiments described above, to increasing the chance of finding a genuine baseline sample the baseline restorer circuit 300 can be replicated multiple times per detector pixel in order to increase the frequency of sampling the input voltage signal V.sub.sha. That is, the same baseline restorer circuit can be replicated and driven with staggered time phases to perform staggered sensing (e.g. half the sampling trial time period apart from each other) of the input voltage signal V.sub.sha.

[0116] In the embodiments described above, the sample repetition may be controlled by a clock signal to get a defined BLR loop regulation speed. That is, the controller 324 may be configured to control the baseline restorer circuit 300 to perform a predetermined number of sampling trials (e.g. 10) with one clock cycle. In these implementations, the controller 324 may be configured to transmit the control signal (exe) to the analogue processing stage 326 to control the analogue processing stage 326 to process a first valid sample of the input voltage signal V.sub.sha within the clock cycle but then deliberately ignores later valid samples within the same clock cycle. Thus the analogue processing stage 326 does not process every valid sample of the input voltage signal V.sub.sha within the clock cycle.

[0117] In the embodiments described above, the sampling may be re-triggered early with the aim of increasing the chance of finding a genuine baseline sample by sampling more often. In particular, as soon as the change detector finds a change indicated by the output signal (chg) having a high (e.g. logic 1) value, the controller 324 may be configured to not wait for the complete sampling trial to end and instead immediately commence a new sampling trial. That is, instead of waiting & executing until time t6, a detected violation could cause the controller 324 to fast-forward to the next t.sub.1 (with a time period where chen=0 in between, to reset the change detector).

[0118] FIG. 9 shows an example of an application where a photon counting circuit 100 comprising the baseline restorer circuit 300 according to an embodiment described herein is provided in a device 900 for medical diagnostics. The device 900 may be configured, for example, as an X-ray apparatus or a computed tomography scanner.

[0119] Although the disclosure has been described in terms of embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiments, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

LIST OF REFERENCE NUMERALS

[0120] 100 photon counting circuit [0121] 102 photon detector [0122] 104 front-end circuit stage [0123] 106 charge sensitive amplifier [0124] 108 feedback resistor [0125] 110 feedback capacitor [0126] 112 energy discriminator [0127] 114 comparator [0128] 116 counter [0129] 118 comparator [0130] 120 counter [0131] 122 baseline restorer circuit [0132] 200 curve of detector current I.sub.det [0133] 250 curve of output voltage V.sub.sha of the front-end circuit stage [0134] 300 baseline restorer circuit [0135] 302 sample-and-hold stage [0136] 304 switch [0137] 306 capacitor [0138] 308 switch [0139] 310 capacitor [0140] 312 comparator [0141] 314 change detector stage [0142] 316 switch [0143] 318 capacitor [0144] 320 comparator [0145] 322 memory element [0146] 324 controller [0147] 326 analogue processing stage [0148] 328 transconductance stage [0149] 500 voltage signal V.sub.sha [0150] 502 voltage signal V.sub.sha [0151] 504 voltage signal V.sub.sha [0152] 702 DC current source [0153] 704 switch [0154] 706 inverter [0155] 802 change detector stage [0156] 900 device