ANALOG-TO-DIGITAL CONVERTER, ADC, CIRCUIT AND A METHOD FOR CONTROLLING SAID ADC CIRCUIT

Abstract

A method for predictive level-crossing, LC, in an analog-to-digital converter, ADC, is provided. The method comprises the steps of comparing a first input signal sampled during a first sampling period with one of an upper threshold level and a lower threshold level to determine if a level crossing has occurred during said first sampling period. Which one of said two threshold levels that is compared with said first input signal is based on if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of the two threshold levels was compared to a prior input signal sampled during said prior sampling period.

Claims

1. A method for predictive level-crossing, LC, in an analog-to-digital converter, ADC, comprising the steps of: comparing a first input signal, V.sub.in, sampled during a first sampling period, T.sub.1,2,3,4, with one of an upper threshold level, V.sub.up, and a lower threshold level, V.sub.low, to determine if a level crossing has occurred during said first sampling period, and wherein which one of said two threshold levels that is compared with said first input signal is based on: if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of the two threshold levels was compared to a prior input signal sampled during said prior sampling period.

2. The method according to claim 1, wherein if a level crossing did not occur during the prior sampling period in which one of the two threshold levels was compared to the prior input signal, then the other of the two threshold levels is compared with said first input signal during said first sampling period.

3. The method according to claim 1, wherein if a level crossing did occur during the prior sampling period in which one of the two threshold levels was compared to the prior input signal, then the same one of the two threshold levels is compared with said first input signal during said first sampling period.

4. The method according to claim 1, further comprising the steps of: in response to a level crossing occurring during said first sampling period, adjusting said two threshold levels.

5. The method according to claim 4, wherein adjusting the one of said two threshold levels comprises increasing said two threshold levels if the upper threshold level was crossed or decreasing said two threshold levels if the lower threshold level was crossed.

6. The method according to claim 1, wherein a level crossing occurring comprises an input signal being greater than an upper threshold level or being lesser than a lower threshold level.

7. The method according to claim 1, further comprising the steps of: in response to determining that a level crossing occurred during said first sampling period: outputting (120) one or more signals indicating said level crossing and which one of said two threshold levels that was compared with said first input signal.

8. An analog-to-digital converter, ADC, circuit comprising: at least one threshold level comparator configured to: compare an input signal, V.sub.in, with an upper threshold level, V.sub.up, to determine if an up level crossing has occurred, and compare an input signal, V.sub.in, with a lower threshold level, V.sub.low, to determine if a down level crossing has occurred; and wherein the ADC circuit is configured to: compare a first input signal sampled during a first sampling period with one of said two threshold levels and determine if a level crossing has occurred during said first sampling period; wherein the ADC circuit is further configured to determine which one of said two threshold levels that is compared with said first input signal based on: if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of said two threshold levels was compared to a prior input signal sampled during said prior sampling period.

9. The ADC circuit according to claim 8, wherein if a level crossing did not occur during the prior sampling period in which one of the two threshold levels was compared to the prior input signal, then the other of the two threshold levels is compared during said first sampling period.

10. The ADC circuit according to claim 8, wherein if a level crossing did occur during the prior sampling period in which one of the two threshold levels was compared to the prior input signal, then the same one of the two threshold levels is compared during said first sampling period.

11. The ADC circuit according to claim 8, wherein the ADC circuit is further configured to: in response to a level crossing occurring during said first sampling period, adjusting said two threshold levels.

12. The ADC circuit according to claim 11, wherein adjusting said two threshold level comprises increasing said two threshold levels if the upper threshold level was crossed or decreasing said two threshold levels if the lower threshold level was crossed.

13. The ADC circuit according to claim 8, wherein the ADC circuit is further configured to: in response to determining that a level crossing occurred during said first sampling period: output one or more signals indicating said level crossing and which one of said two threshold level comparators was that used during said first sampling period.

14. The ADC circuit according to claim 8, further comprising a digital-to-analog converter, DAC, configured to generate the upper threshold level and the lower threshold level for the at least one threshold level comparator.

15. The ADC circuit according to claim 8, wherein the at least one threshold level comparator comprises: an upper threshold level comparator configured to: compare the input signal with the upper threshold level to determine if an up level crossing has occurred; and a lower threshold level comparator configured to: compare the input signal with the lower threshold level to determine if a down level crossing has occurred.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above, as well as additional objects, features and advantages of the present disclosure, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0027] FIG. 1 is a schematic view of an ADC circuitry according to an exemplary embodiment of the present disclosure.

[0028] FIG. 2 is a flow-chart of a method according to an exemplary embodiment of the present disclosure.

[0029] FIG. 3 is a graph showing steps of a method according to an exemplary embodiment according to an aspect of the present disclosure.

[0030] Unless explicitly stated to the contrary, the drawings show only such elements that are necessary to illustrate the example embodiments, while other elements, in the interest of clarity, may be omitted or merely suggested. As illustrated in the figures, the sizes of elements and regions may be exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures of the embodiments.

DETAILED DESCRIPTION

[0031] FIG. 1 illustrates an ADC circuitry 1 according to an exemplary embodiment of the present disclosure.

[0032] The ADC circuitry 1 shown in FIG. 1 comprises two threshold level comparators 2a, 2b. Each comparator 2a, 2b is configured to receive two analog signals and determine which of the two received analog signals is greater. Based on the determination, the comparators 2a, 2b are configured to output a signal indicating said determination. The ADC circuitry 1 further comprises logic circuitry 3 configured to receive the signal(s) from the comparators 2a, 2b.

[0033] The ADC circuitry 1 may further comprise sample-and-hold circuitry 5 configured to sample and hold a signal. The sample-and-hold circuitry 5 may be configured to input the sampled and held signal, i.e. an input signal V.sub.in to the comparator(s) 2a, 2b of the ADC circuitry 1. The sample-and-hold circuitry 5 may be configured to operate at sampling frequency, and may thereby input an input signal V.sub.in to the comparator(s) 2a, 2b until a new input signal V.sub.in is sampled and input to the comparator(s) 2a, 2b, wherein the time between samplings may be a sampling period.

[0034] The ADC circuitry 1 may further comprise at least one DAC 4a, 4b configured to generate analog signals based on a received digital signal. The ADC circuitry 1 is shown in FIG. 1 to comprise 2 DACs 4a, 4b. One of the DACs 4a may be configured to generate an upper threshold level V.sub.up which may be input to a comparator 2a, and the other DAC 4b may be configured to generate a lower threshold level V.sub.low which may be input to a comparator 2b. The threshold levels V.sub.up, V.sub.low may be understood as analog signals. The DAC(s) 4a, 4b may be configured to generate the threshold levels V.sub.up, V.sub.low based on a received digital signal received from the logic circuitry 3.

[0035] It is to be understood that the present disclosure is not limited to comprising two comparators 2a, 2b, and may alternatively, comprise, for example one comparator. Further, the present disclosure is not limited to comprising two DACs 4a, 4b, and may alternatively, comprise, for example, one DAC. For example, the ADC circuitry 1 may comprise one comparator and switches configured to allow the input signal V.sub.in to be connected to either input of the single comparator. Further, the ADC circuitry 1 may comprise one single DAC which may be configured to generate both threshold levels V.sub.up, V.sub.low, and the ADC circuitry 1 may comprise switches configured to allow either threshold level V.sub.up, V.sub.low to be input to either input of the comparator(s).

[0036] The ADC circuitry 1 is configured to determine which one of said two threshold levels V.sub.up, V.sub.low that is compared with the input signal V.sub.in during a current sampling period based on if a level crossing occurred during a prior sampling period directly prior to the current sampling period, and which one of said two threshold levels V.sub.up, V.sub.low was compared to a prior input signal sampled during said prior sampling period. The determination may be done by the logic circuitry 3. The ADC circuitry 1 may be configured to keep track of which threshold levels V.sub.up, V.sub.low that has been used in prior comparisons, and the ADC circuitry 1 may be configured to keep track of if a level crossing occurred.

[0037] The logic circuitry 3 is shown as outputting two signals EVENT, DIR. A first of the signals may be understood as an event signal EVENT, and a second signal of the signal may be understood as a direction signal DIR. For example, the logic circuitry 3 may be configured to output a logic one via the event signal EVENT when a level crossing has occurred. Further, the logic circuitry 3 may, for example, output a logic one when the upper threshold level V.sub.up was the most previously crossed threshold level, and may, for example output a logical zero when the lower threshold level V.sub.low was the most previously crossed threshold level. Such an example of the event signal EVENT and the direction signal DIR could be used to digitally recreate (an approximation of) the sampled input signal. However, it is to be understood that the present disclosure is not limited to outputting binary signals in this manner, and may use other methods of digitally representing the (approximation of) the sampled input signal.

[0038] FIG. 2 is flow-chart of a method 100 according to an exemplary embodiment according to an aspect of the present disclosure.

[0039] The method 100 shown in FIG. 2 comprises the steps of comparing 110 a first input signal (not shown; see e.g. FIG. 1 or 3) sampled during a first sampling period (not shown; see e.g. FIG. 1 or 3) with one of an upper threshold level (not shown; see e.g. FIG. 1 or 3) and a lower threshold level (not shown; see e.g. FIG. 1 or 3)to determine if a level crossing has occurred during said first sampling period. Which one of said two threshold levels that is compared with said first input signal is based on if a level crossing occurred during a prior sampling period directly prior to the first sampling period, and which one of the two threshold levels was compared to a prior input signal sampled during said prior sampling period.

[0040] The method 100 may comprise, in response to a determination 110 that a level crossing has occurred during said first sampling period, adjusting 115 said two threshold levels.

[0041] The method 100 may further comprise, in response to determining that a level crossing occurred during said first sampling period, outputting 120 one or more signals (not shown; see e.g. FIG. 1) indicating said level crossing and which one of said two threshold levels that was compared with said first input signal.

[0042] FIG. 3 is a graph showing steps of a method 100 according to an exemplary embodiment according to an aspect of the present disclosure.

[0043] The graph shown in FIG. 3 is plotted with along the horizontal axis, and amplitude along the vertical axis.

[0044] An input signal V.sub.in is shown in the chart as a thick solid line. The input signal V.sub.in may be understood as being measured by a sensor, or other type of measuring device, and is subsequently input to an ADC circuitry (not shown; see e.g. FIG. 1) according to a first aspect of the present disclosure. However, it is to be understood that the actual input signal V.sub.in which is input to the may be sampled at an amplitude and then held at said amplitude until a subsequent sample is made. However, in order to provide an increased clarity and understanding, such a sampled-and-held signal is not displayed. Instead, sampling periods T.sub.1-4 are indicated in FIG. 3 by vertical dashed lines (which are also thinner than the thick solid line indicated the input signal V.sub.in). The sampled value, or amplitude, of the input signal V.sub.in during a given sampling period may be understood as being equal to the amplitude where the input signal V.sub.in and a corresponding vertical line cross each other.

[0045] FIG. 3 further comprises a plurality of horizontal dashed lines. Some of the horizontal dashed lines has one end which comprises a filled circular shape, and they represent a lower threshold level V.sub.low. The remaining horizontal dashed lines has one end which comprises a filled triangular shape, and they represent an upper threshold level V.sub.up.

[0046] For first sampling period T.sub.1 the lower threshold level V.sub.low is being compared with the input signal V.sub.in. Further, during the sampling period prior to the first sampling period T.sub.1 the upper threshold level V.sub.up was being compared to the input signal V.sub.in. Therefore, in accordance the method 100 according to the present disclosure, during the second sampling period T.sub.2, which is directly subsequent, or following, the first sampling period T.sub.1, the other threshold level, i.e. the upper threshold level V.sub.up, is being used compare with the input signal V.sub.in.

[0047] During the second sampling period T.sub.2 the input signal crosse the upper threshold level V.sub.up, and therefore, the upper threshold level V.sub.up, is increased once such that the upper threshold level V.sub.up, is greater than the input signal V.sub.in.

[0048] Consequently, during a third sampling period T.sub.3, the input signal V.sub.in is being compared with the upper threshold level V.sub.up, i.e. the same threshold level, as it occur a level-crossing during the prior sampling period, i.e. the second sampling period T.sub.2.

[0049] FIG. 3 further shows that during a fourth sampling period T.sub.4, which is after but not directly following the third sampling period T.sub.3, multiple level-crossings occur. Phrased differently, the lower threshold level V.sub.low, needed to be adjusted multiple times before the lower threshold level V.sub.low was lower than the input signal V.sub.in. In can further be seen that each adjustment of the lower threshold level V.sub.low made during the fourth sampling period T.sub.4 is greater than the one directly preceding it. This may be understood as a first adjustment of the lower threshold level V.sub.low being equal to a LSB, a second adjustment lower threshold level V.sub.low being equal to a second-LSB, and so on. However, the present disclosure is not limited to such an adjustment, and may involve steady-level adjustments or decreasing adjustment steps.

[0050] FIG. 3 clearly shows how the present disclosure allows for tracking of an input signal V.sub.in, by comparing every other threshold level when no level crossings are determined, and by following the input signal V.sub.in when a level crossing does occur, by continuing to compare the threshold level which was crossed during the prior sampling period. Thus, the present disclosure allows for reducing the amount of comparisons by up to 50%, which may greatly reduce the energy consumption of an ADC.

[0051] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the present disclosure.