RECEIVER CIRCUIT, CORRESPONDING ISOLATED DRIVER DEVICE, ELECTRONIC SYSTEM AND METHOD OF DECODING A DIFFERENTIAL SIGNAL INTO A DIGITAL OUTPUT SIGNAL

Abstract

A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.

Claims

1. A device, comprising a receiver circuit, the receiver circuit including: a pair of input nodes configured to receive a differential signal therebetween, the differential signal including spikes of a first polarity and spikes of a second polarity; an output node configured to produce a digital output signal as a function of the differential signal; a first comparator circuit configured to receive the differential signal and to produce an intermediate set signal that includes a pulse at each spike of the differential signal having the first polarity; a second comparator circuit configured to receive the differential signal and to produce an intermediate reset signal that includes a pulse at each spike of the differential signal having the second polarity; a logic circuit configured to receive the intermediate set signal, the intermediate reset signal and the digital output signal, and to generate a corrected set signal and a corrected reset signal; and an output control circuit configured to receive the corrected set signal and the corrected reset signal, and further configured to assert the digital output signal based on the corrected set signal and the corrected reset signal.

2. The device circuit of claim 1, wherein the output circuit is configured to assert the digital output signal in response to a pulse being detected in the corrected set signal and de-assert the digital output signal in response to a pulse being detected in the corrected reset signal.

3. The device of claim 2, wherein the logic circuit is configured to: detect whether the digital output signal switches between a first logic value and a second logic value; detect whether the intermediate reset signal includes a pulse having a duration higher than a certain time interval; produce a set correction signal that includes a pulse when the digital output signal switches between a first logic value and a second logic value and, at the same time, the intermediate reset signal includes a pulse having a duration higher than the certain time interval; produce a corrected set signal that includes the pulses of the intermediate set signal and the pulses of the set correction signal; detect whether the intermediate set signal includes a pulse having a duration higher than the certain time interval; produce a reset correction signal that includes a pulse when the digital output signal switches between a first logic value and a second logic value and, at the same time, the intermediate set signal includes a pulse having a duration higher than the certain time interval; and produce a corrected reset signal that includes the pulses of the intermediate reset signal and the pulses of the reset correction signal.

4. The device of claim 3, wherein the logic circuit includes: a first asymmetric buffer circuit configured to receive the intermediate reset signal and produce a first detection signal by passing the active edges of the intermediate reset signal with a delay equal to the certain time interval and passing the inactive edges of the intermediate reset signal without substantial delay; a first gating logic gate configured to pass the first detection signal when the digital output signal switches between a first logic value and a second logic value, and mask the first detection signal otherwise, to produce the set correction signal; a second asymmetric buffer circuit configured to receive the intermediate set signal and produce a second detection signal by passing the active edges of the intermediate set signal with a delay equal to the certain time interval and passing the inactive edges of the intermediate set signal without substantial delay; and a second gating logic gate configured to pass the second detection signal when the digital output signal switches between a first logic value and a second logic value, and mask the second detection signal otherwise, to produce the reset correction signal.

5. The device of claim 4, wherein the first asymmetric buffer circuit includes: a first inverter circuit including a first pull-up transistor and a first pull-down transistor alternately driven by the intermediate reset signal; a first capacitor coupled in parallel to the first pull-down transistor; and a second inverter circuit coupled to the first inverter circuit to produce the first detection signal; and wherein the second asymmetric buffer circuit includes: a third inverter circuit including a second pull-up transistor and a second pull-down transistor alternately driven by the intermediate set signal; a second capacitor coupled in parallel to the second pull-down transistor; and a fourth inverter circuit coupled to the third inverter circuit to produce the second detection signal.

6. The device of claim 4, wherein the logic circuit includes: a first corrective logic gate configured to pass the pulses of the intermediate set signal and the pulses of the set correction signal to produce the corrected set signal; and a second corrective logic gate configured to pass the pulses of the intermediate reset signal and the pulses of the reset correction signal to produce the corrected reset signal.

7. The device of claim 6, wherein the logic circuit includes an edge detector circuit configured to receive the digital output signal and to produce an edge detection signal that includes a pulse at each commutation of the digital output signal between a first logic value and a second logic value, wherein the edge detector circuit includes: a delay circuit block configured to receive the digital output signal and propagate the digital output signal with a respective delay to produce a delayed digital output signal; and an exclusive-OR gate configured to combine the digital output signal and the delayed digital output signal to produce the edge detection signal, wherein the respective delay is higher than the certain time interval.

8. The device of claim 7, wherein: said intermediate reset signal and the first detection signal are normally high, the active edges of the intermediate reset signal are falling edges, and the inactive edges of the intermediate reset signal are rising edges; said intermediate set signal and the second detection signal are normally high, the active edges of the intermediate set signal are falling edges, and the inactive edges of the intermediate set signal are rising edges; said edge detection signal is normally high and includes a low pulse at each commutation of the digital output signal between a first logic value and a second logic value; said first gating logic gate includes an OR gate configured to apply OR logic processing to the first detection signal and the edge detection signal to produce the set correction signal; said second gating logic gate includes an OR gate configured to apply OR logic processing to the second detection signal and the edge detection signal to produce the reset correction signal; said first corrective logic gate includes an AND gate configured to apply AND logic processing to the set correction signal and the intermediate set signal to produce the corrected set signal; and said second corrective logic gate includes an AND gate configured to apply AND logic processing to the reset correction signal and the intermediate reset signal to produce the corrected reset signal.

9. The device of claim 8, wherein the first gating logic gate is further configured to apply OR logic processing to the intermediate reset signal to produce the set correction signal, and the second gating logic gate is further configured to apply OR logic processing to the intermediate set signal to produce the reset correction signal.

10. The device of claim 3, wherein the output control circuit includes a set-reset flip-flop, the set-reset flip-flop having a clock input terminal driven by the corrected set signal and a reset input terminal driven by the corrected reset signal to produce the digital output signal at a data output terminal of the set-reset flip-flop.

11. The device of claim 3, comprising an amplifier circuit configured to receive the differential signal and pass an amplified replica of the differential signal to the first comparator circuit and to the second comparator circuit.

12. The device of claim 3, comprising a driver circuit that includes a half-bridge circuit, the half-bridge circuit being arranged between a positive supply voltage pin and a reference supply voltage pin and driven by the digital output signal to produce an output switching signal.

13. The device of claim 1, comprising an isolated driver device including: a first semiconductor die including: an input pin configured to receive a digital input signal; a transmitter circuit configured to receive the digital input signal and to produce: a first complementary digital signal that is a replica of the digital input signal at a first output node; and a second complementary digital signal that is a complement of the digital input signal at a second output node; a galvanic isolation barrier including a first isolation capacitor having a first terminal coupled to the first output node of the transmitter circuit and a second isolation capacitor having a first terminal coupled to the second output node of the transmitter circuit, whereby a differential signal is produced between a second terminal of the first isolation capacitor and a second terminal of the second isolation capacitor, the differential signal including a spike of a first polarity at each rising edge of the digital input signal and a spike of a second polarity at each falling edge of the digital input signal; a second semiconductor die including the receiver circuit, wherein a first input node of the receiver circuit is electrically coupled to the second terminal of the first isolation capacitor and a second input node of the receiver circuit is electrically coupled to the second terminal of the second isolation capacitor to receive the differential signal.

14. The device of claim 13, comprising a processing unit configured to generate the digital input signal received by the isolated driver device.

15. A method of decoding a differential signal into a digital output signal, the method comprising: receiving the differential signal; producing an intermediate set signal based on the differential signal; producing an intermediate reset signal based on the differential signal; producing a set correction signal based on the digital output signal and the intermediate reset signal; producing a corrected set signal based on the intermediate set signal and the set correction signal; producing a reset correction signal based on the digital output signal and the intermediate set signal; producing a corrected reset signal based on the intermediate reset signal and the reset correction signal; and producing the digital output signal based on the corrected set signal and corrected reset signal; asserting the digital output signal in response to a pulse being detected in the corrected set signal and de-asserting the digital output signal in response to a pulse being detected in the corrected reset signal.

16. The method of claim 15, wherein the differential signal includes spikes of a first polarity and spikes of a second polarity, the method comprising: producing the intermediate set signal with a pulse at each spike of the differential signal having the first polarity; and producing the intermediate reset signal with a pulse at each spike of the differential signal having the second polarity.

17. The method of claim 16, comprising: detecting whether the digital output signal switches between a first logic value and a second logic value; detecting whether the intermediate reset signal includes a pulse having a duration higher than a certain time interval; producing the set correction signal including a pulse when the digital output signal switches between a first logic value and a second logic value and, at the same time, the intermediate reset signal includes a pulse having a duration higher than the certain time interval; producing the corrected set signal including the pulses of the intermediate set signal and the pulses of the set correction signal; detecting whether the intermediate set signal includes a pulse having a duration higher than the certain time interval; producing the reset correction signal that with a pulse when the digital output signal switches between a first logic value and a second logic value and, at the same time, the intermediate set signal includes a pulse having a duration higher than the certain time interval; producing the corrected reset signal including the pulses of the intermediate reset signal and the pulses of the reset correction signal; and asserting the digital output signal in response to a pulse being detected in the corrected set signal and de-asserting the digital output signal in response to a pulse being detected in the corrected reset signal.

18. A receiver circuit, comprising: a differential input including a first input node and a second input node; a first comparator circuit having an inverting input coupled to the first input node and a non-inverting input coupled to the second input node; a second comparator circuit having an inverting input coupled to the second input node and a non-inverting input coupled to the first input node; a logic circuit having a first input coupled to an output of the first comparator a second input coupled to an output of the second comparator; and a flip-flop having a first input coupled to a first output of the logic circuit, a second input coupled to a second output of the logic circuit, and an output terminal, wherein the logic circuit includes a third input coupled to the output of the flip-flop.

19. The receiver circuit of claim 18, wherein the logic circuit includes: a first inverter; a second inverter; a first OR gate including a first input coupled to the first input of the logic circuit, a second input coupled to the third input of the logic circuit, and a third input coupled to an output of the first inverter; and a second OR gate including a first input coupled to the second input of the logic circuit, a second input coupled to the third input of the logic circuit, and a third input coupled to an output of the second inverter.

20. The receiver circuit of claim 19, wherein the logic circuit includes: a first AND gate have a first input coupled to an output of the first OR gate, a second input coupled to the second input of the logic circuit, and an output corresponding to the first output of the logic circuit; and a second AND gate have a first input coupled to an output of the second OR gate, a second input coupled to the first input of the logic circuit, and an output corresponding to the second output of the logic circuit.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0048] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0049] FIGS. 1 to 7 have already been described in the foregoing;

[0050] FIG. 8 is a time diagram including waveforms exemplary of signals in a conventional receiver circuit, e.g., for use in an isolated communication channel of a driver device;

[0051] FIG. 9 is a circuit block diagram exemplary of a receiver circuit according to one or more embodiments of the present description, e.g., for use in an isolated communication channel of a driver device;

[0052] FIG. 10 is a circuit block diagram exemplary of a gate-level implementation of a portion of the receiver circuit of FIG. 9, according to one or more embodiments of the present description; and

[0053] FIG. 11 is a time diagram including waveforms exemplary of signals in the receiver circuit of FIG. 9, according to one or more embodiments of the present description.

DETAILED DESCRIPTION

[0054] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0055] Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0056] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0057] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.

[0058] One or more embodiments relate to a receiver circuit that is configured to reject the spurious pulses SP produced in the set and reset signals COMP.sub.N and COMP.sub.P due to unwanted oscillations of the differential signal Vd (e.g., ringing effects caused by common-mode voltage transients applied at the input of the receiver circuit) to improve the common-mode transient immunity (CMTI). By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIG. 8, which is a time diagram including waveforms exemplary of signals in a conventional receiver circuit 104 (substantially reproducing the contents of FIG. 7). Here, it is shown that the pulses FP of the set and reset signals COMP.sub.N, COMP.sub.P that are functional for the correct operation (e.g., correct signal decoding) of the set-reset flip-flop 46 (e.g., the pulses generated at the edges of the clock signal CLK and at the edges of the input signal PWM.sub.IN) generally have a duration T.sub.r that is in a certain range (e.g., between 1 ns and 2 ns), while the spurious pulses SP of the set and reset signals COMP.sub.N, COMP.sub.P due to common-mode transients and ringing effects have a longer duration T.sub.s, i.e., a duration that exceeds the maximum duration of pulses FP (e.g., higher than 2 ns, for instance around 10 ns). Therefore, one or more embodiments rely on an improved receiver architecture, which includes a logic circuit configured to correct the value of the output signal PWM.sub.RX produced by the flip-flop 46 by generating corrected set and reset signals if the following conditions are satisfied: [0059] i) the duration of the pulses produced at the output of comparators 42 and 44 (i.e., the pulses of signals COMP.sub.N and COMP.sub.P) is higher than a certain threshold, with the value of the threshold being higher than the maximum duration T.sub.r allowed for a functional pulse FP (indicating that the pulse is indeed a spurious one); and [0060] ii) a commutation of the output signal PWM.sub.RX is detected (indicating that the spurious pulse has indeed to be corrected, insofar as it would otherwise force the output signal PWM.sub.RX to a wrong value).

[0061] One or more embodiments may thus relate to a receiver circuit 104 as exemplified in the circuit block diagram of FIG. 9, where parts or elements similar to those described with reference to the previous Figures are indicated by the same or similar reference numbers, and a corresponding description is not repeated for brevity. In particular, the receiver circuit 104 includes a logic circuit 90 arranged between the output terminals of the comparators 42, 44 and the input terminals of the set-reset flip-flop 46. The logic circuit 90 receives the original set and reset signals COMP.sub.N, COMP.sub.P, which are possibly affected by spurious pulses, as well as the reconstructed PWM signal PWM.sub.RX produced by the flip-flop 46. The logic circuit 90 is configured to produce the corrected set and reset signals COMP.sub.N, COMP.sub.P, which are propagated to the flip-flop 46 (with signal COMP.sub.N possibly complemented, just like previously described with reference to FIG. 3) and result in a reconstructed PWM signal PWM.sub.RX that may not be free from spurious pulses but is suitable to correctly drive the output switching stage 105, HS, LS so that the output PWM signal PWM.sub.OUT is free from spurious pulses, as further discussed in the following. In particular, one or more embodiments rely on the fact that signal PWM.sub.RX may include spurious pulses, but the duration of such spurious pulses is reduced to a value lower than the propagation delay T.sub.delay of the output switching stage, so that those pulses may not affect the value of the output PWM signal PWM.sub.OUT.

[0062] In particular, the logic circuit 90 is configured to: [0063] detect the presence of spurious pulses in the signals COMP.sub.N, COMP.sub.P based on the duration of the pulses (e.g., selecting only those pulses longer than a threshold T.sub.count, where T.sub.count is selected to be longer than the maximum duration T.sub.r of a functional pulse); [0064] discard the spurious pulses that would not negatively affect the value of the reconstructed PWM signal PWM.sub.RX (e.g., in the examples considered herein, discard the spurious pulses of signal COMP.sub.N that take place while signal PWM.sub.IN has a high logic value, and the spurious pulses of signal COMP.sub.P that take place while signal PWM.sub.IN has a low logic value); and [0065] in response to a spurious pulse being detected in one of signals COMP.sub.N, COMP.sub.P and not being discarded, producing a corrective pulse in the other one of signals COMP.sub.N, COMP.sub.P thereby producing the corrected set and reset signals COMP.sub.N, COMP.sub.P so as to force the reconstructed PWM signal PWM.sub.RX back to its correct value within a time period T.sub.count shorter than the propagation delay T.sub.delay of the output switching stage, so that the value of the output PWM signal PWM.sub.OUT does not switch to an incorrect value.

[0066] FIG. 10 is a circuit block diagram exemplary of a possible gate-level implementation of a logic circuit 90, and FIG. 11 is a time diagram including waveforms exemplary of signals in the receiver circuit 104, which illustrates possible operation of the receiver circuit.

[0067] The logic circuit 90 includes a first asymmetric buffer 91.sub.P configured to receive the original reset signal COMP.sub.P and produce a first detection signal COMP.sub.P,DLY. Signal COMP.sub.P,DLY substantially corresponds to a replica of signal COMP.sub.P where the active edges of the signal (e.g., the falling edges in the examples considered herein, where the reset signal COMP.sub.P is normally high) are delayed by an interval T.sub.count higher than the expected duration T.sub.r of the functional pulses FP. As a result, as exemplified in FIG. 11, signal COMP.sub.P,DLY is indicative of the spurious pulses SP of the reset signal COMP.sub.P, insofar as the pulses having a duration higher than T.sub.count are propagated with a delayed active (e.g., falling) edge and an almost unaffected inactive (e.g., rising) edge, and the pulses having a duration lower than T.sub.count are not propagated from signal COMP.sub.P to signal COMP.sub.P,DLY (e.g., signal COMP.sub.P,DLY remains at a high logic level during those pulses). In particular, in one or more embodiments, the first asymmetric buffer 91.sub.P may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between a logic supply voltage V.sub.DD and a logic reference voltage V.sub.SS, and driven by signal COMP.sub.P. A capacitor is coupled in parallel to the conductive channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V.sub.SS) to delay the active (e.g., falling) edges. The inactive (e.g., rising) edges are kept fast to discharge the capacitors and make the buffer ready for the next detection action. A second inverter circuit is coupled to the output of the first inverter circuit, and thereby produces signal COMP.sub.P,DLY with the features discussed above.

[0068] Similarly, the logic circuit 90 includes a second asymmetric buffer 91.sub.N configured to receive the original set signal COMP.sub.N and produce a second detection signal COMP.sub.N,DLY. Signal COMP.sub.N,DLY substantially corresponds to a replica of signal COMP.sub.N where the active edges of the signal (e.g., the falling edges in the examples considered herein, where the set signal COMP.sub.N is normally high) are delayed by interval T.sub.count. As a result, as exemplified in FIG. 11, signal COMP.sub.N,DLY is indicative of the spurious pulses SP of the set signal COMP.sub.N, insofar as the pulses having a duration higher than T.sub.count are propagated with a delayed active (e.g., falling) edge and an almost unaffected inactive (e.g., rising) edge, and the pulses having a duration lower than T.sub.count are not propagated from signal COMP.sub.N to signal COMP.sub.N,DLY (e.g., signal COMP.sub.N,DLYremains at a high logic level during those pulses). In particular, in one or more embodiments, the second asymmetric buffer 91.sub.N may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between the logic supply voltage V.sub.DD and the logic reference voltage V.sub.SS, and driven by signal COMP.sub.N. A capacitor is coupled in parallel to the conductive channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V.sub.SS) to delay the active (e.g., falling) edges. The inactive (e.g., rising) edges are kept fast to discharge the capacitors and make the buffer ready for the next detection action. A second inverter circuit is coupled to the output of the first inverter circuit, and thereby produces signal COMP.sub.N,DLY with the features discussed above.

[0069] Further, the logic circuit 90 includes an edge detector circuit 92 coupled to the output of flip-flop 46 and configured to produce an edge detection signal ED that is indicative of the transitions (e.g., edges) of the reconstructed PWM signal PWM.sub.RX, as exemplified in FIG. 11. In particular, the edge detection signal ED may be normally high and may include a low pulse at each occurrence of a transition (e.g., edge) of signal PWM.sub.RX. The duration TED of such low pulse may be longer than T.sub.count. In particular, in one or more embodiments, the edge detector circuit 92 may include a delay circuit block configured to produce a replica of signal PWM.sub.RX delayed by an interval T.sub.ED, an XOR logic gate configured to apply XOR logic processing to signal PWM.sub.RX and its delayed replica, and an inverter circuit coupled to the output of the XOR logic gate to produce the edge detection signal ED with the features discussed above.

[0070] Further, the logic circuit 90 includes a first gating logic gate 93.sub.P configured to combine the first detection signal COMP.sub.P,DLY and the edge detection signal ED to discard the spurious pulses of signal COMP.sub.P,DLY that do not correspond to a transition of the reconstructed PWM signal PWM.sub.RX, thereby producing a set correction signal set.sub.new that is indicative of a corrective action having to be implemented in the original set signal COMP.sub.N to produce the corrected set signal COMP.sub.N. In particular, the set correction signal set.sub.new may be normally high and may include a low pulse when both signals COMP.sub.P,DLY and ED have a low pulse. Therefore, in one or more embodiments the first gating logic gate may include an OR gate 93.sub.P configured to apply OR logic processing to signals COMP.sub.P,DLY and ED to produce signal set.sub.new.

[0071] Similarly, the logic circuit 90 includes a second gating logic gate 93.sub.N configured to combine the second detection signal COMP.sub.N,DLY and the edge detection signal ED to discard the spurious pulses of signal COMP.sub.N,DLY that do not correspond to a transition of the reconstructed PWM signal PWM.sub.RX, thereby producing a reset correction signal reset.sub.new that is indicative of a corrective action having to be implemented in the original reset signal COMP.sub.P to produce the corrected reset signal COMP.sub.P. In particular, the reset correction signal reset.sub.new may be normally high and may include a low pulse when both signals COMP.sub.N,DLY and ED have a low pulse. Therefore, in one or more embodiments the second gating logic gate may include an OR gate 93.sub.N configured to apply OR logic processing to signals COMP.sub.N,DLY and ED to produce signal reset.sub.new.

[0072] Further, the logic circuit 90 includes a first corrective logic gate 94.sub.P configured to combine the set correction signal set new and the original set signal COMP.sub.N to add to signal COMP.sub.N the corrective pulses that are intended to restore the correct value of signal PWM.sub.RX following a spurious reset pulse, thereby producing the corrected set signal COMP.sub.N. In particular, the corrected set signal COMP.sub.N may be normally high and may include low pulses corresponding to the pulses of signals COMP.sub.N and set.sub.new. Therefore, in one or more embodiments the first corrective logic gate 94.sub.P may include an AND gate 94.sub.P configured to apply AND logic processing to signals COMP.sub.N and set.sub.new to produce signal COMP.sub.N.

[0073] Similarly, the logic circuit 90 includes a second corrective logic gate 94.sub.N configured to combine the reset correction signal reset.sub.new and the original reset signal COMP.sub.P to add to signal COMP.sub.P the corrective pulses that are intended to restore the correct value of signal PWM.sub.RX following a spurious set pulse, thereby producing the corrected reset signal COMP.sub.P. In particular, the corrected reset signal COMP.sub.P may be normally high and may include low pulses corresponding to the pulses of signals COMP.sub.P and reset.sub.new. Therefore, in one or more embodiments the second corrective logic gate 94.sub.N may include an AND gate 94.sub.N configured to apply AND logic processing to signals COMP.sub.P and reset.sub.new to produce signal COMP.sub.P.

[0074] As exemplified in FIG. 10, the corrected signals COMP.sub.N and COMP.sub.P are then used as the set and reset signals of the set-reset (S-R) flip-flop 46 of receiver 104, as described with reference to FIG. 3. Thus, flip-flop 46 receives signal COMP.sub.N (possibly complemented by an inverter stage) at its clock input terminal CP and signal COMP.sub.P at its reset input terminal C.sub.D to produce the reconstructed PWM signal PWM.sub.RX.

[0075] Optionally, the first gating logic gate 93.sub.P may be further configured to receive signal COMP.sub.P and combine it with signals COMP.sub.P,DLY and ED so that the inactive (e.g., rising) edges of signal COMP.sub.P are quickly propagated to the set correction signal set.sub.new. Indeed, it has been previously discussed that the asymmetric buffer 91.sub.P is configured to delay substantially (e.g., by an interval T.sub.count) the active (e.g., falling) edges of signal COMP.sub.P while passing without substantial delay the inactive (e.g., rising) edges. However, if signal COMP.sub.P are not directly propagated to gate 93.sub.P, the inactive edges are propagated via the two cascaded inverter circuits of the asymmetric buffer 91.sub.P. By directly propagating signal COMP.sub.P to gate 93.sub.P, instead, the propagation delay of the asymmetric buffer 91.sub.P can be avoided for the inactive edges. Therefore, in one or more embodiments the first gating logic gate may include an OR gate 93.sub.P configured to apply OR logic processing to signals COMP.sub.P,DLY, COMP.sub.P and ED to produce signal set.sub.new. Similarly, the second gating logic gate 93.sub.N may be optionally further configured to receive signal COMP.sub.N and combine it with signals COMP.sub.N,DLY and ED so that the inactive (e.g., rising) edges of signal COMP.sub.N are quickly propagated to the reset correction signal reset.sub.new. Therefore, in one or more embodiments the second gating logic gate may include an OR gate 93.sub.N configured to apply OR logic processing to signals COMP.sub.N,DLY, COMP.sub.N and ED to produce signal reset.sub.new.

[0076] FIG. 11 is a time diagram including waveforms exemplary of signals in the receiver circuit 104 of FIG. 10, which illustrates possible operation of the receiver circuit. Here it is shown, by way of example, that a spurious pulse SP1 of signal COMP.sub.P forces the reconstructed signal PWM.sub.RX to a low logic value (while signal PWM.sub.RX is expected to stay at a high logic value, copying signal PWM.sub.IN). The spurious pulse SP1 is detected, due to its duration being longer than T.sub.count, by signal COMP.sub.P,DLY which switches to a low logic value. In the meanwhile, also the edge detection signal ED switches to a low logic value since signal PWM.sub.RX has switched due to the spurious pulse. Since signal COMP.sub.P,DLY indicates the presence of a spurious reset pulse and signal ED indicates that signal PWM.sub.RX has changed its state, a corrective set pulse CP1 is generated in signal set.sub.new and propagated to the corrected set signal COMP.sub.N, so that the flip-flop 46 is set again and signal PWM.sub.RX switches again to its previous (correct) state. Signal PWM.sub.RX maintains the wrong value just for an interval T.sub.count that is quite lower than the propagation delay T.sub.delay of the pre-driver circuit 105, so that the output PWM.sub.OUT of the pre-driver circuit has no time to switch and is not affected. Furthermore, thanks to the gating action of signal ED, no corrective reset pulses are generated even when a spurious pulse SP2 of signal COMP.sub.N is detected (see signal reset.sub.new that maintains a high logic value even during SP2), since in this case signal PWM.sub.RX already has the correct value and the spurious pulse SP2 does not corrupt it.

[0077] One or more embodiments may thus prove advantageous insofar as they provide a receiver circuit having an advanced grade of robustness against common-mode noises by using (only) logic circuitry added in the decoding circuit to correct spurious signals generated by ringing. Thus, one or more embodiments rely on a simple implementation (e.g., just including additional logic gates compared to the conventional solutions), which is compatible with the conventional transmitter/receiver architectures.

[0078] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0079] The extent of protection is determined by the annexed claims.

[0080] A receiver circuit (104), may be summarized as including: a pair of input nodes configured to receive a differential signal (Vd) therebetween, the differential signal (Vd) including spikes of a first polarity and spikes of a second polarity; an output node configured to produce a digital output signal (PWM.sub.RX) as a function of said differential signal (Vd); a first comparator circuit (42) configured to receive said differential signal (Vd) and to produce an intermediate set signal (COMP.sub.N) that includes a pulse at each spike of said differential signal (Vd) having said first polarity; a second comparator circuit (44) configured to receive said differential signal (Vd) and to produce an intermediate reset signal (COMP.sub.P) that includes a pulse at each spike of said differential signal (Vd) having said second polarity; a logic circuit (90) configured to receive said intermediate set signal (COMP.sub.N), said intermediate reset signal (COMP.sub.P) and said digital output signal (PWM.sub.RX), and further configured to: detect (92, ED) whether said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value; detect (91.sub.P, COMP.sub.P,DLY) whether said intermediate reset signal (COMP.sub.P) includes a pulse (SP1, SP3) having a duration higher than a certain time interval (T.sub.count); produce (93.sub.P) a set correction signal (set.sub.new) that includes a pulse when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value and, at the same time, said intermediate reset signal (COMP.sub.P) includes a pulse (SP1, SP3) having a duration higher than said certain time interval (T.sub.count); produce (94.sub.P) a corrected set signal (COMP.sub.N) that includes the pulses of said intermediate set signal (COMP.sub.N) and the pulses of said set correction signal (set.sub.new); detect (91.sub.N, COMP.sub.N,DLY) whether said intermediate set signal (COMP.sub.N) includes a pulse (SP2) having a duration higher than said certain time interval (T.sub.count); produce (93.sub.N) a reset correction signal (reset.sub.new) that includes a pulse when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value and, at the same time, said intermediate set signal (COMP.sub.N) includes a pulse (SP2) having a duration higher than said certain time interval (T.sub.count); and produce (94.sub.N) a corrected reset signal (COMP.sub.P) that includes the pulses of said intermediate reset signal (COMP.sub.P) and the pulses of said reset correction signal (reset.sub.new); and an output control circuit (46) configured to receive said corrected set signal (COMP.sub.N) and said corrected reset signal (COMP.sub.P), and further configured to assert said digital output signal (PWM.sub.RX) in response to a pulse being detected in said corrected set signal (COMP.sub.N) and de-assert said digital output signal (PWM.sub.RX) in response to a pulse being detected in said corrected reset signal (COMP.sub.P).

[0081] Said logic circuit (90) may include: a first asymmetric buffer circuit (91.sub.P) configured to receive said intermediate reset signal (COMP.sub.P) and produce a first detection signal (COMP.sub.P,DLY) by passing the active edges of said intermediate reset signal (COMP.sub.P) with a delay equal to said certain time interval (T.sub.count) and passing the inactive edges of said intermediate reset signal (COMP.sub.P) without substantial delay; a first gating logic gate (93.sub.P) configured to pass said first detection signal (COMP.sub.P,DLY) when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value, and mask said first detection signal (COMP.sub.P,DLY) otherwise, to produce said set correction signal (set.sub.new); a second asymmetric buffer circuit (91.sub.N) configured to receive said intermediate set signal (COMP.sub.N) and produce a second detection signal (COMP.sub.N,DLY) by passing the active edges of said intermediate set signal (COMP.sub.N) with a delay equal to said certain time interval (T.sub.count) and passing the inactive edges of said intermediate set signal (COMP.sub.N) without substantial delay; and a second gating logic gate (93.sub.N) configured to pass said second detection signal (COMP.sub.N,DLY) when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value, and mask said second detection signal (COMP.sub.N,DLY) otherwise, to produce said reset correction signal (reset.sub.new).

[0082] Said first asymmetric buffer circuit (91.sub.P) may include: a first inverter circuit including a first pull-up transistor and a first pull-down transistor alternately driven by said intermediate reset signal (COMP.sub.P); a first capacitor coupled in parallel to said first pull-down transistor; and a second inverter circuit coupled to said first inverter circuit to produce said first detection signal (COMP.sub.P,DLY); and wherein said second asymmetric buffer circuit (91.sub.N) may include: a third inverter circuit including a second pull-up transistor and a second pull-down transistor alternately driven by said intermediate set signal (COMP.sub.N); a second capacitor coupled in parallel to said second pull-down transistor; and a fourth inverter circuit coupled to said third inverter circuit to produce said second detection signal (COMP.sub.N,DLY).

[0083] Said logic circuit (90) may include: a first corrective logic gate (94.sub.P) configured to pass the pulses of said intermediate set signal (COMP.sub.N) and the pulses of said set correction signal (set.sub.new) to produce said corrected set signal (COMP.sub.N); and a second corrective logic gate (94.sub.N) configured to pass the pulses of said intermediate reset signal (COMP.sub.P) and the pulses of said reset correction signal (reset.sub.new) to produce said corrected reset signal (COMP.sub.P).

[0084] Said logic circuit (90) may include an edge detector circuit (92) configured to receive said digital output signal (PWM.sub.RX) and to produce an edge detection signal (ED) that includes a pulse at each commutation of said digital output signal (PWM.sub.RX) between a first logic value and a second logic value, wherein the edge detector circuit (92) may include: a delay circuit block configured to receive said digital output signal (PWM.sub.RX) and propagate said digital output signal (PWM.sub.RX) with a respective delay (T.sub.ED) to produce a delayed digital output signal; and an exclusive- OR gate configured to combine the digital output signal (PWM.sub.RX) and the delayed digital output signal to produce said edge detection signal (ED), wherein said respective delay (T.sub.ED) may be higher than said certain time interval (T.sub.count).

[0085] Said intermediate reset signal (COMP.sub.P) and said first detection signal (COMP.sub.P,DLY) may be normally high, the active edges of said intermediate reset signal (COMP.sub.P) may be falling edges, and the inactive edges of said intermediate reset signal (COMP.sub.P) may be rising edges; said intermediate set signal (COMP.sub.N) and said second detection signal (COMP.sub.N,DLY) may be normally high, the active edges of said intermediate set signal (COMP.sub.N) may be falling edges, and the inactive edges of said intermediate set signal (COMP.sub.N) may be rising edges; said edge detection signal (ED) may be normally high and includes low pulses pulse at each commutation of said digital output signal (PWM.sub.RX) between a first logic value and a second logic value; said first gating logic gate (93.sub.P) may include an OR gate configured to apply OR logic processing to said first detection signal (COMP.sub.P,DLY) and said edge detection signal (ED) to produce said set correction signal (set.sub.new); said second gating logic gate (93.sub.N) may include an OR gate configured to apply OR logic processing to said second detection signal (COMP.sub.N,DLY) and said edge detection signal (ED) to produce said reset correction signal (reset.sub.new); said first corrective logic gate (94.sub.P) may include an AND gate configured to apply AND logic processing to said set correction signal (set.sub.new) and said intermediate set signal (COMP.sub.N) to produce said corrected set signal (COMP.sub.N); and said second corrective logic gate (94.sub.N) may include an AND gate configured to apply AND logic processing to said reset correction signal (reset.sub.new) and said intermediate reset signal (COMP.sub.P) to produce said corrected reset signal (COMP.sub.P).

[0086] Said first gating logic gate (93.sub.P) may be further configured to apply OR logic processing to said intermediate reset signal (COMP.sub.P) to produce said set correction signal (set.sub.new), and said second gating logic gate (93.sub.N) may be further configured to apply OR logic processing to said intermediate set signal (COMP.sub.N) to produce said reset correction signal (reset.sub.new).

[0087] Said output control circuit may include a set-reset flip-flop (46), the set-reset flip-flop (46) having a clock input terminal (CP) driven by said corrected set signal (COMP.sub.N) and a reset input terminal (C.sub.D) driven by said corrected reset signal (COMP.sub.P) to produce said digital output signal (PWM.sub.RX) at a data output terminal (Q) of the set-reset flip-flop (46).

[0088] The receiver circuit (104) may include an amplifier circuit (40) configured to receive said differential signal (Vd) and pass an amplified replica of said differential signal (Vd) to said first comparator circuit (42) and to said second comparator circuit (44).

[0089] The receiver circuit (104) may include a driver circuit that includes a half-bridge circuit, the half-bridge circuit being arranged between a positive supply voltage pin (VH) and a reference supply voltage pin (VL) and driven by said digital output signal (PWM.sub.RX) to produce an output switching signal (PWM.sub.OUT).

[0090] An isolated driver device (10), may be summarized as including a first semiconductor die (10a) and a second semiconductor die (10b), wherein the first semiconductor die (10a) including: an input pin (101) configured to receive a digital input signal (PWM.sub.IN); a transmitter circuit (102) configured to receive said digital input signal (PWM.sub.IN) and to produce a pair of complementary digital signals (OUT.sub.P, OUT.sub.N), wherein a first one (OUT.sub.P) of said complementary digital signals is a replica of said digital input signal (PWM.sub.IN) and is produced at a first output node of said transmitter circuit (102), and a second one (OUT.sub.N) of said complementary digital signals is the complement of said digital input signal (PWM.sub.IN) and is produced at a second output node of said transmitter circuit (102); and a galvanic isolation barrier including a first isolation capacitor (103P) having a first terminal coupled to the first output node of said transmitter circuit (102) and a second isolation capacitor (103N) having a first terminal coupled to the second output node of said transmitter circuit (102), whereby a differential signal (Vd) is produced between a second terminal of said first isolation capacitor (103P) and a second terminal of said second isolation capacitor (103N), the differential signal (Vd) including a spike of a first polarity at each rising edge of said digital input signal (PWM.sub.IN) and a spike of a second polarity at each falling edge of said digital input signal (PWM.sub.IN); wherein the second semiconductor die (10b) includes a receiver circuit (104) according to any of the previous claims; and wherein a first input node of the receiver circuit (104) is electrically coupled to the second terminal of said first isolation capacitor (103P) and a second input node of the receiver circuit (104) is electrically coupled to the second terminal of said second isolation capacitor (103P) to receive said differential signal (Vd).

[0091] An electronic system may be summarized as including a processing unit and an isolated driver device (10), the processing unit being configured to generate said digital input signal (PWM.sub.IN) received by the isolated driver device (10).

[0092] A method of decoding a differential signal (Vd) into a digital output signal (PWM.sub.RX), the method may be summarized as including: receiving a differential signal (Vd) that includes spikes of a first polarity and spikes of a second polarity; producing an intermediate set signal (COMP.sub.N) that includes a pulse at each spike of said differential signal (Vd) having said first polarity; producing an intermediate reset signal (COMP.sub.P) that includes a pulse at each spike of said differential signal (Vd) having said second polarity; detecting (92, ED) whether said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value; detecting (91.sub.P, COMP.sub.P,DLY) whether said intermediate reset signal (COMP.sub.P) includes a pulse (SP1, SP3) having a duration higher than a certain time interval (T.sub.count); producing (93.sub.P) a set correction signal (set.sub.new) that includes a pulse when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value and, at the same time, said intermediate reset signal (COMP.sub.P) includes a pulse (SP1, SP3) having a duration higher than said certain time interval (T.sub.count); producing (94.sub.P) a corrected set signal (COMP.sub.N) that includes the pulses of said intermediate set signal (COMP.sub.N) and the pulses of said set correction signal (set.sub.new); detecting (91.sub.N, COMP.sub.N,DLY) whether said intermediate set signal (COMP.sub.N) includes a pulse (SP2) having a duration higher than said certain time interval (T.sub.count); producing (93.sub.N) a reset correction signal (reset.sub.new) that includes a pulse when said digital output signal (PWM.sub.RX) switches between a first logic value and a second logic value and, at the same time, said intermediate set signal (COMP.sub.N) includes a pulse (SP2) having a duration higher than said certain time interval (T.sub.count); producing (94.sub.N) a corrected reset signal (COMP.sub.P) that includes the pulses of said intermediate reset signal (COMP.sub.P) and the pulses of said reset correction signal (reset.sub.new); and asserting said digital output signal (PWM.sub.RX) in response to a pulse being detected in said corrected set signal (COMP.sub.N) and de-asserting said digital output signal (PWM.sub.RX) in response to a pulse being detected in said corrected reset signal (COMP.sub.P).

[0093] These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.