ALTERNATING ASYMMETRICAL PHASE-SHIFT MODULATION

Abstract

In order to balance the thermal stress of the switches (S1-S4) of the two legs of an inverter full bridge (4), the driving signals are generated using an up-down counter having a modulation period T.sub.mod of twice the period T of the input voltage (Vin). The up-down counter has a first compare value (41) of D/4 and a second compare value (42) of (2+D)/4, where D is the duty cycle and where the second half bridge is phase shifted by the period T.

Claims

1. A method for controlling a converter comprising an inverter full bridge with a first input terminal, a second input terminal, a first half bridge and a second half bridge connected across the first and second input terminals, wherein a input voltage having a period T is provided between the first and second input terminals, wherein each half bridge comprises a first switch and a second switch connected in series between the first and second input terminals, comprising: generating drive signals for the switches with a pulse width modulation technique with a duty cycle D using an up-down counter having a period T.sub.mod being twice the period T, a first compare value and a second compare value, switching the first switch of the first half bridge ON at the first compare value on an up-count of the up-down counter, switching the first switch of the first half bridge OFF at the second compare value on an up-count of the up-down counter, switching the first switch of the first half bridge ON at the second compare value on a down-count of the up-down counter, switching the first switch of the first half bridge OFF at the first compare value on the down-count of the up-down counter, switching a second switch of the first half bridge interleaved to the first switch of the first half bridge, wherein the first compare value for the first half bridge is D/4 and wherein the second compare value for the first half bridge is (2+D)/4.

2. The method according to claim 1, comprising switching the first switch and the second switch of the second half bridge in the same way as the first and the second switch of the first half bridge, wherein the first compare value for the second half bridge is (1−D/4) and wherein the second compare value for the second half bridge is (1−(2+D)/4).

3. The method according to claim 1, wherein the up-down counter is ramped up from a minimum value to a maximum value during a first half of the modulator period T.sub.mod and then is ramped down from the maximum value to the minimum value during a second half of the modulator period T.sub.mod, wherein the minimum value is zero and the maximum value is 1.

4. The method according to claim 2, wherein the up-down counter is ramped up from a minimum value to a maximum value during a first half of the modulator period T.sub.mod and then is ramped down from the maximum value to the minimum value during a second half of the modulator period T.sub.mod, wherein the minimum value is zero and the maximum value is 1.

5. A converter comprising an inverter full bridge with a first input terminal, a second input terminal, a first half bridge and a second half bridge connected across the first and second input terminals, wherein each half bridge comprises a first switch and a second switch connected in series between the first and second input terminals, a drive signal generator for generating drive signals for the switches with a pulse width modulation technique with a duty cycle D, wherein the drive signal generator comprises an up-down counter having a first compare value, a second compare value and a period T.sub.mod being twice a period T of an input voltage for providing between the first and second input terminals, wherein the drive signal generator is adapted for generating drive signals for the switches according to claim 1.

6. The converter according to claim 5, further comprising a transformer, a converter stage connected between the inverter full bridge and a primary side of the transformer, a rectifier connected to a secondary side of the transformer and an output stage connected to the rectifier, wherein an output power of the converter is provided across an output of the output stage.

7. The converter according to claim 6, wherein the converter stage comprises an LLC resonant tank.

8. The converter according to claim 6, wherein the converter stage comprises a series inductor and a magnetizing inductor, wherein the series inductor is connected in series between the inverter full bridge and the transformer and the magnetizing inductor is connected in parallel to the transformer.

9. The converter according to claim 6, wherein the rectifier comprises a synchronous rectifier.

10. The converter according to claim 7, wherein the rectifier comprises a synchronous rectifier.

11. The converter according to claim 8, wherein the rectifier comprises a synchronous rectifier.

12. The converter according to claim 9, wherein the synchronous rectifier comprises a first controllable rectifier switch connected to a first output terminal of the transformer, a second controllable rectifier switch connected to a second output terminal of the transformer, wherein both controllable rectifier switches are connected to a first output terminal of the rectifier and wherein the secondary of the transformer comprises a center-tap connected to a second output terminal of the rectifier.

13. The converter according to claim 6, wherein the rectifier comprises a diode full bridge rectifier.

14. The converter according to claim 7, wherein the rectifier comprises a diode full bridge rectifier.

15. The converter according to claim 8, wherein the rectifier comprises a diode full bridge rectifier.

16. The converter according to claim 6, wherein the output stage comprises an output filter with a capacitor connected between output terminals of the rectifier.

17. The converter according to claim 7, wherein the output stage comprises an output filter with a capacitor connected between output terminals of the rectifier.

18. The converter according to claim 8, wherein the output stage comprises an output filter with a capacitor connected between output terminals of the rectifier.

19. The converter according to claim 6, wherein the switches of the inverter full bridge comprises a MOSFET.

20. The converter according to claim 7, wherein the switches of the inverter full bridge comprises a MOSFET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings used to explain the embodiments show:

[0044] FIG. 1 a schematic circuit diagram of a phase-shifted full-bridge converter as known in the art;

[0045] FIG. 2, portion a) a switching scheme for the phase-shifted full-bridge converter as shown in FIG. 1 according to the prior art;

[0046] FIG. 2, portion b) the resulting voltage and current of the inverter full bridge using the switching scheme shown in FIG. 2, portion a);

[0047] FIG. 3 a schematic circuit diagram of an LLC converter according to the disclosure;

[0048] FIG. 4 a schematic circuit diagram of a phase-shifted full-bridge converter according to the disclosure;

[0049] FIG. 5 the switching scheme according to the disclosure and the resulting voltage and current of the inverter full bridge.

[0050] In the figures, the same components are given the same reference symbols.

PREFERRED EMBODIMENTS

[0051] FIG. 1 shows a schematic circuit diagram of a phase-shifted full-bridge converter 1 as known in the art. An input voltage Vin is connected across a first input terminal 2 and a second input terminal 3. The phase-shifted full-bridge converter 1 further includes an inverter full bridge 4, a phase-shifted full bridge 5 including a series inductor Ls in series and a magnetizing inductor Lm in parallel with the primary of a transformer 6 having a center-tapped secondary, a rectifier 7 and an output stage 8.

[0052] The inverter full bridge 4 includes two half-bridges connected between the input terminals 2, 3 and each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3 and the second half-bridge includes switches S2 and S4. The common terminal of switches S1, S3 is connected to the series inductor Ls and the common terminal of switches S2, S4 is connected to second terminal of the phase-shifted full bridge 5. The rectifier includes two synchronous rectifiers S5, S6, each connected to one of the output terminals of the transformer 6 and the other terminals of both synchronous rectifiers S5, S6 is connected to a first output terminal 12 of the output stage 8. The secondary of the transformer 6 includes a center-tap 18 that is connected to a second output terminal 13 of the output stage 8. The output stage includes an output capacitor Cout and the output voltage Vout is provided across the output terminals 12, 13.

[0053] FIG. 2, portion a) shows a switching scheme for the phase-shifted full-bridge converter as shown in FIG. 1. In the embodiment shown in FIG. 1-FIG. 2, the switches S1 and S3 are for example operated as the leading leg and the lagging leg switches are switches S2 and S4. In another embodiment, however, the switches S2 and S4 may be operated as the leading leg and the lagging leg switches are switches S1 and S3.

[0054] In phase-shift modulation both half legs of the inverter are operated with a duty cycle of about 50% where the modulation is phase-shifted for one leg to adjust the voltage transfer ratio. This modulation results in freewheeling intervals 20 in which both high-side switches S1 and S2 or both low-side switches S3 and S4 are conducting. The freewheeling intervals 20 are marked by the dashed areas.

[0055] The dead times of the switching scheme are not shown explicitly in the figures but just schematically in that the switch-on times are slightly delayed compared to the switch-off times of the switches.

[0056] FIG. 2, portion b shows the resulting output voltage V.sub.AB and output current i.sub.LS of the inverter full bridge using the switching scheme shown in FIG. 2, portion a).

[0057] As shown in FIG. 2, portion b, the leading leg switches S1, S3 are turned ON at the current i.sub.P2 and they are also switched OFF at the current i.sub.P2. The lagging lag switches S2, S4 are turned ON at the current i.sub.P3 and they are also turned OFF at that current i.sub.P3 where the absolute value of the current i.sub.P2 is significantly larger than the absolute value of the current i.sub.P3. In this 15 connection it is to note the currents i.sub.P2 and i.sub.P3 may be positive or negative but the absolute value is the same.

[0058] Accordingly, the switching scheme as shown in FIG. 2, portion a) has the disadvantage that the leading half bridge is always stressed with larger switching losses than the lagging leg. The switches S1, S3 of the leading leg are turned-off at a larger current whereas the switches S2, S4 of the lagging leg are turned-off at a substantially lower current. This lower turn-off current of the lagging leg may, furthermore, prevent ZVS for the leading leg adding to the switching losses, particularly in light load situations. The energy of the series inductor Ls may not be large enough to ensure ZVS for the lagging leg resulting in increased turn-on losses for the leading leg.

[0059] The freewheeling interval is entered when the leading leg switches S1, S3 are turned-off. During this interval the transformer current reduces such that the lagging leg switches S2, S4 are turned-off at the end of the freewheeling interval with significantly lower currents.

[0060] The larger switching losses result in a thermal imbalance of the switches of the leading leg and the lagging leg. The temperature of the switches of the leading leg is always larger.

[0061] FIG. 3 shows a schematic circuit diagram of an LLC converter 31 according to the disclosure, i. e. for applying the switching scheme according to the disclosure as shown in FIG. 5.

[0062] An input Voltage Vin is connected across a first input terminal 2 and a second input terminal 3. The LLC converter 31 further includes an inverter full bridge 4, a LLC resonant tank 35, a transformer 6 having a center-tapped secondary, a rectifier 7 and an output stage 8. The LLC resonant tank 35 includes a resonant inductor Lr, a magnetizing inductor Lm and a resonant capacitor Cr. The resonant inductor Lr and the resonant capacitor Cr are connected in series and the magnetizing inductor Lm is connected in parallel with the primary of a transformer 6.

[0063] The inverter full bridge 4 includes two half-bridges connected between the input terminals 2, 3 and each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3 and the second half-bridge includes switches S2 and S4. The common terminal of switches S1, S3 is connected to the resonant inductor Lr and the common terminal of switches S2, S4 is connected to the resonant capacitor Cr. The rectifier includes two synchronous rectifiers S5, S6, each connected to one of the output terminals of the transformer 6 and the other terminals of both synchronous rectifiers S5, S6 is connected to a first output terminal 12 of the output stage 8. The secondary of the transformer 6 includes a center-tap 18 that is connected to a second output terminal 13 of the output stage 8. The output stage includes an output capacitor Cout and the output voltage Vout is provided across the output terminals 12, 13.

[0064] The switches S1-S4 are for example implemented using silicon carbide MOSFETs, silicon MOSFETs or gallium nitride MOSFETs. Other types of MOSFETs or more generally, other types of transistors may however be used as well. The best choice for the implementation of the switches depends on the particular application.

[0065] FIG. 4 shows a schematic circuit diagram of a phase-shifted full-bridge converter 41 according to the disclosure, i. e. for applying the switching scheme according to the disclosure as shown in FIG. 5.

[0066] An input Voltage Vin is connected across a first input terminal 2 and a second input terminal 3. The phase-shifted full-bridge converter 1 further includes an inverter full bridge 4, a phase-shifted full bridge 5 including a series inductor Ls in series and a magnetizing inductor Lm in parallel with the primary of a transformer 6, a rectifier 7 and an output stage 8.

[0067] The inverter full bridge 4 includes two half-bridges connected between the input terminals 2, 3 and each half-bridge having two switches connected in series. The first half-bridge includes switches S1 and S3 and the second half-bridge includes switches S2 and S4. The common terminal of switches S1, S3 is connected to the series inductor Ls and the common terminal of switches S2, S4 is connected to second terminal of the phase-shifted full bridge 5. The rectifier includes four diodes D1, D2, D3, D4 connected in a full bridge configuration across the secondary of the transformer 6. The common terminal of the diodes D1 and D2 is connected to a first output terminal 12 of the output stage 8 and the common terminal of the diodes D3 and D4 is connected to a second output terminal 13 of the output stage 8. The output stage includes an output capacitor Cout and the output voltage Vout is provided across the output terminals 12, 13.

[0068] Again, the switches S1-S4 are for example implemented using silicon carbide MOSFETs or silicon MOSFETs. Other types of MOSFETs or more generally, other types of transistors may however be used as well. The best choice for the implementation of the switches depends on the particular application.

[0069] FIG. 5 shows the switching scheme according to the disclosure which may be applied to the phase-shifted full-bridge converter 1 as shown in FIG. 1 including a center tapped synchronous rectifier, to the LLC converter 31 as shown in FIG. 3 including a center tapped synchronous rectifier as well as the phase-shifted full-bridge converter 41 as shown in FIG. 4 including a diode full bridge rectifier.

[0070] FIG. 5, portion a) shows the switching scheme for switch S1, FIG. 5, portion b) shows the switching scheme for switch S3, FIG. 5, portion c) shows the switching scheme for switch S2 and FIG. 5, portion d) shows the switching scheme for switch S4.

[0071] It is to be noted that the control signals as such, as generated by the drive signal generator, are not shown in FIG. 5.

[0072] And it is further to note that the dead times of the switching scheme are not shown explicitly in the figures but just schematically in that the switch-on times are slightly delayed compared to the switch-off times of the switches.

[0073] FIG. 5, portion e) shows the up-down counter 40 having a period that is twice as long as the period T of the input voltage Vin. The up-down counter 40 starts from its minimum value zero and ramps up to its maximum value 1 within one period T and then starts ramping down from its maximum value 1 to its minimum value zero again within one period T. The up-down counter 40 therefore has a period of 2T which is also designated as the modulation period T.sub.mod. FIG. 5, portion e) further shows the first compare value 41 having a value of D/4 as well as the second compare value 42 having a value of (2+D)/4.

[0074] It is to note that in the example shown in FIG. 5 the first and the second compare value as shown in FIG. 5, portion e) is used for both half bridges, i. e. for the switches S1 and S3 as well as for the switches S2 and S4. Accordingly, the up-down counter for the switches S2 and S4 of the second half bridge includes a phase shift of T. For the sake of clarity, this up-down counter for the second half bridge is however not shown in FIG. 5.

[0075] Not shown in FIG. 5 is another example where no phase shift between the two half bridges is applied and the same up-down counter 40 is used for both half bridges. In this case, the compare values for the first half bridge would be same as shown in FIG. 5, portion e), namely the compare value 41 having the value D/4 and the second compare value 42 having the value (2+D)/4. However, the compare values for the second half bridge would be different. The first compare value would be (1−D/4) and the second compare value would be (1−(2+D)/4).

[0076] As can be seen from FIG. 5, portion a) to portion e): [0077] switch S1 is switched ON when the up-down counter 40 crosses the first compare value 41 on an up-count of the up-down counter 40 and switch S1 is switched OFF when the up-down counter 40 crosses the second compare value 42 on an up-count of the up-down counter 40. And then, switch S1 is switched ON when the up-down counter 40 crosses the second compare value 42 on a down-count of the up-down counter 40 and switch S1 is switched OFF when the up-down counter 40 crosses the first compare value 41 on a down-count of the up-down counter 40; [0078] switch S3 is switched OFF when the up-down counter 40 crosses the first compare value 41 on an up-count of the up-down counter 40 and switch S3 is switched ON 10 when the up-down counter 40 crosses the second compare value 42 on an up-count of the up-down counter 40. And then, switch S3 is switched OFF when the up-down counter 40 crosses the second compare value 42 on a down-count of the up-down counter 40 and switch S3 is switched ON when the up-down counter 40 crosses the first compare value 41 on a down-count of the up-down counter 40.

[0079] Accordingly, switch S3 is switched interleaved to switch S1. As can further be seen from FIG. 5, portion a) to portion e), [0080] switch S2 is switched ON and OFF in the same way as switch S3 but including a phase shift of period T, [0081] and switch S4 is switched ON and OFF in the same way as switch S1 but also including a phase shift of period T.

[0082] Again, switches S2 and S4 are switched interleaved to each other.

[0083] FIG. 5, portion f) shows the resulting output voltage of the inverter full bridge 4 and FIG. 5, portion g) shows the resulting output current i.sub.LS of the inverter full bridge 4.

[0084] Whereas the output current i.sub.LS of the inverter full bridge 4 as shown in FIG. 5, portion g) does not differ from the output current i.sub.LS as shown in FIG. 2, portion b), it can be seen from FIG. 5, portion a) to portion d) that during a single modulation period T.sub.mod=2T: [0085] switch S1 is switched ON once at the current i.sub.P3 and once at the current i.sub.P2, [0086] switch S1 is switched OFF once at the current i.sub.P3 and once at the current i.sub.P2, [0087] switch S3 is switched ON once at the current i.sub.P2 and once at the current i.sub.P3 and [0088] switch S3 is switched OFF once at the current i.sub.P3 and once at the current i.sub.P2;

[0089] And, [0090] switch S2 is switched ON once at the current i.sub.P3 and once at the current i.sub.P2, [0091] switch S2 is switched OFF once at the current i.sub.P2 and once at the current i.sub.P3, [0092] switch S4 is switched ON once at the current i.sub.P3 and once at the current i.sub.P2 and [0093] switch S4 is switched OFF once at the current i.sub.P3 and once at the current i.sub.P2.

[0094] Or in other words, all switches S1-S4 are switched ON and OFF at the same number of higher currents i.sub.P2 and lower currents i.sub.P3.

[0095] Accordingly, the switching scheme as shown in FIG. 5 does not have the disadvantage that one of the legs is stressed with larger switching losses than the other leg. The turn-off and the turn-on currents are the same for all switches over a single modulation period of 2T.

[0096] So, the thermal stress is the same for all switches S1-S4. And in the phase-shifted full-bridge converter, ZVS is not prevented in light load conditions due to too less energy of the series inductor.

[0097] The switching scheme according to the disclosure may not only be applied to the inverter configurations describe above, it may however also be applied to an LLC converter including a diode full bridge rectifier. And it may also be applied to other converter configurations including an inverter full bridge as described above independent of the particular implementation of the converter stage and the rectifier in the secondary.

[0098] In summary, it is to be noted that the disclosure enables to create a converter including an inverter full bridge and a corresponding closed modulation method that reduces or even eliminates the thermal imbalance of the switches of the inverter full bridge during operation.