RING OSCILLATOR CIRCUIT

Abstract

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

Claims

1. A ring oscillator circuit comprising: a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage; a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node, wherein each inverter stage comprises a first low-side transistor and a second low-side transistor coupled in series between the reference voltage node and an output node of the respective inverter stage, and a first high-side transistor coupled between the oscillator supply voltage node and the output node of the respective inverter stage, wherein the first low-side transistor and the first high-side transistor of each inverter stage have respective control terminals coupled to an input node of the respective inverter stage to receive therefrom a respective inverter control signal, and wherein the second low-side transistor of each inverter stage has a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage; and a biasing circuit comprising a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor has a control terminal configured to receive an oscillator control signal indicative of whether the ring oscillator circuit is in an active operation state or in an inactive operation state, wherein the second bias control transistor has a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage, and wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

2. The ring oscillator circuit of claim 1, wherein a conductivity of the first low-side transistors, when operating in a conductive state is higher than a conductivity of the respective second low-side transistors, when operating in a conductive state.

3. The ring oscillator circuit of claim 1, wherein a conductive channel of the first low-side transistors is shorter than a conductive channel of the respective second low-side transistors.

4. The ring oscillator circuit of claim 1, wherein each inverter stage comprises a second high-side transistor coupled in series to the first high-side transistor between the oscillator supply voltage node and the output node of the respective inverter stage, and wherein the second high-side transistor has a control terminal coupled to the reference voltage node.

5. The ring oscillator circuit of claim 4, wherein the second high-side transistor of a last inverter stage in a chain of cascade-coupled inverter stages has a control terminal configured to receive the oscillator control signal.

6. The ring oscillator circuit of claim 4, wherein a conductivity of the first high-side transistors, when operating in a conductive state, is higher than a conductivity of the respective first low-side transistors, when operating in a conductive state, and higher than a conductivity of the respective second low-side transistors, when operating in a conductive state.

7. The ring oscillator circuit of claim 4, wherein a conductivity of the second high-side transistors, when operating in a conductive state, is higher than a conductivity of the respective first low-side transistors, when operating in a conductive state, and higher than a conductivity of the respective second low-side transistors, when operating in a conductive state.

8. The ring oscillator circuit of claim 4, wherein a conductivity of the first high-side transistors and the second high-side transistors, when operating in a conductive state, is higher than a conductivity of the respective first low-side transistors, when operating in a conductive state and higher than a conductivity of the respective second low-side transistors, when operating in a conductive state.

9. The ring oscillator circuit of claim 4, wherein a conductive channel of the first high-side transistors is shorter than a conductive channel of the respective first low-side transistors and shorter than a conductive channel of the respective second low-side transistors.

10. The ring oscillator circuit of claim 4, wherein a conductive channel of the second high-side transistors is shorter than a conductive channel of the respective first low-side transistors and shorter than a conductive channel of the respective second low-side transistors.

11. The ring oscillator circuit of claim 4, wherein a conductive channel of the first high-side transistors and the second high-side transistors is shorter than a conductive channel of the respective first low-side transistors and shorter than a conductive channel of the respective second low-side transistors.

12. The ring oscillator circuit of claim 1, further comprising an output control transistor coupled between an output node of the ring oscillator circuit and the reference voltage node.

13. The ring oscillator circuit of claim 12, wherein the output control transistor has a control terminal configured to receive the oscillator control signal, and wherein the output control transistor is configured to selectively couple the reference voltage node and the output node of the ring oscillator circuit in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

14. The ring oscillator circuit of claim 1, wherein each inverter stage comprises a plurality of the second low-side transistors arranged in parallel, wherein the second low-side transistors arranged in parallel have different conductivity values, when operating in a conductive state, and wherein the second low-side transistors arranged in parallel have respective control terminals selectively couplable to the oscillator supply voltage node as a function of respective frequency selection signals.

15. The ring oscillator circuit of claim 14, wherein the biasing circuit includes a plurality of the second bias control transistors arranged in parallel, wherein the second bias control transistors arranged in parallel have different conductivity values, when operating in a conductive state, and wherein the second bias control transistors arranged in parallel have respective control terminals selectively couplable to the oscillator supply voltage node as a function of the respective frequency selection signals.

16. The ring oscillator circuit of claim 1, wherein the biasing circuit includes a plurality of the second bias control transistors arranged in parallel, wherein the second bias control transistors arranged in parallel have different conductivity values, when operating in a conductive state, and wherein the second bias control transistors arranged in parallel have respective control terminals selectively couplable to the oscillator supply voltage node as a function of the respective frequency selection signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments will now be described, by way of example only, with reference to the annexed figures.

[0020] FIG. 1 is a circuit diagram exemplary of a ring oscillator;

[0021] FIG. 2 is a circuit diagram exemplary of a portion of a ring oscillator;

[0022] FIG. 3 is a diagram exemplary of possible time behavior of signals in a balanced ring oscillator;

[0023] FIG. 4 is a diagram exemplary of possible time behavior of signals in an unbalanced ring oscillator;

[0024] FIG. 5 is a circuit diagram exemplary of a ring oscillator according to one or more embodiments of the present description;

[0025] FIG. 6 is a circuit diagram exemplary of a portion of a ring oscillator according to one or more embodiments of the present description;

[0026] FIG. 7 is a circuit diagram exemplary of an equivalent circuit of the low-side portion of an inverter stage of a ring oscillator according to one or more embodiments of the present description, during a discharge phase of the oscillation period;

[0027] FIG. 8 is a circuit diagram exemplary of an inverter stage of a ring oscillator according to one or more embodiments of the present description; and

[0028] FIG. 9 is a circuit diagram exemplary of a biasing circuit of a ring oscillator according to one or more embodiments of the present description.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0029] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0030] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0031] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0032] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.

[0033] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIG. 1, which is a circuit diagram exemplary of a current starved ring oscillator 10 (also referred to simply as ring oscillator in the present description, for the sake of brevity only).

[0034] A ring oscillator 10 comprises a chain of inverter stages 12, e.g., five inverter stages 12.sub.A, 12.sub.B, 12.sub.C, 12.sub.D, 12.sub.E as exemplified in FIG. 1. Each inverter stage 12 comprises an input node and an output node, with the output node of each inverter stage in the chain coupled to the input node of a subsequent inverter stage in the chain. The output node of the last inverter stage of the chain (e.g., 12.sub.E) is coupled to the input node of the first inverter stage of the chain (e.g., 12.sub.A). The input (clock) signals CK received at the input nodes of the inverter stages are respectively designated herein as CK.sub.A, CK.sub.B, CK.sub.C, CK.sub.D, CK.sub.E. As exemplified in FIG. 1, each inverter stage is coupled between an oscillator supply voltage node 14 and a common reference voltage node 16. The oscillator supply voltage node 14 may provide a common oscillator supply voltage V.sub.RO_SUPPLY, and the reference voltage node 16 may provide a common reference voltage V.sub.GND (e.g., 0 V). Each inverter stage 12 may comprise a respective n-channel MOS transistor MN (e.g., MN.sub.A, MN.sub.B, MN.sub.C, MN.sub.D, MN.sub.E) having a source terminal coupled to the reference voltage node 16 and a drain terminal coupled to the output node of the respective inverter stage, and a respective p-channel MOS transistor MP (e.g., MP.sub.A, MP.sub.B, MP.sub.C, MP.sub.D, MP.sub.E) having a source terminal coupled to the oscillator supply voltage node 14 and a drain terminal coupled to the output node of the respective inverter stage. The gate terminals of the n-channel MOS transistors MN and of the p-channel MOS transistors MP may be coupled to the input nodes of the respective inverter stages. All the transistors MN may have their bulk terminal connected to the reference voltage node 16, and all the transistors MP may have their bulk terminal connected to the oscillator supply voltage node 14.

[0035] A capacitance C.sub.RO may be coupled between the oscillator supply voltage node 14 and the common reference voltage node 16. The person skilled in the art will understand that the capacitance C.sub.RO can be either an intrinsic capacitance at node 14 or an external capacitance added on purpose to increase the capacitance value at node 14, so as to improve the stability of the oscillator supply voltage V.sub.RO_SUPPLY. In one or more embodiments, the capacitance C.sub.RO may be an external capacitor whose capacitance adds up to the intrinsic one.

[0036] The ring oscillator 10 may comprise a current generator 18 coupled between the oscillator supply voltage node 14 and a further supply voltage node 20 (e.g., a system supply voltage node) that provides a system supply voltage V.sub.DD, e.g., higher than the oscillator supply voltage V.sub.RO_SUPPLY. The current generator 18 may force a current I.sub.OSC to flow (e.g., may inject a current I.sub.OSC) into the oscillator supply voltage node 14, thereby controlling (e.g., limiting) the value of the oscillator current I.sub.OSC. The oscillation swing (e.g., the maximum signal amplitude at the output node of the last inverter stage 12.sub.E) is limited to the oscillator supply voltage V.sub.RO_SUPPLY at node 14. The voltage level V.sub.RO_SUPPLY in turn depends on the value of the current I.sub.OSC and on the sizing of the inverter stages 12.

[0037] In a ring oscillator 10 as exemplified in FIG. 1, the oscillation frequency depends on the voltage V.sub.RO_SUPPLY at node 14 and on the capacitive load at the output node of each inverter stage 12. The global oscillation period T.sub.OSC is equal to n times the propagation delay T.sub.D of each inverter stage (i.e., T.sub.OSC=n*T.sub.D), n being the number of chained inverter stages 12 (e.g., in the case exemplified herein where the ring oscillator 10 comprises five inverter stages, T.sub.OSC=5*T.sub.D). In a simplified model, the propagation delay T.sub.D of each inverter stage 12 is equal to the sum of two components, i.e., the rising edge time T.sub.RE and the falling edge time T.sub.FE: T.sub.D=T.sub.RE+T.sub.FE.

[0038] In a conventional current starved ring oscillator, providing satisfactory temperature compensation may rely on finding the correct tuning between different variables, leading to an unclear design procedure. For instance, given the oscillation frequency F.sub.OSC, the minimum system supply voltage V.sub.DD,min (at node 20) and the power consumption level as target specifications, the available design parameters may include the value of the current I.sub.OSC and/or the buffer sizing (e.g., sizing of the inverter stages 12).

[0039] Additionally, in a conventional current starved ring oscillator, (dynamic) tuning of the oscillation frequency F.sub.OSC (e.g., to provide oscillation at multiple frequencies) may rely on varying the value of the current I.sub.OSC, thereby affecting the accuracy of the temperature compensation, which is usually obtained for a single working point (i.e., temperature compensation may be effective only for a single value of the oscillator current I.sub.OSC).

[0040] Additionally, operation of a conventional current starved ring oscillator may include a start transient during which the oscillator operates at a frequency (initial frequency) not corresponding to the target frequency. In some applications, fast oscillator start/stop operation may be desirable (e.g., for use in charge pump circuits, or to generate timing phases for reading circuitry in a memory, and the like). A stabilization period can be requested after a stop or at start up to restart the oscillation. The oscillator can be started periodically (e.g., to refresh internal voltages such as the oscillator supply voltage V.sub.RO_SUPPLY), but an additional oscillator may be required (e.g., a low consumption oscillator).

[0041] Operation of a ring oscillator 10 as exemplified in FIG. 1 may be further understood with reference to FIGS. 2, 3 and 4 discussed below.

[0042] FIG. 2 is a circuit diagram exemplary of a portion of the ring oscillator 10, illustrating in particular the inverter stages 12.sub.C, 12.sub.D and the respective input signal CK.sub.C, intermediate signal CK.sub.D, and output signal CK.sub.E. Additionally, FIG. 2 illustrates the capacitances C.sub.OSC,C and C.sub.OSC,D (e.g., intrinsic capacitances) at the output nodes of the inverter stages 12.sub.C and 12.sub.D, which affect the propagation delay T.sub.D of the inverter stages. It will be understood that FIG. 2 refers to a portion of the ring oscillator 10 by way of example, and that similar operation may take place in other portions of the ring oscillator 10.

[0043] FIG. 3 is a diagram exemplary of possible time behavior of signals CK.sub.C (dotted line), CK.sub.D (solid line) and CK.sub.E (dash-and-dot line) in the ring oscillator 10 exemplified in FIG. 2, according to a first example where the p-channel MOS transistors MP and the n-channel MOS transistors MN in the inverter stages 12 are balanced (e.g., they have similar conductivity in the ON state).

[0044] During each of the (e.g., five) time slots T.sub.D=T.sub.RE+T.sub.FE, the amount of current sunk from the oscillator supply voltage node 14 is equal to I.sub.OSC, insofar as a current I.sub.OSC is forced to flow into node 14 by the current generator 18. Such a condition provides an equilibrium point in the oscillator supply voltage node 14, with the oscillator supply voltage V.sub.RO_SUPPLY comprised between the reference voltage of node 16 (e.g., 0 V) and the system supply voltage V.sub.DD (e.g., 0 V<V.sub.RO_SUPPLY<V.sub.DD). In such a case, the current driven by each p-channel MOS transistor MP can be computed as I.sub.P=C.sub.OSC*V.sub.RO_SUPPLY/T.sub.RE.

[0045] The average current sunk from the oscillator supply voltage node 14 during each “commutation interval” T.sub.D can thus be computed as I.sub.P*T.sub.RE/T.sub.D=I.sub.OSC.

[0046] Therefore, as a result of an increase of the current I.sub.P, the rising edge time T.sub.RE decreases provided that the commutation interval T.sub.D remains the same; so, the falling edge time T.sub.FE increases.

[0047] FIG. 4 is a diagram exemplary of possible time behavior of signals CK.sub.C (dotted line), CK.sub.D (solid line) and CK.sub.E (dash-and-dot line) in the ring oscillator 10 exemplified in FIG. 2, according to a second example where the p-channel MOS transistors MP and the n-channel MOS transistors MN in the inverter stages 12 are unbalanced. In particular, FIG. 4 is exemplary of a case where the p-channel MOS transistors MP are (much) faster than the re-channel MOS transistors MN.

[0048] In the case exemplified in FIG. 4, the rising edge time T.sub.RE may amount to a short portion of the (overall) commutation interval T.sub.D. Such a condition can be approximated as if at least one n-channel MOS transistor is always conductive (i.e., in an ON state) in any phase of the oscillation. Given the above approximation, the n-channel MOS transistor should be polarized during the discharge phase to sink a current I.sub.N equal to the current I.sub.OSC forced to flow into the oscillator supply voltage node 14, according to the following equations:

I.sub.N*T.sub.FE/T.sub.D=I.sub.OSC.fwdarw.I.sub.N≈I.sub.OSCif T.sub.RE«T.sub.FE

[0049] Therefore, unbalanced sizing of the p-channel MOS transistors and the n-channel MOS transistors of the inverter stages 12 (e.g., with the p-channel MOS transistors being much more conductive than the n-channel MOS transistors) may have one or more of the following implications: [0050] with V.sub.RO_SUPPLY>0 the n-channel MOS transistors sink a constant current I.sub.N equal to I.sub.OSC during the conductive (e.g., ON) phase; [0051] as a result of a short rising edge time T.sub.RE, the n-channel MOS transistors have their gate terminals biased to the oscillator supply voltage V.sub.RO_SUPPLY during the respective falling edge time slot T.sub.FE (e.g., constantly biased to V.sub.RO_SUPPLY); [0052] the oscillator supply voltage V.sub.RO_SUPPLY should be equal to the gate-source voltage V.sub.GS needed to force through the n-channel MOS transistors the current I.sub.OSC (e.g., on the drain terminal); [0053] as a result of the size of the n-channel MOS transistors being such that the transistors operate at their null point at a current level I.sub.N≈I.sub.OSC, the oscillator supply voltage V.sub.RO_SUPPLY at node 14 may be compensated with respect to temperature variations.

[0054] In the context of the present description, the definition of “null point biasing” is based on the recognition that, for any n-channel MOS transistor, it is possible to define, as a function of the transistor size (e.g., width-to-length ratio W/L), a value of the drain current (I.sub.D) where the gate-source voltage V.sub.GS is constant with respect to temperature. In such a biasing point, the temperature derivatives of the threshold voltage (V.sub.TH) of the n-channel MOS transistor and the overdrive voltage (V.sub.OD=V.sub.GS−V.sub.TH) of the n-channel MOS transistor compensate each other so as to maintain constant the drain current, provided that the n-channel MOS transistor operates in saturation.

[0055] Therefore, in one or more embodiments, the p-channel MOS transistors being (much) faster than the n-channel MOS transistors, and the n-channel MOS transistors being biased at null point versus current I.sub.OSC may result in the oscillator supply voltage V.sub.RO_SUPPLY at node 14 being constant with respect to temperature variations (null point voltage of the n-channel MOS transistors), so that the oscillation will be constant with respect to temperature variations due to a constant oscillator supply voltage V.sub.RO_SUPPLY and a constant oscillator current I.sub.OSC, as per the equations below:

[00001]$V_{\mathrm{RO}\_\mathrm{SUPPLY}}~V_{\mathrm{thn}}+\sqrt[2]{\frac{I_{\mathrm{OSC}}.Math.2}{{\mu }_n.Math.C_{\mathrm{ox}}}.Math.\frac{L}{W}}~\mathrm{Constant}\mathrm{at}\mathrm{Null}\mathrm{Point}$$T_{\mathrm{OSC}}~N.Math.\frac{C_{\mathrm{OSC}}.Math.V_{\mathrm{RO}\_\mathrm{SUPPLY}}}{I_{\mathrm{OSC}}}$

[0056] Therefore, one or more embodiments may relate to a current starved ring oscillator 50 as exemplified in FIG. 5.

[0057] A ring oscillator 50 comprises a chain of inverter stages 52, e.g., five inverter stages 52.sub.A, 52.sub.B, 52.sub.C, 52.sub.D, 52.sub.E as exemplified in FIG. 5. Each inverter stage 52 comprises an input node and an output node, with the output node of each inverter stage in the chain coupled to the input node of a subsequent inverter stage in the chain. The output node of the last inverter stage of the chain (e.g., 52.sub.E) is coupled to the input node of the first inverter stage of the chain (e.g., 52.sub.A). The input (clock) signals CK received at the input nodes of the inverter stages are respectively designated herein as CK.sub.A, CK.sub.B, CK.sub.C, CK.sub.D, CK.sub.E. As exemplified in FIG. 5, each inverter stage is coupled between an oscillator supply voltage node 54 and a common reference voltage node 56. The oscillator supply voltage node 54 may provide a common oscillator supply voltage V.sub.RO_SUPPLY, and the reference voltage node 56 may provide a common reference voltage V.sub.GND (e.g., 0 V).

[0058] Each inverter stage 52 may comprise two n-channel MOS transistors N.sub.L (e.g., N.sub.LA, N.sub.LB, N.sub.LC, N.sub.LD, N.sub.LE) and N.sub.F (e.g., N.sub.FA, N.sub.FB, N.sub.FC, N.sub.FD, N.sub.FE) arranged in series between the reference voltage node 56 and the output node of the inverter stage. For instance, transistors N.sub.F may have their source terminals coupled to the reference voltage node 56 and their drain terminals coupled to the source terminals of the respective transistors N.sub.L. Transistors N.sub.L may have their drain terminals coupled to the output nodes of the respective inverter stages. All the transistors N.sub.L and N.sub.F may have their bulk terminals connected to the reference voltage node 56. The gate terminals of the transistors N.sub.F may be coupled to the input nodes of the respective inverter stages. The gate terminals of the transistors N.sub.L may be coupled to the oscillator supply voltage node 54 to receive the oscillator supply voltage V.sub.RO_SUPPLY.

[0059] Each inverter stage 52 may comprise a p-channel MOS transistor P.sub.F1 (e.g., P.sub.F1A, P.sub.F1B, P.sub.F1C, P.sub.F1D, P.sub.F1E) having a source terminal coupled to the oscillator supply voltage node 54 and a drain terminal coupled to the output node of the inverter stage. All the transistors P.sub.F1 may have their bulk terminals connected to the oscillator supply voltage node 54. The gate terminals of the transistors P.sub.F1 may be coupled to the input nodes of the respective inverter stages.

[0060] Optionally, each inverter stage 52 may comprise a further p-channel MOS transistor P.sub.F2 (e.g., P.sub.F2A, P.sub.F2B, P.sub.F2C, P.sub.F2D, P.sub.F2E) arranged in series with the respective transistor P.sub.F1. For instance, transistors P.sub.F1 may have their source terminals coupled to the oscillator supply voltage node 54 and their drain terminals coupled to the source terminals of the respective transistors P.sub.F2. Transistors P.sub.F2 may have their drain terminals coupled to the output nodes of the respective inverter stages. All the transistors P.sub.F2 may have their bulk terminals connected to the oscillator supply voltage node 54. The gate terminals of the transistors P.sub.F2 may be coupled to the reference voltage node 56 to receive the reference voltage V.sub.GND (e.g., 0 V). Optionally, the gate terminal of the further transistor P.sub.F2 of the last inverter stage of the inverter chain (e.g., transistor P.sub.F2E in the example of FIG. 5) may be configured to receive a control signal StartP generated as discussed in the following.

[0061] In one or more embodiments, transistors N.sub.L and N.sub.F may have different dimensions, insofar as they are designed to play a different role in the switching activity of the inverter stages 52. In particular, the channels of transistors N.sub.L may have a width W.sub.N and a length L.sub.L. The channels of transistors N.sub.F may have the same width W.sub.N and a different (e.g., shorter) length L.sub.S. Therefore, the low-side current flow line of each inverter stage 52 may comprise two n-channel MOS transistors, with a first resistive transistor N.sub.L not oscillating and having a gate terminal biased constantly at V.sub.RO_SUPPLY, and a second highly conductive transistor N.sub.F oscillating as driven by the respective signal CK. The second transistor N.sub.F may be designed to have a low load for oscillation, thereby facilitating oscillation at a high frequency.

[0062] In one or more embodiments, transistors P.sub.F1 and P.sub.F2 may have the same dimensions, insofar as they are designed to play a similar role in the switching activity of the inverter stages 52. In particular, the channels of transistors P.sub.F1 may have a width W.sub.P and a length L.sub.min. The channels of transistors P.sub.F2 may have the same width W.sub.P and the same length L.sub.min.

[0063] In one or more embodiments, the p-channel MOS transistors P.sub.F1 and P.sub.F2 may be designed to be (much) more conductive than the n-channel MOS transistors N.sub.L and N.sub.F when operated in the ON state, e.g., by selecting the length L.sub.min to be (much) shorter than the lengths L.sub.L and L.sub.S. Therefore, the ring oscillator 50 may be substantially unbalanced.

[0064] In one or more embodiments as exemplified in FIG. 5, a ring oscillator 50 may comprise a biasing circuit 500. The basing circuit 500 may comprise a current generator 58 coupled between the oscillator supply voltage node 54 and a further supply voltage node 60 (e.g., a system supply voltage node) providing a system supply voltage V.sub.DD, e.g., higher than the oscillator supply voltage V.sub.RO_SUPPLY. The current generator 58 may force a current I.sub.OSC to flow into the oscillator supply voltage node 54 by (e.g., the current generator 58 may inject a current I.sub.OSC into node 54).

[0065] The biasing circuit 500 may comprise an input terminal 502 configured to receive a control signal StartOsc. The control signal StartOsc may be asserted (e.g., set to 1) when the ring oscillator is expected to produce an oscillating output voltage, and may be de-asserted (e.g., set to 0) when the ring oscillator is not expected to produce an oscillating output voltage. The biasing circuit 500 may comprise an inverter circuit 504 configured to receive the control signal StartOsc and to produce an output signal StartP that substantially corresponds to an inverted replica of the control signal StartOsc. The biasing circuit 500 may comprise two n-channel MOS transistors N.sub.LZ and N.sub.FZ arranged in series between the reference voltage node 56 and the oscillator supply voltage node 54. For instance, transistor N.sub.FZ may have a source terminal coupled to the reference voltage node 56 and a drain terminal coupled to the source terminal of transistor N.sub.LZ. Transistor N.sub.LZ may have a drain terminal coupled to the oscillator supply voltage node 54. Transistors N.sub.LZ and N.sub.FZ may have their bulk terminals connected to the reference voltage node 56. The gate terminal of transistor N.sub.FZ may be coupled to the output of the inverter circuit 504 to receive the control signal StartP. The gate terminal of transistor N.sub.LZ may be coupled to the oscillator supply voltage node 54 to receive the oscillator supply voltage V.sub.RO_SUPPLY. Transistors N.sub.LZ and N.sub.FZ may be sized substantially as the pairs of transistors N.sub.L and N.sub.F in the inverter stages 52. In particular, the channel of transistor N.sub.LZ may have a width W.sub.N and a length L.sub.L. The channel of transistor N.sub.FZ may have the same width W.sub.N and a different length L.sub.S.

[0066] The biasing circuit 500 may comprise a capacitance C.sub.RO coupled between the oscillator supply voltage node 54 and the common reference voltage node 56. As previously discussed, the capacitance C.sub.RO can be either an intrinsic capacitance at node 54 or an external capacitance added on purpose to increase the capacitance value at node 54, so as to improve the stability of the oscillator supply voltage V.sub.RO_SUPPLY. In one or more embodiments, the capacitance C.sub.RO may be an external capacitor whose capacitance adds up to the intrinsic one.

[0067] In one or more embodiments, a ring oscillator 50 may further comprise an n-channel MOS transistor 62 having a selectively conductive channel arranged between the output node of the ring oscillator 50 (e.g., the output terminal of the last inverter stage, exemplified herein by the inverter stage 52.sub.E) and the reference voltage node 56. For instance, transistor 62 may have a source terminal coupled to the reference voltage node 56 and a drain terminal coupled to the output node of the ring oscillator 50. The bulk terminal of transistor 62 may be connected to the reference voltage node 56. The gate terminal of transistor 62 may be coupled to the output node of the inverter circuit 504 to receive the control signal StartP.

[0068] Operation of a ring oscillator 50 as exemplified in FIG. 5 may be further understood with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram exemplary of a portion of a ring oscillator 50, in particular exemplary of the inverter stages 52.sub.B and 52.sub.C. FIG. 7 is a circuit diagram exemplary of an equivalent representation of the low-side portion of the inverter stage 52.sub.B during a discharge phase of the respective oscillation period.

[0069] As exemplified in FIG. 7, during oscillation of the ring oscillator 50, the gate terminals of the transistors N.sub.L and N.sub.F in the low-side portion of a certain inverter stage (e.g., the second inverter stage 52.sub.B, purely by way of example) are biased at V.sub.RO_SUPPLY during the respective discharge phase (i.e., when the high-side portion of the inverter is in a non-conductive state and the low-side portion of the inverter is in a conductive state), insofar as transistors NL are constantly biased at V.sub.RO_SUPPLY and transistors NF receive a driving signal CK that switches between V.sub.GND (e.g., 0 V) and V.sub.RO_SUPPLY. Polarization of the series arrangement of transistors N.sub.L and N.sub.F is equivalent to a constant biasing at I.sub.OSC on an equivalent series transistor having length L.sub.EQ=L.sub.L+L.sub.S. The equivalent transistor may be biased in null point at I.sub.OSC, thereby providing temperature compensation of the oscillator supply voltage V.sub.RO_SUPPLY at null point.

[0070] In one or more embodiments, the transistor N.sub.FZ driven by signal StartP may be turned off during oscillation of the ring oscillator 50 (e.g., when StartOsc=1 and StartP=0) and may be turned on while the ring oscillator 50 is inactive (e.g., when StartOsc=0 and StartP=1) in order to keep the oscillator supply voltage V.sub.RO_SUPPLY at node 54 close to oscillation operating value. By having the oscillator supply voltage V.sub.RO_SUPPLY biased very close to the oscillation operating voltage before starting the oscillator 50, the oscillations may rapidly reach a regime value upon activation of the ring oscillator 50. This may facilitate reducing or even avoiding a transient (out-of-specification) phase at the start of the ring oscillator 50.

[0071] In one or more embodiments, a high oscillation frequency (e.g., around 900 MHz) may be achieved resorting to a series arrangement of two n-channel MOS transistors in the low-side portion of the inverter stages 52. In particular, a MOS transistor with a long channel (N.sub.L, having length L.sub.L) does not switch and has a gate terminal constantly biased at V.sub.RO_SUPPLY, and a MOS transistor with a short channel (N.sub.F, having length L.sub.S) switches under the control of a respective control signal CK, providing a low loading for oscillations at high frequencies.

[0072] Additionally, unbalanced sizing of the high-side p-channel MOS transistors and the low-side n-channel MOS transistors (e.g., with the p-channel transistors being more conductive than the n-channel transistors) may result in fast rising edges and slow falling edges of the signals CK.

[0073] One or more embodiments may thus provide a clear design procedure for the design of a ring oscillator 50. In particular, the design procedure may set certain parameters of the ring oscillator 50 as target parameters. The target parameters may include a minimum system supply voltage V.sub.DD,min, an oscillation frequency F.sub.OSC, and/or a power consumption level (e.g., a value of the oscillator current I.sub.OSC). Once set the parameters above, the design procedure may include selecting the size W/L (width to length ratio) of the equivalent n-channel MOS transistor for the low-side portions of the inverter stages in order to obtain a value of oscillator supply voltage V.sub.RO_SUPPLY compatible with the minimum system supply voltage V.sub.DD,min at the null biasing point of the equivalent n-channel MOS transistor. For instance, V.sub.RO_SUPPLY may be selected to be approximately equal to V.sub.DD,min−0.1V to maintain the current generator 58 in saturation. The width to length ratio W/L of the equivalent n-channel MOS transistor may be selected such that V.sub.RO_SUPPLY is the gate voltage at null point with current I.sub.OSC flowing in the equivalent n-channel MOS transistor. At this stage, the length L.sub.S of switching transistor N.sub.F may be selected to be short enough to fulfill the capacitance target (C.sub.OSC) to meet the desired oscillation frequency F.sub.OSC. The length L.sub.L of non-switching transistor N.sub.L may be selected to be equal to the difference in lengths, as L.sub.L=L−L.sub.S. As indicated in the equation below, the capacitance of the n-channel MOS transistor N.sub.F may be selected to meet the desired oscillation frequency F.sub.OSC:

[00002]$T_{\mathrm{OSC}}=\frac{1}{F_{\mathrm{OSC}}}~N.Math.\frac{C_{\mathrm{OSC}}.Math.V_{\mathrm{RO}\_\mathrm{SUPPLY}}}{I_{\mathrm{OSC}}}=N.Math.\frac{(C_{\mathrm{PMOS}}+C_{\mathrm{NMOS}}.Math.V_{\mathrm{RO}\_\mathrm{SUPPLY}}}{I_{\mathrm{OSC}}}$

[0074] In one or more embodiments as exemplified in FIG. 8, a ring oscillator 50 may be configured to provide operation at multiple (e.g., selectable) oscillation frequencies while preserving temperature compensation at any such frequency.

[0075] In particular, FIG. 8 is a circuit diagram exemplary of a single inverter stage 52′ as possibly provided in a ring oscillator 50. The person skilled in the art will understand that a single inverter stage 52′ is illustrated in FIG. 8 for the sake of ease of illustration only, and that a ring oscillator 50 may comprise a chain of inverter stages 52′ as previously discussed with reference to FIG. 5. In one or more embodiments, the low-side portion of each inverter stage 52′ may comprise two (or more) resistive n-channel MOS transistors N.sub.L1, N.sub.L2 arranged in parallel in the place of a single n-channel MOS transistor N.sub.L. The transistors N.sub.L1 and N.sub.L2 may have the same width W.sub.N and different lengths L.sub.L1 and L.sub.L2, respectively.

[0076] The gate terminal of each of the transistors N.sub.L1, N.sub.L2 is configured to receive the voltage V.sub.RO_SUPPLY via a respective selectively activatable buffer (e.g., inverter) circuit 80.sub.1, 80.sub.2. For instance, the gate terminal of transistor N.sub.L1 may be coupled to the output node of an inverter 80.sub.1 arranged between nodes 54 and 56, which may receive a control signal F1 at a respective input node 801. The gate terminal of transistor N.sub.L2 may be coupled to the output node of an inverter 80.sub.2 arranged between nodes 54 and 56, which may receive a control signal F2 at a respective input node 802. Therefore, if F1=1 and F2=0 the inverter stage 52′ operates via the series arrangement of transistors N.sub.F and N.sub.L2, and if F1=0 and F2=1 the inverter stage 52′ operates via the series arrangement of transistors N.sub.F and N.sub.L1. Since transistors Nu, N.sub.L2 have different lengths and are designed to have null biasing point at different values of the current I.sub.OSC, then I.sub.OSC2≠I.sub.OSC1 and F.sub.OSC2≠F.sub.OSC1.

[0077] In one or more embodiments as exemplified with reference to FIG. 8, the biasing circuit may be modified accordingly, providing two (or more) resistive n-channel MOS transistors N.sub.LZ1, N.sub.LZ2 arranged in parallel in the place of a single n-channel MOS transistor N.sub.LZ. FIG. 9 is a circuit diagram exemplary of such a modified biasing circuit 500′. The transistors N.sub.LZ1 and N.sub.LZ2 may have the same width W.sub.N and different lengths L.sub.L1 and L.sub.L2, respectively.

[0078] The gate terminal of each of the transistors N.sub.LZ1, N.sub.LZ2 is configured to receive the voltage V.sub.RO_SUPPLY via the respective selectively activatable buffer (or inverter) circuit 80.sub.1, 80.sub.2. For instance, the gate terminal of transistor NN.sub.LZ1 may be coupled to the output node of inverter 80.sub.1 and the gate terminal of transistor N.sub.LZ2 may be coupled to the output node of inverter 80.sub.2.

[0079] The person skilled in the art will understand that either signal F1 or signal F2 may assume a high logic value (e.g., 1) according to the selected oscillation frequency. In one or more embodiments, more than two resistive n-channel MOS transistors may be provided in parallel, so that more than two selectable oscillation frequencies may be provided. Additionally or alternatively, the oscillation frequency may be selected by operating a combination of such MOS transistors (e.g., depending on the combinations of logic values of the control signals F1, F2, . . . ).

[0080] One or more embodiments may thus provide one or more of the following advantages: [0081] a well-defined design method to obtain a good trade-off between oscillation frequency F.sub.OSC, power consumption, and minimum system supply voltage V.sub.DD,min; [0082] temperature compensation obtained by null point biasing of the low-side n-channel transistors; [0083] possibility of tuning the oscillator circuit at more than one frequency while maintaining a temperature compensation; and [0084] fast start/stop operation of the oscillator circuit without using additional circuitry (e.g., without using an additional oscillator) insofar as the oscillation frequency may be at regime when the oscillator starts, thereby avoiding the risk of out-of-spec frequency for logic blocks that receive the output signal from the oscillator circuit.

[0085] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0086] The extent of protection is determined by the annexed claims.

[0087] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.