INTEGRATED CIRCUIT AND METHOD FOR LIMITING A SWITCHABLE LOAD CURRENT

Abstract

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

Claims

1-10. (canceled)

11. An integrated circuit for limiting a switchable load current, comprising: a main transistor switchable between a conductive state and a non-conductive state, through which in the conductive state a load current flows for supplying a load; a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor, and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor; a coupling circuit which is electrically connected to drain terminals of the main transistor and of the mirror transistor and is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor; and a gate control circuit, which is electrically connected to the gate terminal of the main transistor and which is configured to limit the load current through the main transistor based on a drain current through the mirror transistor.

12. The integrated circuit as recited in claim 11, wherein a width-to-length ratio of the main transistor compared to a width-to-length ratio of the mirror transistor is greater by a factor α>1.

13. The integrated circuit as recited in claim 12, wherein the factor is α≥10.

14. The integrated circuit as recited in claim 12, wherein the factor is α≥100.

15. The integrated circuit as recited in claim 11, wherein the coupling circuit includes: a first secondary transistor, which is connected in series to the mirror transistor; and a second secondary transistor, which is diode-connected and is connected in series to the main transistor, a gate terminal of the first secondary transistor being electrically connected to a gate terminal of the second secondary transistor; a first current sink connected to the drain terminal of the second secondary transistor.

16. The integrated circuit as recited in claim 15, wherein a width-to length ratio of the first secondary transistor differs from a width-to-length ratio of the second secondary transistor by a factor.

17. The integrated circuit as recited in claim 11, wherein the coupling circuit includes: a first secondary transistor, which is connected in series to the mirror transistor; and a first operational amplifier, inputs of the first operational amplifier being electrically connected to the drain terminals of the main transistor and of the mirror transistor, and an output being electrically connected to the gate terminal of the first secondary transistor.

18. The integrated circuit as recited in claim 11, wherein the coupling circuit is configured to set the source drain voltage of the mirror transistor with the source drain voltage of the main transistor to an identical value.

19. The integrated circuit as recited in claim 15, further comprising: a measuring resistor, which is connected in series to the drain terminal of the first secondary transistor, wherein the gate control circuit includes a second operational amplifier which is configured to regulate the gate terminal of the main transistor based on a difference between a measured voltage over the measuring resistor and a reference voltage.

20. The integrated circuit as recited in claim 11, further comprising: a second current sink, which is electrically connected to a drain terminal of the first secondary transistor, wherein the gate control circuit includes a comparator and is configured to switch the main transistor into a non-conductive state when the drain current through the second mirror transistor is greater than a current value of the second current sink.

21. A method for limiting a switchable load current, comprising: providing a mirror transistor and a main transistor, the main transistor being switchable between a conductive state and a non-conductive state and through which in the conductive state a load current flows for supplying a load, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor; tracking a source drain voltage of the mirror transistor as a function of a source drain voltage of the main transistor; and limiting a load current through the main transistor based on a drain current through the mirror transistor.

22. The method for limiting a switchable load current as recited in claim 21, wherein the limiting includes a regulating or a switching off.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments of the present invention are explained in greater detail below with reference to the figures and to the following description.

[0028] FIG. 1 shows an integrated circuit for limiting a switchable load current according to the related art.

[0029] FIG. 2 shows an integrated circuit for limiting a switchable load current according to one first specific example embodiment of the present invention.

[0030] FIG. 3 shows an integrated circuit for limiting a switchable load current according to one second specific example embodiment of the present invention.

[0031] FIG. 4 shows an integrated circuit for limiting a switchable load current according to one third specific example embodiment of the present invention.

[0032] FIG. 5 shows an integrated circuit for limiting a switchable load current according to one fourth specific example embodiment of the present invention.

[0033] FIG. 6 schematically shows a method for limiting a switchable load current according to one specific example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0034] An integrated circuit 1 for limiting a switchable load current according to one first specific embodiment of the present invention is shown in FIG. 2. Integrated circuit 1 includes a main transistor M1. Main transistor M1 is used to switch a load current for supplying an (external) load R.sub.L, which is represented here by a resistor. A source terminal of main transistor M1 is connected in this case with a first contact K1 and with a second contact K2 to an external electric line, in particular, to a supply voltage Vdd. First contact K1 in this example is present at a positive supply voltage Vdd. Load R.sub.L is correspondingly connected in series to main transistor M1.

[0035] Main transistor M1 is switchable between a conductive state, i.e., a low impedance state, and a non-conductive state, i.e., a high-impedance state. In the conductive state, a load current I.sub.L essentially flows through main transistor M1. Thus, this corresponds to drain source current I.sub.sd1 over the source drain path of main transistor M1, i.e., I.sub.L≈I.sub.sd1.

[0036] Integrated circuit 1 further includes a mirror transistor M2. Mirror transistor M2 is connected in parallel to main transistor M1 with respect to its source-drain path. A gate terminal of mirror transistor M2 is electrically connected to a gate terminal of main transistor M1. Furthermore, a source terminal of mirror transistor M2 is electrically connected to a source terminal of main transistor M1. The wiring ensures that the source gate voltage of the two transistors M1, M2 is identical, i.e., U.sub.sg2=U.sub.sg1 Main transistor M1 in this case is operated in the linear range, i.e., in the triode range. In this operating state, its source drain current I.sub.sd1 is not determined alone by source gate voltage U.sub.SG1 but primarily also by source drain voltage U.sub.SD1.

[0037] Integrated circuit 1 thus further includes a coupling circuit 10. The dashed lines in FIG. 2 indicating coupling circuit 10, as in the further figures, serve merely to better illustrate integrated circuit 1. Coupling circuit 10 is electrically connected to the drain terminals of main transistor M1 and of mirror transistor M2. Coupling circuit 10 is designed in such a way as to track or to set a source drain voltage U.sub.sd2 of mirror transistor M2 as a function of source drain voltage U.sub.sd1 of main transistor M1. In other words, source drain voltage U.sub.usd1 of main transistor M1 is forced over, or transferred to, mirror transistor M2. This dependency is preferably (in a first approximation) the following: U.sub.sd2=U.sub.sd1+U.sub.offs, where U.sub.offs may be positive, negative or 0. In particular specific embodiments, U.sub.sd2=U.sub.sd1 is preferred. The result of this dependency is that drain current I.sub.sd2 through mirror transistor M2 is, at least in a load current range, proportional to drain current I.sub.sd1 through main transistor M1. Drain current I.sub.sd2 through mirror transistor M2 thus represents a measure for the current flowing through main transistor M1. If drain current I.sub.sd1 through main transistor M1 increases, then drain current I.sub.sd2 through mirror transistor M2 increases accordingly. Preferred specific embodiments of the coupling circuits are described in the further figures.

[0038] A width-to-length ratio of main transistor M1 compared to a width-to-length ratio of mirror transistor M2 is greater by a factor α>1, preferably α≥10, even more preferably α≥100. This means, if first main transistor M1 has a width-to-length ratio of W.sub.a/L.sub.a, then mirror transistor M2 preferably has a width-to-length ratio of αW.sub.a/L.sub.a. At the same voltage U.sub.sd2=U.sub.sd1, such a dimensioning is the result of drain current I.sub.sd2 being less than drain current I.sub.sd1 by a factor α. As a result, a correspondingly smaller proportional current may be conducted in the current path through mirror transistor M2. A factor α≥100 is, in particular, advantageous, since as a result only a small current is branched off from main transistor M1. Mirror transistor M2 may thus be dimensioned to be correspondingly small.

[0039] Integrated circuit 1 further includes a gate control circuit 20. Gate control circuit 20 is electrically connected to the gate terminal of main transistor M1, or electrically connected to the shared gate terminal. With the aid of gate control circuit 20, it is possible to control, in particular, automatically control the gate voltage at main transistor M1. Gate control circuit 20 limits the load current through main switch M1 on the basis of the drain current through mirror transistor M2. The drain current through mirror transistor M2 is, as described above, proportional to the load current. As a result, a limitation may be carried out with the aid of the detection of this diverted current. Preferred examples thereof are described in greater detail below.

[0040] In the preferred specific embodiment described herein, coupling circuit 10 includes a first secondary transistor M3. First secondary transistor M3 is connected in series to mirror transistor M2. In other words, the source terminal of first secondary transistor N3 is electrically connected to the drain terminal of mirror transistor M2.

[0041] Coupling circuit 10 in this particular embodiment further includes a second secondary transistor M4. Second secondary transistor M4 is further diode-connected, i.e., it is designed as a transistor interconnected as a diode. Gate terminal and drain terminal are thus electrically connected to one another. Second secondary transistor M4 is thus consistently in the saturation range. Second secondary transistor M4 is further connected in series to main transistor M1. This means in other words that the drain terminal of main transistor M1 is electrically connected to the source terminal of second secondary transistor M4. A gate terminal of first secondary transistor M3 is further electrically connected to a gate terminal of second secondary transistor M4. Coupling circuit 10 further includes a current sink I.sub.1, which is connected to the drain terminal of second secondary transistor M4. This wiring ensures that a source gate voltage U.sub.sg4 forms over second secondary transistor M4 according to established value I.sub.s of first current sink I.sub.1. First current sink I.sub.1 may, for example, be designed as a further transistor.

[0042] Coupling circuit 10 enables a voltage coupling of the drain potentials. Mirror transistor M2 may, in particular, be operated via the voltage coupling in such a way that source drain voltage U.sub.sd2 of mirror transistor M2 is adapted as a function of source drain voltage U.sub.sd1 of main transistor M1. With similar dimensioning of secondary transistors M3, M4, in particular, drain source voltages U.sub.sd2 and U.sub.sd1 may be considered to be equivalent. The circuit complexity of this wiring is advantageously minimal.

[0043] A width-to-length ratio of first secondary transistor M3 compared to a width-to-length ratio of second secondary transistor M4 may further include a factor β, in particular, may be β≠1. This means, if first secondary transistor M3 has a width-to-length ratio of W.sub.b/L.sub.b, then second secondary transistor M4, may have a width-to-length ratio βW.sub.b/L.sub.b. For example, β may be a lighter correction value such as for example, in the range of 0.1 to 10 and may be used for the operation point correction or operation point optimization. As a result, the electrical circuit includes a further degree of freedom for dimensioning. Thus, via the factor beta, an offset, i.e., an offset voltage U.sub.offs, may be implemented. On the whole, source gate voltage U.sub.sg3 and thus also source drain voltage U.sub.sd2 of mirror transistor M2 may be a function of the drain current of mirror transistor I.sub.sd2.

[0044] Integrated circuit 1 further includes a measuring resistor R.sub.m, which is connected in series with the drain terminal of first secondary transistor M3. Thus, a measured current I.sub.M, which corresponds to drain current I.sub.sd2 and is thus proportional to the load current through mirror transistor M2, flows through measuring resistor R.sub.m.

[0045] Gate control circuit 20 in this embodiment includes an operational amplifier 22. A positive input of operational amplifier 22 in this case may be connected to the drain terminal of second secondary transistor M4. Thus, measured voltage U.sub.M over measuring resistor R.sub.m is present at this input. A negative input may be set to a reference voltage V.sub.ref, for example, with the aid of a voltage source V. The output of operational amplifier 22 may further be electrically connected to the gate terminal of first main transistor M1. Thus, a control circuit is implemented on the basis of drain current I.sub.sd2 through mirror transistor M2. In further specific embodiments of the present invention, it is provided that a timer circuit is provided, which will achieve a complete switch-off after a particular period of time, in which the maximum load current is flowing. This avoids an operation in the event of a permanent fault.

[0046] Operational amplifier 22 is further configured to regulate the gate terminal of main transistor M1 on the basis of the difference between measured voltage U.sub.m over measuring resistor R.sub.m and reference voltage U.sub.ref, so that measured voltage U.sub.m=U.sub.ref is set. In this way, maximum load current I.sub.Lmax in this embodiment is established. This maximum load current I.sub.Lmax may thus be established on the basis of U.sub.ref, R.sub.m, factors α and β and of current I.sub.s of current sink I.sub.1.

[0047] The described specific embodiment will be further discussed below with reference to illustrative examples, the present invention not being limited to these examples.

[0048] Measured current I.sub.M through measuring resistor R.sub.M is proportional to load current I.sub.L. The proportionality factor is determined by the establishment of coefficients α and β and by the establishment of current I.sub.1. For β=1 and I.sub.1=I.sub.L, for example, I.sub.sd2=I.sub.sd1/α or I.sub.M=I.sub.L/α is applicable.

[0049] For example, the current of current sink I.sub.1 may be set to maximum load current I.sub.Lmax: I.sub.s=I.sub.Lmax/α. With the aid of factor β, ratio I.sub.L/I.sub.M may be selected to be greater or smaller than α according to the generally known dependency of the drain source or source drain current of a MOS transistor on its drain source or source drain voltage in the triode range or in the linear range. This offers an additional degree of freedom in the dimensioning of the circuit.

[0050] Reference voltage U.sub.REF of voltage source V thus determines, together with the choice of measuring resistor R.sub.M, coefficients α and β and the choice of current I.sub.1, maximum load current I.sub.Lmax, which may flow through main transistor M.sub.1 operating as the switch. For β=1, I.sub.s=I.sub.Lmax/α0 and R.sub.M=U.sub.REF /I.sub.s, for example, I.sub.Lmax/α=U.sub.REF/R.sub.M is applicable.

[0051] I FIG. 3 shows an integrated circuit 1 according to one second specific embodiment. This specific embodiment is also a control circuit as described previously in FIG. 2. Only the differences with respect to FIG. 2 are described in greater detail below. For the similarities, reference is made to the description in FIG. 2.

[0052] In this specific embodiment, coupling circuit 10′ also includes a first secondary transistor M3, which is connected in series to mirror transistor M2. Coupling circuit 10′ further includes a first operational amplifier 12, inputs of first operational amplifier 12 being electrically connected to the drain terminals of main transistor M1 and of mirror transistor M2. In this specific example, a positive input of first operational amplifier 12 is electrically connected to the drain terminal of main transistor M1 and a negative input is connected to the drain terminal of mirror transistor M2. An output is electrically connected to the gate terminal of first secondary transistor M3. This embodiment has the advantage that a very exact setting of the drain source voltage or of the drain potentials at mirror transistor M2 may take place.

[0053] First operational amplifier 12 activates the gate terminal of first secondary transistor M3 in such a way that for mirror transistor M2, the same source drain voltage U.sub.sd2 results as for main transistor M1. This is achieved by first operational amplifier 12 adjusting its differential input voltage U.sub.D=U.sub.sd2−U.sub.sd1 between its positive and its negative input to U.sub.D=OV. Thus, in this specific embodiment, U.sub.sd2=U.sub.sd1 is always applicable. The setting of maximum load current I.sub.Lmax as a regulating point again takes place via the choice of measuring resistor R.sub.M, coefficient α as well as width-to-length ratio W/L of first secondary transistor M3. For further details, reference is made to the description for FIG. 2, which applies here as well.

[0054] FIG. 4 shows an integrated circuit 1 according to one third specific embodiment of the present invention. In this specific embodiment, no regulation of the load current takes place, rather a switch-off of the load current is implemented circuitry-wise. Coupling circuit 10 in this case is designed similarly to the embodiment described in FIG. 2. Thus, only the differences with respect to FIG. 2 are described and for similarities, reference is made to FIG. 2. These similarities, which are not expressly mentioned, may, however, also be applied here in specific embodiments of the present invention.

[0055] The integrated circuit further includes a second current sink I.sub.2. This second current sink I.sub.2 is electrically connected in this case to a drain terminal of first secondary transistor M3. Gate control circuit 20′ in this exemplary embodiment includes a comparator 24. Gate control circuit 20′ with comparator 24 switches the gate terminal in this case into a non-conuctive state when drain current I.sub.sd2 through mirror transistor M2 is greater than the current value of second current sink I.sub.2, identified in the figure by way of example with γI.sub.s, the present invention not being limited to a particular value of γ.

[0056] A positive input of comparator 24 in this case is connected to the drain terminal of first secondary transistor M3. A negative input is set to a reference voltage U.sub.ref. This may take place with the aid of an additional voltage source V. Thus, comparator 24 switches over when the voltage at the drain terminal is drawn above reference voltage U.sub.ref. In the present specific embodiment, this occurs when drain current I.sub.sd2 through mirror transistor M2 which, as a result of the coupling circuit, is proportional to load current I.sub.L through main transistor M1, is greater than the current value of second current sink I.sub.2. Gate control circuit 20′ may then switch the gate terminal into a non-conductive state. The current sink thus serves to establish a switch-over point on the basis of electrical currents, in particular, on the basis of scaled current I.sub.sd2 through mirror transistor M2. The proportionality of drain current I.sub.sd2 to the load current is thus utilized in order to define a switch-off point.

[0057] This will be described by way of example below for illustrative purposes. The gate terminals of secondary transistors M3, M4 are electrically connected to one another. In this way, it is possible, given a suitable choice of the width-to-length ratios W.sub.a/L.sub.a of main transistor M1 or W.sub.b/L.sub.b of second secondary transistor M4, and of coefficients α, β, and γ, to very exactly set in which load current I.sub.L secondary transistor M3 and M4 have the same source gate voltage U.sub.sg3 and U.sub.sg4. Secondary transistors M3 and M4 may then occupy the same operating point. As a result, source drain voltages U.sub.sd3 and U.sub.sd4 of the two secondary transistors M3 and M4 may also be identical. However, it is emphasized here that the present invention is not dependent on one specific choice of parameters, an exact dimensioning of circuit 1 may take place.

[0058] The significance of second current sink I.sub.2 is described in greater detail below. Current sink I.sub.2 may, for example, dissipate current I.sub.2=γI.sub.s, for example, when β≠1. In specific embodiments, γ may also assume the value 1. Given a suitable choice of the width-to-length ratios W.sub.a/L.sub.a or W.sub.b/L.sub.b as well as of coefficients α, β, and γ, mirror transistor M2 may provide current I.sub.Lmax/α according to the width-to-length ratio a of M1 and M2 directly proximate to the switch-over point of comparator 12. I.sub.Lmax in this case corresponds to the maximum allowable load current through main transistor M1 adjustable with the aid of the circuit parameters.

[0059] In the event that load current I.sub.L<I.sub.Lmax, equivalent to I.sub.sd2<γI.sub.s, first secondary transistor M2 is unable to provide the current that current sink I.sub.2 is able to dissipate. Consequently, the result is U.sub.SG3<U.sub.SG4 and the positive input of comparator 12 is drawn to ground by current sink 1.sub.2. In such a case, the output of comparator 12 would be, for example, LOW for I.sub.L<I.sub.Lmax or for I.sub.sd2<γI.sub.s.

[0060] If load current is I.sub.L>I.sub.Lmax, equivalent to I.sub.sd2>γI.sub.s, first secondary transistor M2 is able to provide more current than current sink I.sub.2 is able to dissipate. This therefore results in U.sub.SG3>U.sub.SG4 and the positive input of comparator 12 is drawn by mirror transistor M2 and first secondary transistor M3 to positive supply voltage V.sub.DD via reference voltage U.sub.REF of voltage source V1. As a result, the output of comparator 12, given a suitable choice of reference voltage U.sub.REF, is accordingly able to go to HIGH. An advantageous switch-off in the case of overcurrent may thus take place with the aid of the current path through mirror transistor M2.

[0061] The previous explanations are described merely for illustrating the present invention and limit the present invention neither to a PMOS logic, since the circuit may also be designed with NMOS transistors, nor to a particular selection of parameters. The dimensioning parameters in this case may be used for the optimization of the circuit and for the exact setting of I.sub.Lmax. An integrated circuit 1 according to one fourth specific embodiment of the present invention is shown in FIG. 5. The specific embodiment also describes a switch-off of main transistor M1 in the case of an excessively high load current as in FIG. 4. In contrast to FIG. 4, however, a coupling circuit 20′ described similarly to FIG. 3 is described. Thus, reference is made to the description content of the previous figures.

[0062] In addition to first secondary transistor M3, which is connected in series to mirror transistor M2, coupling circuit 10′ further includes a first operational amplifier 12, inputs of first operational amplifier 12 being electrically connected to the drain terminals of main transistor M1 and of mirror transistor M2. In this specific example, a positive input of first operational amplifier 12 is electrically connected to the drain terminal of main transistor M1 and the negative input is connected to the drain terminal of mirror transistor M2. An output is electrically connected to the gate terminal of first secondary transistor M3. This embodiment has the advantage that a current sink I.sub.1 may be omitted.

[0063] The gate control circuit is identical to that of FIG. 4 and reference is made to the description content of FIG. 4 above.

[0064] A method for limiting a switchable load current is further schematically described in FIG. 6. In a first step S1, the method includes the provision of a mirror transistor M2 and of a main transistor M1 switchable between a conductive state and a non-conductive state, through which in the conductive state a load current I.sub.L for supplying a load R.sub.L flows. A gate terminal of mirror transistor M2 is electrically connected to a gate terminal of main transistor M1 and a source terminal of mirror transistor M2 is electrically connected to a source terminal of main transistor M1.

[0065] In a second step S2, the tracking of the source drain voltage U.sub.sd2 of mirror transistor M2 takes place in a proportional dependence on source drain voltage U.sub.sd1 of main transistor M1.

[0066] In a third step S3, the limiting of a load current through main transistor M1 takes place on the basis of a drain current through mirror transistor M2.

[0067] The limiting may be a regulating or a switch-off, see in this regard also the description relating to FIGS. 1 through 4. The advantages of the method result in this case from the portions of the description described above. Further steps of the method may be derived from the above sections of the description of integrated circuit 1.

[0068] In summary, a current limitation, in particular, a current regulation or current switch-off is described in the present invention, in which a required detection of the current in the form of a proportional current is implemented without a shunt. This is achieved in that a mirror transistor M2 represents preferably a scaled version or a scaled-down copy of main transistor M1, which is activated in the same manner as main transistor M1 itself. The voltage drop over the main transistor is detected with the aid of a coupling circuit 10, 10′ and forced circuit-wise over scaled-down mirror transistor M2. This results in identical proportions, i.e., a proportionality for both main transistor M1 as well as for mirror transistor M2 both in the activation as well as with respect to the potentials. In this case, a shunt is omitted, but a precise detection of the current, which flows through main transistor M1, is nevertheless made possible. In addition, the evaluation electronics for limiting or switching off the load current are simplified.

[0069] Although the present invention has been illustrated and described in greater detail using preferred exemplary embodiments, the present invention is not limited by the described examples and other variations may be derived therefrom by those skilled in the art without departing from the scope of protection of the present invention.