POWER DETECTOR

Abstract

A power detector for detecting the RMS power of an AC voltage includes a transconductor configured to receive the AC voltage and to provide a first current to a node with a non-linear relation between the first current and the voltage. A current output digital to analog converter is configured to receive a digital signal and to provide a second current to the node. A low pass filter is coupled to the node, and an inverter is coupled to the node and configured to provide a binary signal.

Claims

1. An electronic circuit including a power detector for detecting RMS power of an AC voltage, the power detector comprising: a transconductor configured to receive the AC voltage and to provide a first current to a node with a non-linear relation between the first current and the AC voltage; a current output digital to analog converter configured to receive a digital signal and to provide a second current to the node; a low pass filter coupled to the node; and an inverter having an input coupled to the node and an output configured to provide a binary signal.

2. The electronic circuit according to claim 1, wherein the low pass filter comprises a first capacitor having an electrode coupled to the node.

3. The electronic circuit according to claim 2, wherein the first MOS transistor is an n-channel transistor having a drain connected to the node, a source connected to ground, and a gate coupled to the AC voltage.

4. The electronic circuit according to claim 3, wherein the gate of the first MOS transistor is capacitively coupled to the AC voltage through a capacitor, and is also coupled to receive a bias voltage.

5. The electronic circuit according to claim 1, wherein the transconductor comprises a first MOS transistor.

6. The electronic circuit according to claim 5, wherein the current output digital to analog converter comprises second MOS transistors and controllable switches, each second MOS transistor being coupled in series with one of the controllable switches, each controllable switch being controlled by one bit of the digital signal.

7. The electronic circuit according to claim 6, wherein the current output digital to analog converter further comprises a current source configured to provide a constant reference current and first current mirrors configured to copy the constant reference current multiplied by different multiplying factors to thereby generate the second current, each first current mirror comprising one of the second MOS transistors.

8. The electronic circuit according to claim 7, further comprising a diode mounted third MOS transistor, wherein a gate of the third MOS transistor is coupled to a gate of the first MOS transistor via a resistor and a second current mirror configured to copy the constant reference current to supply the third MOS transistor.

9. The electronic circuit according to claim 1, further comprising an electronic unit configured to receive the binary signal and to vary the digital signal until a toggling of the binary signal occurs.

10. The electronic circuit according to claim 9, wherein the electronic circuit is configured to define a radiofrequency receiver.

11. The electronic circuit electronic circuit according to claim 10, wherein the transconductor comprises a first MOS transistor; and further comprising an amplifier configured to receive a radiofrequency AC voltage and to amplify the radiofrequency AC voltage, wherein the amplifier is a transconductance amplifier comprising a fourth MOS transistor, and wherein the first MOS transistor is a scale replica of the fourth MOS transistor.

12. The electronic circuit according to claim 9, wherein the electronic circuit is configured to define a radiofrequency emitter.

13. The electronic circuit electronic circuit according to claim 12, wherein the transconductor comprises a first MOS transistor; and further comprising an amplifier configured to receive a radiofrequency AC voltage and to amplify the radiofrequency AC voltage, wherein the amplifier is a transconductance amplifier comprising a fourth MOS transistor, and wherein the first MOS transistor is a scale replica of the fourth MOS transistor.

14. A method for determining RMS power of an AC voltage using a power detector, the method comprising: receiving the AC voltage and providing a first current to a node with a non-linear relation between the first current and the AC voltage, using a transconductor; receiving a digital signal at a current output digital to analog converter and providing a second current to the node; low-pass filtering the node; inverting a voltage at the node to produce a binary signal; and varying the digital signal until toggling of the binary signal occurs.

15. The method according to claim 14, further comprising setting the AC voltage at a constant value, varying the digital signal until the toggling of the binary signal occurs, and storing the digital signal for which the binary signal has toggled.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0020] FIG. 1 partially and schematically shows an embodiment of a power detector;

[0021] FIG. 2 is a block diagram of an embodiment of a method for calibrating the power detector shown in FIG. 1;

[0022] FIG. 3 partially and schematically shows an embodiment of a current output Digital to Analog converter;

[0023] FIG. 4 partially and schematically shows another embodiment of a power detector;

[0024] FIG. 5 partially and schematically shows another embodiment of a power detector; and

[0025] FIG. 6 partially and schematically shows an embodiment of a radiofrequency receiver circuit.

DETAILED DESCRIPTION

[0026] Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional, and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

[0027] Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct electrical connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected, or that they can be coupled via one or more other elements. Further, a signal which alternates between a first constant state, for example, a low state, noted 0, and a second constant state, for example, a high state, noted 1, is called a binary signal. The high and low states of different binary signals of a same electronic circuit may be different. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state.

[0028] Unless specified otherwise, the expressions around, approximately, substantially and in the order of signify within 10%, and preferably within 5%. Further the expression substantially constant means which varies by less than 10% over time with respect to a reference value.

[0029] The RMS value of an AC signal is defined as the amount of DC signal required to produce an equivalent amount of heat in the same load. Therefore, the RMS voltage V.sub.rms of an AC voltage V is given by the following relation:

[00001]$\begin{array}{cc}{V}_{\mathrm{rms}}=\sqrt{\mathrm{avg}\left[V^2\left(t\right)\right]}& \left(1\right)\end{array}$

[0030] The power P(dBm) of an AC signal V, expressed in dBm, is given by the following relation:

[00002]$\begin{array}{cc}P\left(\mathrm{dBm}\right)=10{\log }_{10}\left(\frac{\frac{V_{\mathrm{rms}}^2}{50}}{1\mathrm{mW}}\right)=10{\log }_{10}\left(\frac{\frac{\mathrm{avg}\left[V_{\left(t\right)}^2\right]}{50}}{1\mathrm{mW}}\right)& \left(2\right)\end{array}$

[0031] According to an embodiment, the RMS power detector comprises, in order to realize the power detection of the input AC voltage, a transconductor receiving the input AC voltage and providing an output current and having a non-linear characteristic between the output current and the input voltage. The transconductor can be a metal-oxide-semiconductor field-effect transistor, called MOS transistor hereafter.

[0032] FIG. 1 partially and schematically shows an embodiment of a power detector 10 configured to determine the RMS power of a signal V.sub.RF, for example a radiofrequency AC voltage. Power detector 10 is coupled between a source of a high reference potential Vdd and a source of a low reference potential Gnd, for example the ground taken equal to 0V.

[0033] Power detector 10 comprises: an input IN receiving voltage V.sub.RF; an output OUT providing a binary voltage v.sub.OUT; a MOS transistor M0 , for example an N-channel MOS transistor, the source of transistor M0 being coupled or connected to the source of the low reference potential Gnd, the drain of transistor M0 being coupled or connected, to a node D; a current output Digital to Analog converter C-DAC controlled by a digital control signal S and coupled or connected, between node D and the source of the high reference potential Vdd; a resistor R coupled or connected, between the gate of transistor M0 and a source of a biasing voltage v.sub.bias; a first capacitor C.sub.RF coupled or connected, between input IN and the gate of transistor M0; a second capacitor C.sub.filt coupled or connected, between node D and the source of the low reference potential Gnd; and an inverter INV, the input of inverter INV being coupled or connected, to node D, and the output of inverter INV being coupled or connected to output OUT.

[0034] Power detector 10 is controlled by a control electronic circuit P, for example a microcontroller, receiving binary voltage v.sub.OUT and providing control signal S.

[0035] The operation of detector 10 is now described. The converter C-DAC provides a current i.sub.DAC at node D that depends on control signal S. Control signal S is a digital signal having N+1 bits S.sub.0 to S.sub.N, N being an integer for example greater than or equal to 3. Bit S.sub.0 is for example the least significant bit of control signal S. The current at the drain of transistor M0 is denoted as ?OUT and the gate-source voltage of transistor M0 is denoted as led V.sub.gs. The first derivative of current jour with respect to voltage V.sub.gs is denoted as gm and the second derivative of current i.sub.OUT with respect to voltage V.sub.gs is denoted as gm. When voltage V.sub.RF is equal to 0V, current i.sub.OUT is equal to a constant current i.sub.bias. The voltage across capacitor C.sub.filt is called v.sub.filt.

[0036] Without taking into account the filtering action of capacitor C.sub.filt, current i.sub.OUT is given by the following relation, neglecting the terms higher than the second order terms:

[00003]$\begin{array}{cc}{i}_{\mathrm{OUT}}=i_{\mathrm{bias}}+\mathrm{gm}.Math.v_{\mathrm{RF}}+{\mathrm{gm}}^{}.Math.v_{\mathrm{RF}}^2& \left(3\right)\end{array}$

[0037] When voltage V.sub.RF is a sinusoidal voltage with a pulsation @ and an maximum amplitude V.sub.RF, input voltage V.sub.RF is given by equation:

[00004]$\begin{array}{cc}{v}_{\mathrm{RF}}=V_{\mathrm{RF}}.Math.\cos \left(?t\right)& \left(4\right)\end{array}$

[0038] Equation 3 then becomes:

[00005]$\begin{array}{cc}{i}_{\mathrm{OUT}}=i_{\mathrm{bias}}+\mathrm{gm}.Math.V_{\mathrm{RF}}.Math.\cos \left(?t\right)+{\mathrm{gm}}^{}.Math.V_{\mathrm{RF}}^2.Math.{\left(\cos \left(?t\right)\right)}^2& \left(5\right)\end{array}$

[0039] Current i.sub.OUT is averaged by the filtering action of capacitor C.sub.filt, so that actual current i.sub.OUT is given by the following equation:

[00006]$\begin{array}{cc}{i}_{\mathrm{OUT}}=i_{\mathrm{bias}}+\frac{1}{2}{\mathrm{gm}}^{}.Math.V_{\mathrm{RF}}^2& \left(6\right)\end{array}$

[0040] In Equation 6 of current i.sub.OUT, the second term is proportional to the RMS power of voltage v.sub.RF. Detector 10 senses the DC amplitude of the second order distortion product generated by the non-linear characteristics of MOS transistor M0 by comparing current jour with current i.sub.DAC generated by converter C-DAC and by detecting when current i.sub.DAC is equal current i.sub.OUT.

[0041] According to an embodiment, converter C-DAC is controlled so that current i.sub.DAC is increased from a 0 A. Therefore, initially current i.sub.DAC is inferior to the maximum current jour than can be conducted by transistor M0 . Voltage v.sub.filt is therefore substantially at the low reference voltage Gnd. Voltage v.sub.OUT is at logical value 1. Control S is modified to increase current i.sub.DAC. As soon as current i.sub.DAC becomes superior to the maximum current i.sub.OUT than can be conducted by transistor M0 , voltage v.sub.filt is driven by transistor M0 and increases to be substantially equal to the high reference voltage Vdd minus the voltage across the converter C-DAC and is superior to the threshold of inverter INV. Voltage v.sub.filt therefore decreases instantly above the threshold of inverter INV so that voltage v.sub.OUT is at a low logical value 0. Therefore, voltage v.sub.OUT toggles from a high logical value 1 to a low logical value 0 when current i.sub.DAC is equal to current i.sub.OUT. The toggling of voltage v.sub.OUT is detected by control circuit P and the value S.sub.tog of control signal S for which voltage v.sub.OUT toggles from a high logical value 1 to a low logical value 0 is stored.

[0042] Since current i.sub.bias is known, the second term of Equation 6 can be determined.

[0043] Detector 10 compares in a single branch the drain current i.sub.OUT of transistor M0 with a calibrated current i.sub.DAC by using voltage V.sub.filt at node D that is a high-gain rail-to-rail node, so that the comparison can be performed by a simple inverter INV.

[0044] Transistor M0 can controlled in the active region, the triode region, or the weak inversion region. In the active region and the triode region, the relationship i.sub.ds/v.sub.gs is quadratic, with i.sub.ds being the drain to source current and v.sub.gs being the gate to source voltage. In the weak inversion region, the relationship i.sub.ds/v.sub.gs is exponential. In the active region, the triode region, or the weak inversion region, current i.sub.OUT carries a term linearly proportional to the RF RMS input power, so that the detection method previously described can be implemented.

[0045] Due to the mismatch of the components of detector 10, there may be an extra DC term i.sub.off that appears in the Equation 6 of current i.sub.OUT, which becomes the following:

[00007]$\begin{array}{cc}{i}_{\mathrm{OUT}}=i_{\mathrm{bias}}+\frac{1}{2}{\mathrm{gm}}^{}.Math.V_{\mathrm{RF}}^2+i_{\mathrm{off}}& \left(7\right)\end{array}$

[0046] FIG. 2 is a block diagram illustrating an embodiment of a calibration method of detector 10 to take into account the extra term i.sub.off.

[0047] At step 20, voltage v.sub.RF is set to 0V.

[0048] At step 22, converter C-DAC is controlled so that current i.sub.DAC is equal to 0A.

[0049] At step 24, voltage v.sub.OUT is observed. In case voltage v.sub.OUT is equal to high logical value 1 (Y), the method goes on to step 26. In case voltage v.sub.OUT is equal to low logical value 0 (N), the method continues at step 28.

[0050] At step 26, control signal S is increased, for example, by one bit. This leads to an increase of current i.sub.DAC. The method goes back at step 24 in which voltage v.sub.OUT is observed.

[0051] At step 28, the toggling of voltage v.sub.OUT is detected by control circuit P and the value S.sub.off of control value S is stored. Since voltage v.sub.OUT has just toggled from high logical value 1 to low logical value 0, current i.sub.DAC corresponding to stored control value S.sub.off is equal to the sum of i.sub.bias and i.sub.off.

[0052] According to another embodiment, the determination of value S.sub.off of control signal S can be made by a dichotomy algorithm.

[0053] When value S.sub.tog of control signal S for which voltage v.sub.OUT toggles from a high logical value 1 to a low logical value 0 is detected, the difference between values S.sub.tog and S.sub.off can be determined.

[0054] The method for determining control value S.sub.off can be implemented at the startup of the electronic device comprising detector 10. Values S.sub.off and S.sub.tog of control signal S can be used to determine the second term of Equation 6 that is proportional to the RMS power of voltage V.sub.RF.

[0055] The previously described method for determining control value S.sub.off advantageously does not require additional analog hardware to be implemented. Moreover, it advantageously does not require voltage v.sub.RF.

[0056] FIG. 3 shows an embodiment of current output Digital to Analog converter C-DAC.

[0057] Current output Digital to Analog converter C-DAC comprises: a current source CS providing a constant current I.sub.ref and having a first terminal coupled or connected to the source of the low reference potential Gnd; a MOS transistor M1, for an example a P channel MOS transistor, the source of transistor M1 being coupled or connected to the source of the high reference potential Vdd, the drain of transistor M1 being coupled or connected, to a second terminal of current source CS, and the gate of transistor M1 being coupled or connected, to the second terminal of current source CS; N+1 MOS transistors MC.sub.i, i being a integer varying from 0 to N, each transistor MC.sub.i being for example a P channel MOS transistor, the source of transistor MC.sub.i being coupled or connected to the source of the high reference potential Vdd, and the gate of transistor MC.sub.i being coupled or connected, to the gate of transistor M1; and N+1 controllable switches SW.sub.i, i being a integer varying from 0 to N, each switch SW.sub.i having a first terminal coupled or connected to the drain of transistor MC.sub.i and a second terminal coupled or connected to node D, each switch SW.sub.i being controlled by bit S.sub.i of control signal S.

[0058] Each transistor MC.sub.i has a size factor with respect to transistor M1 equal to 2.sup.i. This means that transistor MC.sub.0 has the same size as transistor M1 and that transistor MC.sub.N is 2.sup.N times bigger than transistor M1. Each transistor MC.sub.i forms a current mirror with transistor M1 and reproduces current I.sub.ref multiplied by a factor equal to 2.sup.i.

[0059] In an embodiment, switch SW.sub.i is closed when bit S.sub.i is at a high logical value 1 and is open when bit S.sub.i is at a low logical value 0. For example, switch SW.sub.i is a MOS transistor, for an example an N channel MOS transistor, the drain of the transistor being coupled or connected to the drain of transistor MC.sub.i, the source of the transistor being coupled or connected to node D, and the gate of the transistor receiving bit S.sub.i.

[0060] FIG. 4 partially and schematically shows another embodiment of a power detector 30. Power detector 30 shown in FIG. 4 comprises all the elements of power detector 10 shown in FIG. 1 except that transistor M0 is replaced by a transconductor T receiving input voltage V.sub.RF, and possibly biasing voltage v.sub.bias, and providing current i.sub.OUT. Transconductor has a non-linear relation between current jour and input voltage v.sub.RF. For example, transconductor T comprises a bipolar junction transistor.

[0061] FIG. 5 partially and schematically shows another embodiment of a power detector 40. Power detector 40 shown in FIG. 5 comprises all the elements of power detector 10 with converter C-DAC having the structure shown in FIG. 3. Power detector 40 further comprises: a transistor MOS M2, for example a P channel MOS transistor, the source of transistor M2 being coupled or connected to the source of the high reference potential Vdd, and the gate of transistor M2 being coupled or connected, to the gate of transistor M1; and a transistor MOS M3, for example a N channel MOS transistor, the source of transistor M3 being coupled or connected to the source of the low reference potential Gnd, the gate of transistor M3 being coupled or connected to resistor R and the drain of transistor M3 being coupled or connected to the drain of transistor M2 and to the gate of transistor M3.

[0062] In the embodiment shown in FIG. 5, the same current source CS is used to bias the converter C-DAC and to bias transistor M0 . This allows advantageously tracking of offset variations that depend on temperature.

[0063] An application of a power detector concerns a radiofrequency receiver or a radiofrequency emitter.

[0064] FIG. 6 is a schematic bloc diagram of a radiofrequency receiver 50 receiving ac voltage RFIN that can correspond to an ac voltage obtained from an antenna.

[0065] Receiver 50 comprises: a low noise amplifier 52 (LNA) receiving voltage RFIN and amplifying voltage RFIN; a down-conversion unit 54 that receives the amplified voltage provided by low noise amplifier 52 and that converts it down to the baseband frequency; a variable gain amplifier 56 (VGA) that amplifies the down-converted signal; an Analog to Digital converter 58 (ADC) that converts the down-converted and amplified signal into a digital signal V.sub.D; a power detector 60, that corresponds to any of power detectors 10, 30 or 40, receiving voltage RFIN and providing digital control values S.sub.off and S.sub.tog of control signal S upon the detection of the RMS power of voltage RFIN; and an automatic gain control circuit 62 (AGC), that can correspond to the control circuit P previously described, that sends control signal S to power detector 60, and that sends gain control signals G1, G2, G3 to low noise amplifier 52, variable gain amplifier 56, and/or Analog to Digital converter 58, that depend on the detected RMS power of voltage RFIN.

[0066] As a variation, instead of determining the RMS power of voltage RFIN power detector 60 can determine the RMS power of the amplified voltage provided by low noise amplifier 52.

[0067] According to an embodiment, low noise amplifier 52 comprises at least one MOS transistor.

[0068] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.

[0069] Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.