POWER SUPPLY FOR USE WITH ELECTRODYNAMIC SCREEN

Abstract

An AC power supply for connection to at least one electrode of an electrodynamic screen includes a DC-to-DC converter electrically coupled to a source of DC voltage including an output. The system includes a DC-to-AC converter electrically coupled to the output of the DC-to-DC converter, including a two-terminal passive element electrically coupled in series with a first transistor including a control terminal electrically coupled to a periodic voltage signal configured to switch the first transistor between an on/off state. The system includes an AC output including an AC voltage configured to change periodically. The system includes a regulator circuit configured to sample the AC output voltage and detect when the AC output voltage reaches a predetermined voltage. The regulator circuit is configured to electrically couple the power supply to the source of DC voltage when the output voltage is less than the predetermined voltage.

Claims

1. An AC power supply for connection to at least one electrode of an electrodynamic screen, the power supply comprising: a DC-to-DC converter electrically coupled to a source of DC voltage, the DC-to-DC converter further comprising an output of the DC-to-DC converter; a DC-to-AC converter electrically coupled to the output of the DC-to-DC converter, the DC-to-AC converter comprising a two-terminal passive element electrically coupled in series with a first transistor, the first transistor comprising a control terminal, wherein the control terminal of the first transistor is electrically coupled to a periodic voltage signal configured to switch the first transistor into an on state and an off state; an AC output, the AC output comprising an AC voltage configured to change periodically; a regulator circuit configured to sample the AC output voltage of the power supply, the regulator circuit further configured to detect when the AC output voltage reaches a predetermined voltage, and wherein; the regulator circuit is configured to electrically couple the power supply to the source of DC voltage when the output voltage is less than the predetermined voltage.

2. The power supply of claim 1, wherein the periodic voltage signal is configured to control the on/off state of the at least a transistor causes the AC output to transition periodically, at a predetermined frequency, between zero and a positive or negative voltage of a magnitude larger than zero.

3. The power supply of claim 2, wherein the periodic voltage signal comprises a frequency, the frequency configured to vary.

4. The power supply of claim 1, wherein the regulator circuit comprises a second transistor configured to connect and disconnect the power supply to the source of DC voltage.

5. The power supply of claim 1, wherein the DC-to-DC converter is a cascaded-boost converter.

6. The power supply of claim 2, wherein the second transistor is a p-channel MOSFET.

7. The power supply of claim 5, wherein the cascaded-boost converter operates in a discontinuous mode.

8. The power supply of claim 1, wherein the output voltage is applied to at least one electrode of an electrodynamic screen, the electrode comprising a capacitance electrically coupled in parallel with the AC output of the power supply.

9. The power supply of claim 1, wherein the periodic voltage signal configured to control the on/off state of the first transistor causes the AC output of the power supply to transition periodically between a positive voltage and a negative voltage.

10. The power supply of claim 9, wherein the periodic voltage signal comprises a frequency, the frequency configured to change over time.

11. The power supply of claim 1, wherein the periodic voltage is produced by an astable multivibrator.

12. The power supply of claim 1, wherein the AC output comprises a plurality of distinct AC outputs.

13. The power supply of claim 12, wherein the plurality of distinct AC outputs apply poly-phased voltages to a plurality of electrodes of an electrodynamic screen.

14. The power-supply circuits of claim 13, wherein the number of poly-phased voltages is between two and five.

15. The power supply of claim 1, wherein the AC output voltage of the power supply is configured to transition periodically between a voltage near zero and a voltage, wherein the voltage comprises a magnitude no larger than one kilovolt.

16. The power supply of claim 15, wherein the magnitude of the AC output voltage of the power supply is configured to increase in magnitude to a predetermined value that is larger than one kilovolt.

17. An analog hysteretic two-position regulator circuit for use with a power supply, the regulator circuit comprising: a Schmitt trigger comprising: an input to the Schmitt trigger, the input being derived from an output of a voltage sampling circuit electrically coupled to a power supply output; and an output from the Schmitt trigger; a first comparator comprising an input to the first comparator, the input to the first comparator electrically coupled to the output from the Schmitt trigger via a first resistor; a second comparator comprising an output from the second comparator, the output from the second comparator electrically coupled to the input to the Schmitt trigger via a second resistor, the second comparator further comprising: an input to the second comparator, the input to the second comparator electrically coupled to a periodic voltage signal; a resistor network electrically coupled to a power supply input voltage and a reference ground, the resistor network configured to provide a reference voltage, the reference voltage electrically coupled to a second input of the first comparator and a second input of the second comparator; a cascaded boost converter, the cascaded boost converter comprising an input voltage terminal; a transistor configured to switch between an on state and an off state, the transistor electrically coupled between the power supply input voltage and the input voltage terminal of the cascaded boost converter, the transistor comprising a control terminal, the control terminal electrically coupled to the output of the first comparator; and the transistor configured to switch to the on state in response to an output voltage of the cascaded boost convert, wherein the output voltage of the cascaded boost converter is below a predetermined threshold; and the transistor further configured to switch to the off state in response to an output voltage of the cascaded boost converter wherein the output voltage of the cascaded boost converter is above the predetermined threshold.

18. The regulator circuit of claim 17, wherein the regulator circuit further comprises a tunable, pulsed-output voltage regulation and timing system, the tunable, pulsed-output voltage regulation and timing system further comprising a cascaded-boost converter.

19. The regulator circuit of claim 17, wherein the regulator circuit comprises a plurality of distinct regulator circuits configured to be electrically coupled.

20. The regulator circuit of claim 19, wherein the regulator circuit comprises between two and five distinct regulator circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] A detailed description of various aspects, features, and embodiments of the subject matter described herein is provided with reference to the accompanying drawings, which are briefly described below. The drawings are illustrative and do not reflect the physical size of the disclosed circuitry. The drawings in schematic form illustrate various aspects and features of the present subject matter and may illustrate one or more embodiment(s) or example(s) of the present subject matter in whole or in part.

[0037] FIG. 1 is a diagram of a prior-art power supply.

[0038] FIG. 2 is a diagram of the overall configuration of the power supply incorporating aspects of the disclosed invention.

[0039] FIG. 3 is a schematic representation of a prior-art cascaded-boost converter driving a load.

[0040] FIG. 4 shows one implementation of the disclosed invention using a cascaded-boost converter.

[0041] FIGS. 5A and 5B show waveforms relevant to the circuit of FIG. 4.

[0042] FIG. 6 is a representation of one aspect of the disclosed invention wherein the power-supply module has a series output impedance.

[0043] FIG. 7 shows a version of the circuit incorporating an analog hysteretic feedback circuit.

[0044] FIG. 8 shows the details of one embodiment of the analog hysteretic feedback circuit of FIG. 7.

[0045] FIG. 9 illustrates exemplary waveforms for the circuit of FIG. 7.

[0046] FIG. 10 shows exemplary waveforms for a three-phase version of the disclosed power supply.

DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT

[0047] Reference will now be made in detail to exemplary embodiments of the disclosed subject matter, examples of which are illustrated in the accompanying drawings. The method and corresponding steps of the disclosed subject matter will be described in conjunction with the detailed description of the system.

[0048] The methods and systems presented herein may be used for producing poly-phase voltages at the kilovolt level over an approximate frequency range of 1 to 100 Hz. It is understood that voltages more than, or less than, one kilovolt are to be included within the scope of the invention. Likewise, AC voltage output frequencies within this general range, but higher or lower in frequency, are to be included within the scope of the invention. The disclosed power supply configuration is particularly suited for use in driving an electrodynamic screen for the purpose of removing dust particles from the surfaces of solar collectors. The deposition of such particles in a solar power plant can significantly reduce power output capability. For the purposes of this disclosure, a “power supply” is a device configured to supply electric power to an electrical load. Additionally or alternatively, a power supply may be configured to convert electric current from a source to the correct voltage, current and frequency to the electrical load. For example and without limitation, the power supply may be a standalone component or built into a larger system or plurality of connected components.

[0049] In FIG. 1, a prior-art power-supply module 100 is adapted to be connected to a source 101 of DC power that applies V.sub.DC to the V.sub.IN input 102 of the power-supply module. Power-supply module 100 produces an output voltage 103 (V.sub.OUT) that is applied across the terminals of load 104. Load 104 can be a resistor, capacitor, other circuit element, or any other circuit or electrical system requiring voltage. For the purposes of this disclosure, “electrically coupled” is the configuration referring to one or more components being connected by at least a conductor or means for transferring electrical energy.

[0050] For the purpose of explanation and illustration, and not limitation, an exemplary embodiment of the system in accordance with the disclosed subject matter is shown in FIG. 2. FIG. 2 shows additional elements added to power-supply module 100. These additional elements comprise portions of the disclosed invention. Regulator 105 is a circuit connected in series between one terminal of the input voltage source 101 and a corresponding terminal of the V.sub.IN input 102. Regulator 105 receives a voltage representative of V.sub.OUT 103 via feedback path 107 to communicate to regulator 105 the instantaneous value of output 103 for the purpose of regulating V.sub.OUT. A DC-to-AC converter circuit 106, connected at output terminals 108 of the DC-to-DC converter 100, acts to convert the voltage output of converter 100 into V.sub.AC, which constitutes an AC output 109 suitable for driving load 104. For the purposes of this disclosure, “terminal” is the point at which a conductor from a component, device or network comes to an end. Terminal may also refer to an electrical connector at this endpoint, acting as the reusable interface to a conductor and creating a point where external circuits can be connected. A terminal may simply be the end of a wire or it may be fitted with a connector or fastener.

[0051] FIG. 3 shows prior-art circuit 200 based on the topology of the cascaded-boost converter (CBC) known in the art. Circuit 200 comprises one prior-art embodiment of the DC-to-DC converter circuit 100 shown in FIG. 1. In FIG. 3, a first terminal of inductor L.sub.1 is connected to the anodes of diodes D.sub.1 and D.sub.2. A second terminal of L.sub.1 is adapted to be connected to one terminal of DC source. The cathode of D.sub.1 is connected to a first terminal of inductor L.sub.2, and the cathode of diode D.sub.2 is connected to a second terminal of inductor L.sub.2. Capacitor C.sub.1 is connected between the cathode of diode D.sub.1 and reference ground 205. Transistor M.sub.1, in this embodiment an n-channel, metal-oxide-semiconductor field-effect transistor (MOSFET), is connected between the cathode of diode D.sub.2 and reference ground 205. Transistor M.sub.1 operates as a switch.

[0052] For the purposes of this disclosure, a “transistor” is a semiconductor device configured to switch and/or amplify electrical signals and power. When configured as a switch, a transistor may include an “off” and “on” states or phases. Important parameters for this application include the current switched, the voltage handled, and the switching speed, characterized by the rise and fall times. Parameters are chosen such that the “off” output is limited to leakage currents may be too small to affect connected circuitry, the resistance of the transistor in the “on” state may be too small to affect circuitry, and the transition between the two states may be fast enough not to have a detrimental effect.

[0053] According to embodiments of the disclosed subject matter, transistors such as bipolar transistors may be used in switching applications, and requires biasing the transistor so that it operates between its cut-off region in the off-state and the saturation region (on). This requires sufficient base drive current. As the transistor provides current gain, it facilitates the switching of a relatively large current in the collector by a much smaller current into the base terminal. The ratio of these currents varies depending on the type of transistor, and even for a particular type, varies depending on the collector current.

[0054] For the purposes of this disclosure, a “switch” is an electrical component configured to disconnect or connect the conducting path in an electrical circuit, interrupting the electric current or diverting it from one conductor to another. According to embodiments of the present disclosure, a switch may include one or more switches or types of switches. For example and without limitation, a switch may include sets of contacts controlled by the same knob or actuator, and the contacts may operate simultaneously, sequentially, or alternately. A switch may be operated manually, for example, a light switch or a keyboard button, or may function as a sensing element. Many specialized forms exist, such as the push-button switch, reversing switch, relay, and circuit breaker. According to embodiments of the present subject matter, one or switches configured for use in high-powered circuits may have special construction to prevent destructive arcing when they are opened.

[0055] The anode of diode D.sub.3 is connected to the cathode of diode D.sub.2 and the second terminal of inductor L.sub.2. The cathode of diode D.sub.3 is connected to the positive (+) terminal of output voltage V.sub.OUT which is applied to load 104. Storage capacitor C.sub.2 is connected between the (+) side of TOUT and reference ground 205.

[0056] The control terminal of transistor M.sub.1, generally the gate terminal of a MOSFET, is driven by pulse-width-modulated (PWM) control signal 208. The PWM signal may be derived from one of any astable multi-vibrator circuits known in the art, for example from a 555-timer integrated circuit or microcontroller. For the purposes of this disclosure, the “pulse-width-modulated (PWM) control signal is a modulation technique that generates variable-width pulses to represent the amplitude of an input signal. For the purposes of this disclosure, an “astable multivibrator” includes two amplifying stages connected in a positive feedback loop by two capacitive-resistive coupling networks in which the circuit is not stable in either state, it continually switches from one state to the other. The circuit has two astable (unstable) states that change alternatively with maximum transition rate because of the “accelerating” positive feedback. It is implemented by the coupling capacitors that instantly transfer voltage changes because the voltage across a capacitor cannot suddenly change. In each state, one transistor is switched on and the other is switched off. Accordingly, one fully charged capacitor discharges (reverse charges) slowly thus converting the time into an exponentially changing voltage. At the same time, the other empty capacitor quickly charges thus restoring its charge (the first capacitor acts as a time-setting capacitor and the second prepares to play this role in the next state). The circuit operation is based on the fact that the forward-biased base-emitter junction of the switched-on bipolar transistor can provide a path for the capacitor restoration.

[0057] The load 104 is connected between the (+) and (−) terminals of the output V.sub.OUT. This load could be, among other things, a resistor, capacitor, inductor, any combination of these three elements, or an electronic circuit that requires power from power-supply module 200.

[0058] The operation of the cascaded-boost converter of FIG. 3 is known in the art. The circuit is generally analyzed as follows: For the time t.sub.on that switching transistor M.sub.1 is on, the change in current through inductors L.sub.1 and L.sub.2 can be expressed by:

[00001]$\begin{array}{cc}\Delta I_{L1}=\frac{V_{IN}}{L_1}DT,\Delta I_{L2}=\frac{v_{C1}}{L_2}DT,& \left(1\right)\end{array}$

where T is the period of the PWM signal and D=t.sub.on/T is the duty cycle, i.e., the percentage of time of the cycle that M.sub.1 is “on”. Similarly, for the time t.sub.off that transistor M.sub.1 is off, the change in current through inductors L.sub.1 and L.sub.2 can be expressed by:

[00002]$\begin{array}{cc}\Delta I_{L1}=\frac{V_{IN}-v_{C1}}{L_1}\left(1-D\right)T,\Delta I_{L2}=\frac{v_{C1}-V_{OUT}}{L_2}\left(1-D\right)T& \left(2\right)\end{array}$

These equations assume that the forward voltage drops across D.sub.1 and D.sub.2 are small relative to V.sub.IN and can be neglected in the calculations. Applying the principle of current balance to inductors L.sub.1 and L.sub.2 reveals that:

[00003]$V_{OUT}=\frac{V_{IN}}{{\left(1-D\right)}^2}$

which is the expected transfer function for two boost converters cascaded with each other. Of note is the fact that V.sub.OUT is larger in magnitude than V.sub.IN, because D<1. The preceding analysis is valid only when the CBC delivers sufficient current to the load. If the load 104 is represented, for the sake of analysis, as a resistor R.sub.LOAD, then current V.sub.OUT/R.sub.LOAD will flow into the load 104. The current flowing into R.sub.LOAD represents the current drawn by a power-consuming load connected across the V.sub.OUT terminals. If sufficient load current is not drawn by the load, then CBC 200 will perform essentially as a current source that continually increases the charge stored in output capacitor C.sub.2, thereby continually increasing output voltage 103.

[0059] It is known in the art that an EDS electrode can be modeled as a capacitive load. If CBC 200 drives an EDS, then output capacitor 111 (C.sub.2) will be connected in parallel with such a capacitive load. As noted above, the parallel combination of these capacitors will be continually charged, because the circuitry inside CBC 200 will act essentially as a current source charging the capacitances. If neither capacitor C.sub.2 nor the EDS-electrode capacitive load succumbs to breakdown due to overvoltage, output voltage 103 of the converter of FIG. 3 will be limited only by the reverse breakdown voltage of diode D.sub.3. Power losses in the circuit may also limit the charging of capacitor C.sub.2 and the EDS capacitance. For example and without limitation, the EDS may include a window, a solar/photovoltaic panel, a mirror, an electronic screen, lenses, telescopes, optical systems, portals, windows, electronic displays, and floors, or any application requiring the transport of particles.

[0060] According to Equations (1) and (2), when the load is capacitive, the load cannot draw sufficient current to maintain continuous-mode operation of the DC/AC converter 106. Thus the converter will operate in the discontinuous mode, wherein the current that flows into the parallel combination of C.sub.2 and the EDS load capacitance will depend on the input voltage V.sub.IN, the switching period T, and the duty cycle D of PWM signal 208. The converter currents will be inversely proportional to the inductance values of L.sub.1 and L.sub.2, as shown in Equations (1) and (2). The phenomenon of generating high voltages by continually charging a capacitive load is desirable for EDS applications, because voltages in the kilovolt range can be produced in this way. The problem remains that with no or very limited energy dissipative component to load 104, the voltage across C.sub.2 will rise to an undesirable magnitude unless other measures are taken.

[0061] The circuit of FIG. 4 shows one embodiment of the DC/AC converter 106 connected across terminals 108. Resistor 206, labeled R.sub.2, is connected in series with M.sub.2 transistor 207 which operates as a switch. The series combination of R.sub.2 and M.sub.2 is connected across terminals 108. In the embodiment of FIG. 4, M.sub.2 is a MOSFET, and the load is capacitor 110 (C.sub.LOAD). A periodic signal 203 (DCHRG), which generally has a much lower frequency than PWM signal 208 driving M.sub.1, is connected to the control terminal of M.sub.2, which is the gate of MOSFET 207 in the embodiment of FIG. 4. While FIG. 4 shows the source of MOSFET 207 connected to ground 205, and resistor 206 connected to the positive (+) V.sub.OUT terminal, an arrangement wherein the positions are reversed, with the drain of MOSFET 207 connected to the (+) V.sub.OUT terminal and the resistor 206 connected to ground 205, is also within the scope of the invention. Likewise, FIG. 4 shows M.sub.1 and M.sub.2 as n-channel MOSFETs, but appropriately connected p-channel MOSFETs or BJT devices could also be used.

[0062] When periodic signal DCHRG is high in FIG. 4, transistor M.sub.2 turns on (becomes conducting), effectively connecting R.sub.2 in parallel with C.sub.LOAD. This connection discharges any voltage across C.sub.LOAD with a time constant on the order of R.sub.2(C.sub.2+C.sub.LOAD), where C.sub.2 is capacitor 111. (It is known in the art the net capacitance of two capacitors connected in parallel is equal to their sum). When DCHRG is low, M.sub.2 turns off, effectively disconnecting R.sub.2 from the circuit. During this time interval, the capacitor C.sub.2 inside CBC 200 and C.sub.LOAD will be charged together by the circuitry of the CBC.

[0063] FIG. 5A generally shows the relationship over time between DCHRG and V.sub.OUT for the case were the voltage charging C.sub.LOAD has an output resistance. In some cases, the output of CBC 200 can be modeled as a current source of value I.sub.0. In such cases, C.sub.2 in parallel with C.sub.LOAD will be charged linearly with slope dv/dt=I.sub.0(C.sub.2+|C.sub.LOAD) during the off phase of M.sub.2. The resulting output voltage for this latter case is shown in FIG. 5B.

[0064] An important metric in the design of a CBC which drives a capacitive load is the time required for the output to rise from zero to some desired output voltage, for example, to 1.3 kV in one embodiment of relevance to the EDS. Because the average current that charges the combined (C.sub.2+C.sub.LOAD) is proportional to the duty cycle D and PWM period T (see Equation 1), the CBC can be modeled as having an equivalent “resistance” R.sub.S charging (C.sub.2+C.sub.LOAD) as follows:

[00004]$\begin{array}{cc}{R}_S\propto L\frac{1}{DT}& \left(4\right)\end{array}$

The time constant for charging C.sub.2 in the circuit of FIG. 4 can be expressed as:

[00005]$\begin{array}{cc}\tau =R_S\left(C_2+C_{\mathrm{LOAD}}\right)\propto L\frac{1}{DT}\left(C_2+C_{\mathrm{LOAD}}\right)& \left(5\right)\end{array}$

The values T=0.167 ms (f=6 kHz) and D=0.6 comprise exemplary parameters suitable for use in an EDS system, but other values are possible within the scope of the invention. These parameters can provide a good balance between the charging rate when DCHRG is low, and the power consumption that occurs when transistor M.sub.1 switches between its on and off states. These values are also favorable for reducing the effects of second-order parameters in the circuit, such as the internal series resistances of inductors L.sub.1 and L.sub.2, forward voltage drops of diodes D.sub.1, D.sub.2, and D.sub.3, and capacitor dissipation effects. Of note is the fact that the CBC will operate in the discontinuous conduction mode when the load current is too small to maintain continuous-mode operation. This phenomenon is consistent with traditional analysis outlined, for example, in Fundamentals of Power Electronics by Erickson and Maksimovic (Springer 2020).

[0065] FIG. 6 shows the above version of the DC/AC converter 106 connected to a more general version of DC-to-DC converter 100. Internal impedance 210 represents the series impedance Z.sub.S seen looking into the output terminals of DC-to-DC converter 100. In general, the magnitude of impedance 210 must be larger than the resistance of R.sub.2, typically (but not limited to) at least ten times larger. To the extent that Z.sub.S can be represented by a resistance R.sub.S, a metric for the charging of C.sub.LOAD in FIG. 6 will be the charging time-constant parameter R.sub.S(C.sub.LOAD+C.sub.2).

[0066] Referring now to FIG. 7, an analog-hysteretic, two-position feedback network 303 (AHFN), functioning as the regulator 105 shown in FIG. 2, is added to circuit 200 of FIG. 4 to produce modified circuit 300. The AHFN 303 regulates the peak output voltage so that it cannot rise above a predetermined level even if discharge signal 203 has not yet turned on transistor M.sub.2 to initiate the discharge of C.sub.2 and C.sub.LOAD. Feedback resistors R.sub.3 and R.sub.4 in FIG. 7 form a voltage divider 301 that produces a reduced version of V.sub.OUT by attenuating it to a level consistent with the limits of standard operational amplifiers or similar components, typically no larger than about 20 V. Because V.sub.OUT can be in the kilovolt range, this feature is necessary for proper operation of AHFN 303, as explained below. Note that R3 and R4 should be much larger than R.sub.2, a factor of at least ten times higher, to avoid R.sub.3 and R.sub.4 effecting the discharge time of C.sub.LOAD.

[0067] AHFN 303 establishes a connection between the input voltage source 101 and input 102 to the CBC, but only if output voltage 103 has not yet reached a predetermined value during the charging phase of C.sub.LOAD. Once the predetermined output voltage has been reached, AHFN 303 temporarily disconnects the CBC from input voltage source 101. Reconnection occurs once C.sub.LOAD has been discharged by resistor R.sub.2 via transistor M.sub.2. This discharging occurs during the “on” phase of M.sub.2.

[0068] Referring now to FIG. 8, details of one embodiment of AHFN 303 are shown. A signal 204 (CHRG) is applied to the gate of p-channel MOSFET M.sub.3, and signal 203 (DCHRG) is applied to both M.sub.2 and the V.sub.− input of circuit U.sub.2. Operation of the circuit over one period of V.sub.OUT is described as follows: Charging signal CHRG and discharge signal DCHRG both start in their low (“logic 0”) states. The low value of CHRG turns on p-channel MOSFET M.sub.3, thereby connecting input voltage V.sub.DC (101) to cascaded-boost converter 200. Resistor R.sub.2 is also disconnected from the circuit via MOSFET M.sub.2, because DCHRG is also low, thereby placing M.sub.2 in its off state. In one embodiment, the DCRHG signal may comprise a 5-Hz, 50-percent duty cycle waveform that proceeds regardless of the output of the feedback network comprising R.sub.3 and R.sub.4. In one embodiment, U.sub.1 is a Schmitt trigger whose output goes to its high (“logic 1”) when the feedback voltage between R.sub.3 and R.sub.4 rises to 10 V; U.sub.1 goes low again when the feedback voltage falls to 4 V. These values comprise the hysteresis voltages of Schmitt trigger U.sub.1 in the disclosed embodiment. Other values of these transition voltages can be used without departing from the intent of the invention.

[0069] For the purposes of this disclosure, a “Schmitt trigger” is a comparator circuit with hysteresis implemented by applying positive feedback to the non-inverting input of a comparator or differential amplifier. According to embodiments, a Schmitt trigger may be an active circuit which converts an analog input signal to a digital output signal. The Schmitt trigger may be a configured to include an output that retains its value until the input changes sufficiently to trigger a change. In a non-inverting configuration, when the input is higher than a chosen threshold, the output is high. According to embodiments, and further, configurations thereof, when the input is below a different (lower) chosen threshold the output is low, and when the input is between the two levels the output retains its value. This dual threshold action is called hysteresis and implies that the Schmitt trigger may possess a memory and can act as a bistable multivibrator (latch or flip-flop), in embodiments.

[0070] In embodiments, when the input to Schmitt trigger U.sub.1 is 12 V, the output of U.sub.1 is forced to its high output state (e.g., “logic 1”), causing three events occur: (1) The DCHRG signal is inverted by comparator U.sub.2; (2) the summation circuit formed by two same-valued resistors R.sub.ADD, with their midpoint connected to the (−) input of operational amplifier U.sub.3, then creates a voltage of 6 V at the V.sub.− inverting input of U.sub.3; and (3) the output of U.sub.3 switches to its high voltage output state, thus turning off p-channel MOSFET M.sub.3 connected between CBC 200 and DC source 101. For the purposes of this disclosure, “comparator” is a device that compares two or more voltages or currents, and outputs a signal indicating which is larger. A comparator may include one or more specialized high-gain differential amplifiers. The output of U.sub.3 is held high until DCHRG goes high, at which point M.sub.2 turns on and discharges C.sub.2 and any C.sub.LOAD connected in parallel with C.sub.2. Here again, C.sub.LOAD may represent an EDS capacitance. During this time interval, M.sub.2 will still be off, because the voltage at the noninverting input of U.sub.3 will still be large enough to force the output of U.sub.3 to its high voltage. Only when DCHRG again goes low does M.sub.3 turn back on. This operation ensures that the CBC will only charge C.sub.2 and C.sub.LOAD until the desired peak output voltage is reached. The resulting output 103 will thus take the form of a 50% duty cycle output, even though the CBC has only operated for a fraction of the portion of the cycle over which the output V.sub.OUT is high. FIG. 9 shows a typical output waveform derived from the circuit of FIG. 4 with the AHFN of FIG. 8 connected as in FIG. 7. The output waveform may correspond to the interdigitated electrodes disposed on or in the EDS. The electrodes may be configured to produce one or more traveling electrostatic fields, those in turn exerts a coulomb and other forces on deposited particles, thereby transporting the particles to one or more edges of the EDS. The traveling electrostatic field functions to clear the EDS of debris and increasing the effectiveness of the EDS, according to embodiments of the present subject matter. In solar applications, this clearing of particles substantially restores the power output of the collector, in embodiments wherein the EDS is a photovoltaic panel. The electrostatic field may charge the dust particles and remove the dust particles (or move to an acceptable degree and area) without the need for physical contact. In embodiments the process of removing dust from an EDS (i.e., soiling) may be controlled manually or automatedly by one or more computers, processors, systems, or combination thereof.

[0071] While the disclosed subject matter is described herein in terms of certain preferred embodiments, those skilled in the art will recognize that various modifications and improvements may be made to the disclosed subject matter without departing from the scope thereof. Moreover, although individual features of one embodiment of the disclosed subject matter may be discussed herein or shown in the drawings of the one embodiment and not in other embodiments, it should be apparent that individual features of one embodiment may be combined with one or more features of another embodiment or features from a plurality of embodiments.

[0072] In addition to the specific embodiments claimed below, the disclosed subject matter is also directed to other embodiments having any other possible combination of the dependent features claimed below and those disclosed above. As such, the particular features presented in the dependent claims and disclosed above can be combined with each other in other manners within the scope of the disclosed subject matter such that the disclosed subject matter should be recognized as also specifically directed to other embodiments having any other possible combinations. Thus, the foregoing description of specific embodiments of the disclosed subject matter has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosed subject matter to those embodiments disclosed.

[0073] It will be apparent to those skilled in the art that various modifications and variations can be made in the method and system of the disclosed subject matter without departing from the spirit or scope of the disclosed subject matter. Thus, it is intended that the disclosed subject matter include modifications and variations that are within the scope of the appended claims and their equivalents.